X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.h;h=7ed8caff4f949bcde015ae37efe4d8cda4a36c22;hb=f7be0e2b7adc4f6c4057f44f789bd7405844701c;hp=a289aa182e6f7ffd31ce6845482e4b0a540fd99b;hpb=0bbd14543fec5fd4f5664b676771812663235252;p=pcsx_rearmed.git

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index a289aa18..7ed8caff 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -16,6 +16,16 @@
 #define PCSX 1
 #define RAM_SIZE 0x200000
 
+#ifndef __ARM_ARCH_7A__
+#define ARMv5_ONLY
+//#undef CORTEX_A8_BRANCH_PREDICTION_HACK
+//#undef USE_MINI_HT
+#endif
+
+#ifndef __ANDROID__
+#define BASE_ADDR_FIXED 1
+#endif
+
 #ifdef FORCE32
 #define REG_SHIFT 2
 #else
@@ -48,8 +58,16 @@
 
 extern char *invc_ptr;
 
-#define BASE_ADDR 0x1000000 // Code generator target address
 #define TARGET_SIZE_2 24 // 2^24 = 16 megabytes
 
+// Code generator target address
+#ifdef BASE_ADDR_FIXED
+// "round" address helpful for debug
+#define BASE_ADDR 0x1000000
+#else
+extern char translation_cache[1 << TARGET_SIZE_2];
+#define BASE_ADDR translation_cache
+#endif
+
 // This is defined in linkage_arm.s, but gcc -O3 likes this better
 #define rdram ((unsigned int *)0x80000000)