X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fassem_arm.h;h=da4144dca8cdbb9fb4c4515666c7a1ed8dbee578;hb=cb4d282af668df3bdbd428be5a5ad26996cd0f4f;hp=0148a9530f0ba9ae8084ab11f94749bcaa1bbafb;hpb=a327ad27099341fb6eed61aa0419dff418429f96;p=pcsx_rearmed.git

diff --git a/libpcsxcore/new_dynarec/assem_arm.h b/libpcsxcore/new_dynarec/assem_arm.h
index 0148a953..da4144dc 100644
--- a/libpcsxcore/new_dynarec/assem_arm.h
+++ b/libpcsxcore/new_dynarec/assem_arm.h
@@ -17,18 +17,13 @@
 #define RAM_SIZE 0x200000
 
 #ifndef __ARM_ARCH_7A__
-#define ARMv5_ONLY
 //#undef CORTEX_A8_BRANCH_PREDICTION_HACK
 //#undef USE_MINI_HT
 #endif
 
 #ifndef BASE_ADDR_FIXED
-#ifndef __ANDROID__
-#define BASE_ADDR_FIXED 1
-#else
 #define BASE_ADDR_FIXED 0
 #endif
-#endif
 
 #ifdef FORCE32
 #define REG_SHIFT 2
@@ -69,6 +64,10 @@ extern char *invc_ptr;
 // "round" address helpful for debug
 #define BASE_ADDR 0x1000000
 #else
+#if defined(VITA)
+extern char* translation_cache;
+#else
 extern char translation_cache[1 << TARGET_SIZE_2];
-#define BASE_ADDR translation_cache
+#endif
+#define BASE_ADDR (u_int)translation_cache
 #endif