X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=962b338a88439b2cd6ea3362095de78fa05d1c4b;hb=ece032e6deb31bbbbe037c7d1dd630994d46b954;hp=72f18bff13dc018a283f694046cc93587b50054c;hpb=cf95b4f0e912b19298e38ae60dd66a9f4a773e9b;p=pcsx_rearmed.git diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index 72f18bff..962b338a 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -29,16 +29,13 @@ #ifdef _3DS #include <3ds_utils.h> #endif -#ifdef VITA -#include -static int sceBlock; -#endif #include "new_dynarec_config.h" #include "../psxhle.h" #include "../psxinterpreter.h" #include "../gte.h" #include "emu_if.h" // emulator interface +#include "arm_features.h" #define noinline __attribute__((noinline,noclone)) #ifndef ARRAY_SIZE @@ -53,6 +50,7 @@ static int sceBlock; //#define DISASM //#define ASSEM_PRINT +//#define STAT_PRINT #ifdef ASSEM_PRINT #define assem_debug printf @@ -79,9 +77,17 @@ static int sceBlock; #define MAXBLOCK 4096 #define MAX_OUTPUT_BLOCK_SIZE 262144 +#ifdef VITA +// apparently Vita has a 16MB limit, so either we cut tc in half, +// or use this hack (it's a hack because tc size was designed to be power-of-2) +#define TC_REDUCE_BYTES 4096 +#else +#define TC_REDUCE_BYTES 0 +#endif + struct ndrc_mem { - u_char translation_cache[1 << TARGET_SIZE_2]; + u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES]; struct { struct tramp_insns ops[2048 / sizeof(struct tramp_insns)]; @@ -114,6 +120,11 @@ enum stub_type { INVCODE_STUB = 14, }; +// regmap_pre[i] - regs before [i] insn starts; dirty things here that +// don't match .regmap will be written back +// [i].regmap_entry - regs that must be set up if someone jumps here +// [i].regmap - regs [i] insn will read/(over)write +// branch_regs[i].* - same as above but for branches, takes delay slot into account struct regstat { signed char regmap_entry[HOST_REGS]; @@ -121,8 +132,8 @@ struct regstat uint64_t wasdirty; uint64_t dirty; uint64_t u; - u_int wasconst; - u_int isconst; + u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true + u_int isconst; // ... but isconst is false when r2 is known u_int loadedconst; // host regs that have constants loaded u_int waswritten; // MIPS regs that were used as store base before }; @@ -170,23 +181,25 @@ static struct decoded_insn u_char rs2; u_char rt1; u_char rt2; - u_char lt1; + u_char use_lt1:1; u_char bt:1; - u_char likely:1; u_char ooo:1; u_char is_ds:1; + u_char is_jump:1; + u_char is_ujump:1; + u_char is_load:1; + u_char is_store:1; } dops[MAXBLOCK]; // used by asm: - u_char *out; struct ht_entry hash_table[65536] __attribute__((aligned(16))); struct ll_entry *jump_in[4096] __attribute__((aligned(16))); - struct ll_entry *jump_dirty[4096]; + static u_char *out; + static struct ll_entry *jump_dirty[4096]; static struct ll_entry *jump_out[4096]; static u_int start; static u_int *source; - static char insn[MAXBLOCK][10]; static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs static uint64_t gte_rt[MAXBLOCK]; static uint64_t gte_unneeded[MAXBLOCK]; @@ -199,7 +212,8 @@ static struct decoded_insn static u_int ba[MAXBLOCK]; static uint64_t unneeded_reg[MAXBLOCK]; static uint64_t branch_unneeded_reg[MAXBLOCK]; - static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i? + // see 'struct regstat' for a description + static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // contains 'real' consts at [i] insn, but may differ from what's actually // loaded in host reg as 'final' value is always loaded, see get_final_value() static uint32_t current_constmap[HOST_REGS]; @@ -207,9 +221,6 @@ static struct decoded_insn static struct regstat regs[MAXBLOCK]; static struct regstat branch_regs[MAXBLOCK]; static signed char minimum_free_regs[MAXBLOCK]; - static u_int needed_reg[MAXBLOCK]; - static u_int wont_dirty[MAXBLOCK]; - static u_int will_dirty[MAXBLOCK]; static int ccadj[MAXBLOCK]; static int slen; static void *instr_addr[MAXBLOCK]; @@ -224,10 +235,19 @@ static struct decoded_insn static void *copy; static int expirep; static u_int stop_after_jal; -#ifndef RAM_FIXED - static uintptr_t ram_offset; + static u_int f1_hack; +#ifdef STAT_PRINT + static int stat_bc_direct; + static int stat_bc_pre; + static int stat_bc_restore; + static int stat_jump_in_lookups; + static int stat_restore_tries; + static int stat_restore_compares; + static int stat_inv_addr_calls; + static int stat_inv_hits; + #define stat_inc(s) s++ #else - static const uintptr_t ram_offset=0; + #define stat_inc(s) #endif int new_dynarec_hacks; @@ -242,8 +262,8 @@ static struct decoded_insn extern int pcaddr; extern int pending_exception; extern int branch_target; + extern uintptr_t ram_offset; extern uintptr_t mini_ht[32][2]; - extern u_char restore_candidate[512]; /* registers that may be allocated */ /* 1-31 gpr */ @@ -254,7 +274,7 @@ static struct decoded_insn #define CCREG 36 // Cycle count #define INVCP 37 // Pointer to invalid_code //#define MMREG 38 // Pointer to memory_map -//#define ROREG 39 // ram offset (if rdram!=0x80000000) +#define ROREG 39 // ram offset (if rdram!=0x80000000) #define TEMPREG 40 #define FTEMP 40 // FPU temporary register #define PTEMP 41 // Prefetch temporary register @@ -292,7 +312,7 @@ static struct decoded_insn //#define FLOAT 19 // Floating point unit //#define FCONV 20 // Convert integer to float //#define FCOMP 21 // Floating point compare (sets FSREG) -#define SYSCALL 22// SYSCALL +#define SYSCALL 22// SYSCALL,BREAK #define OTHER 23 // Other #define SPAN 24 // Branch/delay slot spans 2 pages #define NI 25 // Not implemented @@ -315,7 +335,6 @@ int new_recompile_block(u_int addr); void *get_addr_ht(u_int vaddr); void invalidate_block(u_int block); void invalidate_addr(u_int addr); -void remove_hash(int vaddr); void dyna_linker(); void dyna_linker_ds(); void verify_code(); @@ -323,18 +342,27 @@ void verify_code_ds(); void cc_interrupt(); void fp_exception(); void fp_exception_ds(); +void jump_syscall (u_int u0, u_int u1, u_int pc); +void jump_syscall_ds(u_int u0, u_int u1, u_int pc); +void jump_break (u_int u0, u_int u1, u_int pc); +void jump_break_ds(u_int u0, u_int u1, u_int pc); void jump_to_new_pc(); void call_gteStall(); +void add_jump_out(u_int vaddr, void *src); void new_dyna_leave(); +static void *get_clean_addr(void *addr); +static void get_bounds(void *addr, u_char **start, u_char **end); +static void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr); + // Needed by assembler -static void wb_register(signed char r,signed char regmap[],uint64_t dirty); -static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty); -static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr); -static void load_all_regs(signed char i_regmap[]); -static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]); +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty); +static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty); +static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr); +static void load_all_regs(const signed char i_regmap[]); +static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]); static void load_regs_entry(int t); -static void load_all_consts(signed char regmap[],u_int dirty,int i); +static void load_all_consts(const signed char regmap[], u_int dirty, int i); static u_int get_host_reglist(const signed char *regmap); static int verify_dirty(const u_int *ptr); @@ -344,7 +372,8 @@ static void add_stub(enum stub_type type, void *addr, void *retaddr, static void add_stub_r(enum stub_type type, void *addr, void *retaddr, int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist); static void add_to_linker(void *addr, u_int target, int ext); -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override); +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override); static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host); static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist); @@ -352,6 +381,14 @@ static void pass_args(int a0, int a1); static void emit_far_jump(const void *f); static void emit_far_call(const void *f); +#ifdef VITA +#include +static int sceBlock; +// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c +extern int getVMBlock(); +int _newlib_vm_size_user = sizeof(*ndrc); +#endif + static void mprotect_w_x(void *start, void *end, int is_x) { #ifdef NO_WRITE_EXEC @@ -463,30 +500,18 @@ static void do_clear_cache(void) #define NO_CYCLE_PENALTY_THR 12 -int cycle_multiplier; // 100 for 1.0 +int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0 int cycle_multiplier_override; int cycle_multiplier_old; +static int cycle_multiplier_active; static int CLOCK_ADJUST(int x) { - int m = cycle_multiplier_override - ? cycle_multiplier_override : cycle_multiplier; - int s=(x>>31)|1; + int m = cycle_multiplier_active; + int s = (x >> 31) | 1; return (x * m + s * 50) / 100; } -// is the op an unconditional jump? -static int is_ujump(int i) -{ - return dops[i].itype == UJUMP || dops[i].itype == RJUMP - || (source[i] >> 16) == 0x1000; // beq r0, r0, offset // b offset -} - -static int is_jump(int i) -{ - return dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP; -} - static int ds_writes_rjump_rs(int i) { return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2); @@ -521,6 +546,21 @@ static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr) ht_bin->tcaddr[0] = tcaddr; } +static void mark_valid_code(u_int vaddr, u_int len) +{ + u_int i, j; + vaddr &= 0x1fffffff; + for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) { + // ram mirrors, but should not hurt bios + for (j = 0; j < 0x800000; j += 0x200000) { + invalid_code[(i|j) >> 12] = + invalid_code[(i|j|0x80000000u) >> 12] = + invalid_code[(i|j|0xa0000000u) >> 12] = 0; + } + } + inv_code_start = inv_code_end = ~0; +} + // some messy ari64's code, seems to rely on unsigned 32bit overflow static int doesnt_expire_soon(void *tcaddr) { @@ -528,59 +568,100 @@ static int doesnt_expire_soon(void *tcaddr) return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2))); } +void *ndrc_try_restore_block(u_int vaddr) +{ + u_char *source_start = NULL, *source_end = NULL; + void *found_stub = NULL, *found_clean = NULL; + u_int len, page = get_page(vaddr); + const struct ll_entry *head; + int ep_count = 0; + + stat_inc(stat_restore_tries); + for (head = jump_dirty[page]; head != NULL; head = head->next) + { + if (head->vaddr != vaddr) + continue; + // don't restore blocks which are about to expire from the cache + if (!doesnt_expire_soon(head->addr)) + continue; + stat_inc(stat_restore_compares); + if (!verify_dirty(head->addr)) + continue; + + found_stub = head->addr; + break; + } + if (!found_stub) + return NULL; + + found_clean = get_clean_addr(found_stub); + get_bounds(found_stub, &source_start, &source_end); + assert(source_start < source_end); + len = source_end - source_start; + mark_valid_code(vaddr, len); + + // restore all entry points + for (head = jump_dirty[page]; head != NULL; head = head->next) + { + if (head->vaddr < vaddr || head->vaddr >= vaddr + len) + continue; + + u_char *start = NULL, *end = NULL; + get_bounds(head->addr, &start, &end); + if (start != source_start || end != source_end) + continue; + + void *clean_addr = get_clean_addr(head->addr); + ll_add_flags(jump_in + page, head->vaddr, head->reg_sv_flags, clean_addr); + + int in_ht = 0; + struct ht_entry *ht_bin = hash_table_get(head->vaddr); + if (ht_bin->vaddr[0] == head->vaddr) { + ht_bin->tcaddr[0] = clean_addr; // Replace existing entry + in_ht = 1; + } + if (ht_bin->vaddr[1] == head->vaddr) { + ht_bin->tcaddr[1] = clean_addr; // Replace existing entry + in_ht = 1; + } + if (!in_ht) + hash_table_add(ht_bin, head->vaddr, clean_addr); + ep_count++; + } + inv_debug("INV: Restored %08x %p (%d)\n", vaddr, found_stub, ep_count); + stat_inc(stat_bc_restore); + return found_clean; +} + // Get address from virtual address // This is called from the recompiled JR/JALR instructions void noinline *get_addr(u_int vaddr) { - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); + u_int page = get_page(vaddr); struct ll_entry *head; - //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page); - head=jump_in[page]; - while(head!=NULL) { - if(head->vaddr==vaddr) { - //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr); + void *code; + + stat_inc(stat_jump_in_lookups); + for (head = jump_in[page]; head != NULL; head = head->next) { + if (head->vaddr == vaddr) { hash_table_add(hash_table_get(vaddr), vaddr, head->addr); return head->addr; } - head=head->next; } - head=jump_dirty[vpage]; - while(head!=NULL) { - if(head->vaddr==vaddr) { - //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr); - // Don't restore blocks which are about to expire from the cache - if (doesnt_expire_soon(head->addr)) - if (verify_dirty(head->addr)) { - //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]); - invalid_code[vaddr>>12]=0; - inv_code_start=inv_code_end=~0; - if(vpage<2048) { - restore_candidate[vpage>>3]|=1<<(vpage&7); - } - else restore_candidate[page>>3]|=1<<(page&7); - struct ht_entry *ht_bin = hash_table_get(vaddr); - if (ht_bin->vaddr[0] == vaddr) - ht_bin->tcaddr[0] = head->addr; // Replace existing entry - else - hash_table_add(ht_bin, vaddr, head->addr); + code = ndrc_try_restore_block(vaddr); + if (code) + return code; - return head->addr; - } - } - head=head->next; - } - //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr); - int r=new_recompile_block(vaddr); - if(r==0) return get_addr(vaddr); - // Execute in unmapped page, generate pagefault execption + int r = new_recompile_block(vaddr); + if (r == 0) + return get_addr(vaddr); + + // generate an address error Status|=2; - Cause=(vaddr<<31)|0x8; + Cause=(vaddr<<31)|(4<<2); EPC=(vaddr&1)?vaddr-5:vaddr; BadVAddr=(vaddr&~1); - Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0); - EntryHi=BadVAddr&0xFFFFE000; - return get_addr_ht(0x80000000); + return get_addr_ht(0x80000080); } // Look up address in hash table first void *get_addr_ht(u_int vaddr) @@ -592,16 +673,48 @@ void *get_addr_ht(u_int vaddr) return get_addr(vaddr); } -void clear_all_regs(signed char regmap[]) +static void clear_all_regs(signed char regmap[]) +{ + memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS); +} + +// get_reg: get allocated host reg from mips reg +// returns -1 if no such mips reg was allocated +#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11 + +extern signed char get_reg(const signed char regmap[], signed char r); + +#else + +static signed char get_reg(const signed char regmap[], signed char r) { int hr; - for (hr=0;hr host +#define RRMAP_SIZE 64 +static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE], + u_int *regs_can_change) +{ + u_int r, hr, hr_can_change = 0; + memset(rrmap, -1, RRMAP_SIZE); + for (hr = 0; hr < HOST_REGS; ) + { + r = regmap[hr]; + rrmap[r & (RRMAP_SIZE - 1)] = hr; + // only add mips $1-$31+$lo, others shifted out + hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32)); + hr++; + if (hr == EXCLUDE_REG) + hr++; + } + hr_can_change |= 1u << (rrmap[33] & 31); + hr_can_change |= 1u << (rrmap[CCREG] & 31); + hr_can_change &= ~(1u << 31); + *regs_can_change = hr_can_change; +} + +// same as get_reg, but takes rrmap +static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r) +{ + assert(0 <= r && r < RRMAP_SIZE); + return rrmap[r]; +} + +static int count_free_regs(const signed char regmap[]) { int count=0; int hr; @@ -626,70 +769,62 @@ int count_free_regs(signed char regmap[]) return count; } -void dirty_reg(struct regstat *cur,signed char reg) +static void dirty_reg(struct regstat *cur, signed char reg) { int hr; - if(!reg) return; - for (hr=0;hrregmap[hr]&63)==reg) { - cur->dirty|=1<regmap, reg); + if (hr >= 0) + cur->dirty |= 1<regmap[hr]==reg) { - cur->isconst|=1<regmap, reg); + if (hr >= 0) { + cur->isconst |= 1<regmap[hr]&63)==reg) { - cur->isconst&=~(1<regmap, reg); + if (hr >= 0) + cur->isconst &= ~(1<regmap[hr]&63)==reg) { - return (cur->isconst>>hr)&1; - } - } + if (reg < 0) return 0; + if (!reg) return 1; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return (cur->isconst>>hr)&1; return 0; } -static uint32_t get_const(struct regstat *cur, signed char reg) +static uint32_t get_const(const struct regstat *cur, signed char reg) { int hr; - if(!reg) return 0; - for (hr=0;hrregmap[hr]==reg) { - return current_constmap[hr]; - } - } - SysPrintf("Unknown constant in r%d\n",reg); + if (!reg) return 0; + hr = get_reg(cur->regmap, reg); + if (hr >= 0) + return current_constmap[hr]; + + SysPrintf("Unknown constant in r%d\n", reg); abort(); } // Least soon needed registers // Look at the next ten instructions and see which registers // will be used. Try not to reallocate these. -void lsn(u_char hsn[], int i, int *preferred_reg) +static void lsn(u_char hsn[], int i, int *preferred_reg) { int j; int b=-1; @@ -699,7 +834,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -717,11 +852,12 @@ void lsn(u_char hsn[], int i, int *preferred_reg) hsn[dops[i+j].rs1]=j; hsn[dops[i+j].rs2]=j; } + if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store)) + hsn[ROREG] = j; // On some architectures stores need invc_ptr #if defined(HOST_IMM8) - if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR || (dops[i+j].opcode&0x3b)==0x39 || (dops[i+j].opcode&0x3b)==0x3a) { - hsn[INVCP]=j; - } + if (dops[i+j].is_store) + hsn[INVCP] = j; #endif if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP)) { @@ -747,7 +883,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) // TODO: preferred register based on backward branch } // Delay slot should preferably not overwrite branch conditions or cycle count - if (i > 0 && is_jump(i-1)) { + if (i > 0 && dops[i-1].is_jump) { if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1; if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1; hsn[CCREG]=1; @@ -756,7 +892,7 @@ void lsn(u_char hsn[], int i, int *preferred_reg) hsn[RHTBL]=1; } // Coprocessor load/store needs FTEMP, even if not declared - if(dops[i].itype==C1LS||dops[i].itype==C2LS) { + if(dops[i].itype==C2LS) { hsn[FTEMP]=0; } // Load L/R also uses FTEMP as a temporary register @@ -776,13 +912,13 @@ void lsn(u_char hsn[], int i, int *preferred_reg) } // We only want to allocate registers if we're going to use them again soon -int needed_again(int r, int i) +static int needed_again(int r, int i) { int j; int b=-1; int rn=10; - if (i > 0 && is_ujump(i-1)) + if (i > 0 && dops[i-1].is_ujump) { if(ba[i-1]start+slen*4-4) return 0; // Don't need any registers if exiting the block @@ -793,7 +929,7 @@ int needed_again(int r, int i) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -821,7 +957,7 @@ int needed_again(int r, int i) // Try to match register allocations at the end of a loop with those // at the beginning -int loop_reg(int i, int r, int hr) +static int loop_reg(int i, int r, int hr) { int j,k; for(j=0;j<9;j++) @@ -830,7 +966,7 @@ int loop_reg(int i, int r, int hr) j=slen-i-1; break; } - if (is_ujump(i+j)) + if (dops[i+j].is_ujump) { // Don't go past an unconditonal jump j++; @@ -863,20 +999,20 @@ int loop_reg(int i, int r, int hr) // Allocate every register, preserving source/target regs -void alloc_all(struct regstat *cur,int i) +static void alloc_all(struct regstat *cur,int i) { int hr; for(hr=0;hrregmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&& - ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2)) + if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&& + (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2)) { cur->regmap[hr]=-1; cur->dirty&=~(1<regmap[hr]&63)==0) + if(cur->regmap[hr]==0) { cur->regmap[hr]=-1; cur->dirty&=~(1<reg_sv_flags=reg_sv_flags; @@ -1023,7 +1163,7 @@ void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr // Check if an address is already compiled // but don't return addresses which are about to expire from the cache -void *check_addr(u_int vaddr) +static void *check_addr(u_int vaddr) { struct ht_entry *ht_bin = hash_table_get(vaddr); size_t i; @@ -1067,7 +1207,7 @@ void *check_addr(u_int vaddr) return 0; } -void remove_hash(int vaddr) +static void remove_hash(int vaddr) { //printf("remove hash: %x\n",vaddr); struct ht_entry *ht_bin = hash_table_get(vaddr); @@ -1106,7 +1246,7 @@ static void ll_remove_matching_addrs(struct ll_entry **head, } // Remove all entries from linked list -void ll_clear(struct ll_entry **head) +static void ll_clear(struct ll_entry **head) { struct ll_entry *cur; struct ll_entry *next; @@ -1146,6 +1286,7 @@ static void invalidate_page(u_int page) struct ll_entry *head; struct ll_entry *next; head=jump_in[page]; + if (head) stat_inc(stat_inv_hits); jump_in[page]=0; while(head!=NULL) { inv_debug("INVALIDATE: %x\n",head->vaddr); @@ -1225,6 +1366,7 @@ void invalidate_addr(u_int addr) //static int rhits; // this check is done by the caller //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; } + stat_inc(stat_inv_addr_calls); u_int page=get_vpage(addr); if(page<2048) { // RAM struct ll_entry *head; @@ -1284,11 +1426,6 @@ void invalidate_all_pages(void) u_int page; for(page=0;page<4096;page++) invalidate_page(page); - for(page=0;page<1048576;page++) - if(!invalid_code[page]) { - restore_candidate[(page&2047)>>3]|=1<<(page&7); - restore_candidate[((page&2047)>>3)+256]|=1<<(page&7); - } #ifdef USE_MINI_HT memset(mini_ht,-1,sizeof(mini_ht)); #endif @@ -1318,55 +1455,6 @@ void add_jump_out(u_int vaddr,void *src) //inv_debug("add_jump_out: to %p\n",get_pointer(src)); } -// If a code block was found to be unmodified (bit was set in -// restore_candidate) and it remains unmodified (bit is clear -// in invalid_code) then move the entries for that 4K page from -// the dirty list to the clean list. -void clean_blocks(u_int page) -{ - struct ll_entry *head; - inv_debug("INV: clean_blocks page=%d\n",page); - head=jump_dirty[page]; - while(head!=NULL) { - if(!invalid_code[head->vaddr>>12]) { - // Don't restore blocks which are about to expire from the cache - if (doesnt_expire_soon(head->addr)) { - if(verify_dirty(head->addr)) { - u_char *start, *end; - //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr); - u_int i; - u_int inv=0; - get_bounds(head->addr, &start, &end); - if (start - rdram < RAM_SIZE) { - for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) { - inv|=invalid_code[i]; - } - } - else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) { - inv=1; - } - if(!inv) { - void *clean_addr = get_clean_addr(head->addr); - if (doesnt_expire_soon(clean_addr)) { - u_int ppage=page; - inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr); - //printf("page=%x, addr=%x\n",page,head->vaddr); - //assert(head->vaddr>>12==(page|0x80000)); - ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr); - struct ht_entry *ht_bin = hash_table_get(head->vaddr); - if (ht_bin->vaddr[0] == head->vaddr) - ht_bin->tcaddr[0] = clean_addr; // Replace existing entry - if (ht_bin->vaddr[1] == head->vaddr) - ht_bin->tcaddr[1] = clean_addr; // Replace existing entry - } - } - } - } - } - head=head->next; - } -} - /* Register allocation */ // Note: registers are allocated clean (unmodified state) @@ -1374,18 +1462,19 @@ void clean_blocks(u_int page) static void alloc_reg(struct regstat *cur,int i,signed char reg) { int r,hr; - int preferred_reg = (reg&7); - if(reg==CCREG) preferred_reg=HOST_CCREG; - if(reg==PTEMP||reg==FTEMP) preferred_reg=12; + int preferred_reg = PREFERRED_REG_FIRST + + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1); + if (reg == CCREG) preferred_reg = HOST_CCREG; + if (reg == PTEMP || reg == FTEMP) preferred_reg = 12; + assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS); + assert(reg >= 0); // Don't allocate unused registers if((cur->u>>reg)&1) return; // see if it's already allocated - for(hr=0;hrregmap[hr]==reg) return; - } + if (get_reg(cur->regmap, reg) >= 0) + return; // Keep the same mapping if the register was already allocated in a loop preferred_reg = loop_reg(i,reg,preferred_reg); @@ -1420,28 +1509,47 @@ static void alloc_reg(struct regstat *cur,int i,signed char reg) if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;} } } + // Try to allocate any available register, but prefer // registers that have not been used recently. - if(i>0) { - for(hr=0;hrregmap[hr]==-1) { - if(regs[i-1].regmap[hr]!=dops[i-1].rs1&®s[i-1].regmap[hr]!=dops[i-1].rs2&®s[i-1].regmap[hr]!=dops[i-1].rt1&®s[i-1].regmap[hr]!=dops[i-1].rt2) { + if (i > 0) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { + int oldreg = regs[i-1].regmap[hr]; + if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2 + && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2)) + { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<regmap[hr]==-1) { + for (hr = PREFERRED_REG_FIRST; ; ) { + if (cur->regmap[hr] < 0) { cur->regmap[hr]=reg; cur->dirty&=~(1<isconst&=~(1<2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(dops[i-2].itype==RJUMP||dops[i-2].itype==UJUMP||dops[i-2].itype==CJUMP||dops[i-2].itype==SJUMP)) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { // Alloc preferred register if available if(hsn[r=cur->regmap[preferred_reg]&63]==j) { for(hr=0;hrregmap[hr]&63)==r) { + if(cur->regmap[hr]==r) { cur->regmap[hr]=-1; cur->dirty&=~(1<isconst&=~(1<2) hsn[CCREG]=2; - if(i>1&&hsn[CCREG]>2&&(dops[i-2].itype==RJUMP||dops[i-2].itype==UJUMP||dops[i-2].itype==CJUMP||dops[i-2].itype==SJUMP)) hsn[CCREG]=2; + if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2; for(j=10;j>=3;j--) { for(r=1;r<=MAXREG;r++) @@ -1604,9 +1712,8 @@ static void alloc_reg_temp(struct regstat *cur,int i,signed char reg) static void mov_alloc(struct regstat *current,int i) { if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) { - // logically this is needed but just won't work, no idea why - //alloc_cc(current,i); // for stalls - //dirty_reg(current,CCREG); + alloc_cc(current,i); // for stalls + dirty_reg(current,CCREG); } // Note: Don't need to actually alloc the source registers @@ -1624,7 +1731,7 @@ static void shiftimm_alloc(struct regstat *current,int i) { if(dops[i].rt1) { if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); - else dops[i].lt1=dops[i].rs1; + else dops[i].use_lt1=!!dops[i].rs1; alloc_reg(current,i,dops[i].rt1); dirty_reg(current,dops[i].rt1); if(is_const(current,dops[i].rs1)) { @@ -1730,7 +1837,7 @@ static void alu_alloc(struct regstat *current,int i) static void imm16_alloc(struct regstat *current,int i) { if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); - else dops[i].lt1=dops[i].rs1; + else dops[i].use_lt1=!!dops[i].rs1; if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1); if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU assert(0); @@ -1766,7 +1873,10 @@ static void load_alloc(struct regstat *current,int i) clear_const(current,dops[i].rt1); //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt? if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register - if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); + if (needed_again(dops[i].rs1, i)) + alloc_reg(current, i, dops[i].rs1); + if (ram_offset) + alloc_reg(current, i, ROREG); if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) { alloc_reg(current,i,dops[i].rt1); assert(get_reg(current->regmap,dops[i].rt1)>=0); @@ -1804,7 +1914,7 @@ static void load_alloc(struct regstat *current,int i) } } -void store_alloc(struct regstat *current,int i) +static void store_alloc(struct regstat *current,int i) { clear_const(current,dops[i].rs2); if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary @@ -1813,9 +1923,11 @@ void store_alloc(struct regstat *current,int i) if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD assert(0); } + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - else alloc_reg(current,i,INVCP); + alloc_reg(current, i, INVCP); #endif if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR alloc_reg(current,i,FTEMP); @@ -1825,33 +1937,22 @@ void store_alloc(struct regstat *current,int i) minimum_free_regs[i]=1; } -void c1ls_alloc(struct regstat *current,int i) +static void c1ls_alloc(struct regstat *current,int i) { - //clear_const(current,dops[i].rs1); // FIXME clear_const(current,dops[i].rt1); - if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); alloc_reg(current,i,CSREG); // Status - alloc_reg(current,i,FTEMP); - if(dops[i].opcode==0x35||dops[i].opcode==0x3d) { // 64-bit LDC1/SDC1 - assert(0); - } - #if defined(HOST_IMM8) - // On CPUs without 32-bit immediates we need a pointer to invalid_code - else if((dops[i].opcode&0x3b)==0x39) // SWC1/SDC1 - alloc_reg(current,i,INVCP); - #endif - // We need a temporary register for address generation - alloc_reg_temp(current,i,-1); } -void c2ls_alloc(struct regstat *current,int i) +static void c2ls_alloc(struct regstat *current,int i) { clear_const(current,dops[i].rt1); if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1); alloc_reg(current,i,FTEMP); + if (ram_offset) + alloc_reg(current, i, ROREG); #if defined(HOST_IMM8) // On CPUs without 32-bit immediates we need a pointer to invalid_code - if((dops[i].opcode&0x3b)==0x3a) // SWC2/SDC2 + if (dops[i].opcode == 0x3a) // SWC2 alloc_reg(current,i,INVCP); #endif // We need a temporary register for address generation @@ -1860,7 +1961,7 @@ void c2ls_alloc(struct regstat *current,int i) } #ifndef multdiv_alloc -void multdiv_alloc(struct regstat *current,int i) +static void multdiv_alloc(struct regstat *current,int i) { // case 0x18: MULT // case 0x19: MULTU @@ -1904,7 +2005,7 @@ void multdiv_alloc(struct regstat *current,int i) } #endif -void cop0_alloc(struct regstat *current,int i) +static void cop0_alloc(struct regstat *current,int i) { if(dops[i].opcode2==0) // MFC0 { @@ -1964,14 +2065,14 @@ static void cop2_alloc(struct regstat *current,int i) minimum_free_regs[i]=1; } -void c2op_alloc(struct regstat *current,int i) +static void c2op_alloc(struct regstat *current,int i) { alloc_cc(current,i); // for stalls dirty_reg(current,CCREG); alloc_reg_temp(current,i,-1); } -void syscall_alloc(struct regstat *current,int i) +static void syscall_alloc(struct regstat *current,int i) { alloc_cc(current,i); dirty_reg(current,CCREG); @@ -1980,7 +2081,7 @@ void syscall_alloc(struct regstat *current,int i) current->isconst=0; } -void delayslot_alloc(struct regstat *current,int i) +static void delayslot_alloc(struct regstat *current,int i) { switch(dops[i].itype) { case UJUMP: @@ -2098,12 +2199,12 @@ static void add_stub_r(enum stub_type type, void *addr, void *retaddr, } // Write out a single register -static void wb_register(signed char r,signed char regmap[],uint64_t dirty) +static void wb_register(signed char r, const signed char regmap[], uint64_t dirty) { int hr; for(hr=0;hr>hr)&1) { assert(regmap[hr]<64); emit_storereg(r,hr); @@ -2116,23 +2217,13 @@ static void wb_register(signed char r,signed char regmap[],uint64_t dirty) static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u) { //if(dirty_pre==dirty) return; - int hr,reg; - for(hr=0;hr>(reg&63))&1) { - if(reg>0) { - if(((dirty_pre&~dirty)>>hr)&1) { - if(reg>0&®<34) { - emit_storereg(reg,hr); - } - else if(reg>=64) { - assert(0); - } - } - } - } - } + int hr, r; + for (hr = 0; hr < HOST_REGS; hr++) { + r = pre[hr]; + if (r < 1 || r > 33 || ((u >> r) & 1)) + continue; + if (((dirty_pre & ~dirty) >> hr) & 1) + emit_storereg(r, hr); } } @@ -2153,7 +2244,7 @@ static void pass_args(int a0, int a1) } } -static void alu_assemble(int i,struct regstat *i_regs) +static void alu_assemble(int i, const struct regstat *i_regs) { if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU if(dops[i].rt1) { @@ -2293,7 +2384,7 @@ static void alu_assemble(int i,struct regstat *i_regs) } } -void imm16_assemble(int i,struct regstat *i_regs) +static void imm16_assemble(int i, const struct regstat *i_regs) { if (dops[i].opcode==0x0f) { // LUI if(dops[i].rt1) { @@ -2448,7 +2539,7 @@ void imm16_assemble(int i,struct regstat *i_regs) } } -void shiftimm_assemble(int i,struct regstat *i_regs) +static void shiftimm_assemble(int i, const struct regstat *i_regs) { if(dops[i].opcode2<=0x3) // SLL/SRL/SRA { @@ -2506,7 +2597,7 @@ void shiftimm_assemble(int i,struct regstat *i_regs) } #ifndef shift_assemble -static void shift_assemble(int i,struct regstat *i_regs) +static void shift_assemble(int i, const struct regstat *i_regs) { signed char s,t,shift; if (dops[i].rt1 == 0) @@ -2572,11 +2663,25 @@ static int get_ptr_mem_type(u_int a) return MTYPE_8000; } -static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) +static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free) +{ + int r = get_reg(i_regs->regmap, ROREG); + if (r < 0 && host_tempreg_free) { + host_tempreg_acquire(); + emit_loadreg(ROREG, r = HOST_TEMPREG); + } + if (r < 0) + abort(); + return r; +} + +static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs, + int addr, int *offset_reg, int *addr_reg_override) { void *jaddr = NULL; - int type=0; - int mr=dops[i].rs1; + int type = 0; + int mr = dops[i].rs1; + *offset_reg = -1; if(((smrv_strong|smrv_weak)>>mr)&1) { type=get_ptr_mem_type(smrv[mr]); //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type); @@ -2620,22 +2725,19 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) } } - if(type==0) + if (type == 0) // need ram check { emit_cmpimm(addr,RAM_SIZE); - jaddr=out; + jaddr = out; #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK // Hint to branch predictor that the branch is unlikely to be taken - if(dops[i].rs1>=28) + if (dops[i].rs1 >= 28) emit_jno_unlikely(0); else #endif emit_jno(0); - if(ram_offset!=0) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - addr=*addr_reg_override=HOST_TEMPREG; - } + if (ram_offset != 0) + *offset_reg = get_ro_reg(i_regs, 0); } return jaddr; @@ -2645,9 +2747,10 @@ static void *emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override) static void *get_direct_memhandler(void *table, u_int addr, enum stub_type type, uintptr_t *addr_host) { + uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1); uintptr_t l1, l2 = 0; l1 = ((uintptr_t *)table)[addr>>12]; - if ((l1 & (1ul << (sizeof(l1)*8-1))) == 0) { + if (!(l1 & msb)) { uintptr_t v = l1 << 1; *addr_host = v + addr; return NULL; @@ -2657,10 +2760,10 @@ static void *get_direct_memhandler(void *table, u_int addr, if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB) l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)]; else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB) - l2=((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; + l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2]; else - l2=((uintptr_t *)l1)[(addr&0xfff)/4]; - if ((l2 & (1<<31)) == 0) { + l2 = ((uintptr_t *)l1)[(addr&0xfff)/4]; + if (!(l2 & msb)) { uintptr_t v = l2 << 1; *addr_host = v + (addr&0xfff); return NULL; @@ -2697,13 +2800,56 @@ static int reglist_find_free(u_int reglist) return __builtin_ctz(free_regs); } -static void load_assemble(int i, const struct regstat *i_regs) +static void do_load_word(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_ldr_dualindexed(offset_reg, a, rt); + else + emit_readword_indexed(0, a, rt); +} + +static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writeword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_str_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a) +{ + if (offset_reg < 0) { + emit_writehword_indexed(rt, ofs, a); + return; + } + if (ofs != 0) + emit_addimm(a, ofs, a); + emit_strh_dualindexed(offset_reg, a, rt); + if (ofs != 0 && preseve_a) + emit_addimm(a, -ofs, a); +} + +static void do_store_byte(int a, int rt, int offset_reg) +{ + if (offset_reg >= 0) + emit_strb_dualindexed(offset_reg, a, rt); + else + emit_writebyte_indexed(rt, 0, a); +} + +static void load_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rt1); s=get_reg(i_regs->regmap,dops[i].rs1); @@ -2723,12 +2869,12 @@ static void load_assemble(int i, const struct regstat *i_regs) // could be FIFO, must perform the read // ||dummy read assem_debug("(forced read)\n"); - tl=get_reg(i_regs->regmap,-1); + tl=get_reg_temp(i_regs->regmap); assert(tl>=0); } if(offset||s<0||c) addr=tl; else addr=s; - //if(tl<0) tl=get_reg(i_regs->regmap,-1); + //if(tl<0) tl=get_reg_temp(i_regs->regmap); if(tl>=0) { //printf("load_assemble: c=%d\n",c); //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset); @@ -2740,111 +2886,126 @@ static void load_assemble(int i, const struct regstat *i_regs) if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE) #endif { - jaddr=emit_fastpath_cmp_jump(i,addr,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, addr, + &offset_reg, &fastio_reg_override); } } - else if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(addr,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg - if (dops[i].opcode==0x20) { // LB + switch (dops[i].opcode) { + case 0x20: // LB if(!c||memtarget) { if(!dummy) { - { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movsbl_indexed(x,a,tl); - } + if (offset_reg >= 0) + emit_ldrsb_dualindexed(offset_reg, a, tl); + else + emit_movsbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x21) { // LH + inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x21: // LH if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movswl_indexed(x,a,tl); + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrsh_dualindexed(offset_reg, a, tl); + else + emit_movswl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x23) { // LW + inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x23: // LW if(!c||memtarget) { if(!dummy) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); } if(jaddr) - add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x24) { // LBU + inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x24: // LBU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; + int a = tl; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; - emit_movzbl_indexed(x,a,tl); + if (offset_reg >= 0) + emit_ldrb_dualindexed(offset_reg, a, tl); + else + emit_movzbl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x25) { // LHU + inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x25: // LHU if(!c||memtarget) { if(!dummy) { - int x=0,a=tl; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_movzwl_indexed(x,a,tl); + int a = tl; + if(!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + if (offset_reg >= 0) + emit_ldrh_dualindexed(offset_reg, a, tl); + else + emit_movzwl_indexed(0, a, tl); } if(jaddr) - add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist); + add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); } else - inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist); - } - if (dops[i].opcode==0x27) { // LWU - assert(0); - } - if (dops[i].opcode==0x37) { // LD + inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist); + break; + case 0x27: // LWU + case 0x37: // LD + default: assert(0); } } - if (fastio_reg_override == HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); } #ifndef loadlr_assemble -static void loadlr_assemble(int i, const struct regstat *i_regs) +static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl,temp,temp2,addr; int offset; void *jaddr=0; int memtarget=0,c=0; - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rt1); s=get_reg(i_regs->regmap,dops[i].rs1); - temp=get_reg(i_regs->regmap,-1); + temp=get_reg_temp(i_regs->regmap); temp2=get_reg(i_regs->regmap,FTEMP); addr=get_reg(i_regs->regmap,AGEN1+(i&1)); assert(addr<0); @@ -2865,13 +3026,12 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) }else{ emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR } - jaddr=emit_fastpath_cmp_jump(i,temp2,&fastio_reg_override); + jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2, + &offset_reg, &fastio_reg_override); } else { - if(ram_offset&&memtarget) { - host_tempreg_acquire(); - emit_addimm(temp2,ram_offset,HOST_TEMPREG); - fastio_reg_override=HOST_TEMPREG; + if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); } if (dops[i].opcode==0x22||dops[i].opcode==0x26) { emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR @@ -2881,14 +3041,16 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) } if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR if(!c||memtarget) { - int a=temp2; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_readword_indexed(0,a,temp2); - if(fastio_reg_override==HOST_TEMPREG) host_tempreg_release(); - if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist); + int a = temp2; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, temp2, offset_reg); + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) + host_tempreg_release(); + if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist); } else - inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist); + inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist); if(dops[i].rt1) { assert(tl>=0); emit_andimm(temp,24,temp); @@ -2914,21 +3076,22 @@ static void loadlr_assemble(int i, const struct regstat *i_regs) } #endif -void store_assemble(int i, const struct regstat *i_regs) +static void store_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int addr,temp; int offset; void *jaddr=0; - enum stub_type type; + enum stub_type type=0; int memtarget=0,c=0; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->wasconst>>s)&1; @@ -2941,51 +3104,54 @@ void store_assemble(int i, const struct regstat *i_regs) if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<=0) a=fastio_reg_override; - emit_writebyte_indexed(tl,x,a); - } - type=STOREB_STUB; - } - if (dops[i].opcode==0x29) { // SH + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_byte(a, tl, offset_reg); + } + type = STOREB_STUB; + break; + case 0x29: // SH if(!c||memtarget) { - int x=0,a=temp; - if(!c) a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writehword_indexed(tl,x,a); - } - type=STOREH_STUB; - } - if (dops[i].opcode==0x2B) { // SW + int a = temp; + if (!c) a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_hword(a, 0, tl, offset_reg, 1); + } + type = STOREH_STUB; + break; + case 0x2B: // SW if(!c||memtarget) { - int a=addr; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); - } - type=STOREW_STUB; - } - if (dops[i].opcode==0x3F) { // SD + int a = addr; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + } + type = STOREW_STUB; + break; + case 0x3F: // SD + default: assert(0); - type=STORED_STUB; } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr) { // PCSX store handlers don't check invcode again reglist|=1<waswritten&(1<regmap,dops[i].rs2,ccadj[i],reglist); + inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist); } // basic current block modification detection.. // not looking back as that should be in mips cache already @@ -3035,21 +3201,22 @@ void store_assemble(int i, const struct regstat *i_regs) } } -static void storelr_assemble(int i, const struct regstat *i_regs) +static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int temp; int offset; void *jaddr=0; - void *case1, *case2, *case3; + void *case1, *case23, *case3; void *done0, *done1, *done2; int memtarget=0,c=0; int agr=AGEN1+(i&1); + int offset_reg = -1; u_int reglist=get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); temp=get_reg(i_regs->regmap,agr); - if(temp<0) temp=get_reg(i_regs->regmap,-1); + if(temp<0) temp=get_reg_temp(i_regs->regmap); offset=imm[i]; if(s>=0) { c=(i_regs->isconst>>s)&1; @@ -3072,86 +3239,85 @@ static void storelr_assemble(int i, const struct regstat *i_regs) emit_jmp(0); } } - if(ram_offset) - emit_addimm_no_flags(ram_offset,temp); + if (ram_offset) + offset_reg = get_ro_reg(i_regs, 0); if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR assert(0); } - emit_xorimm(temp,3,temp); emit_testimm(temp,2); - case2=out; + case23=out; emit_jne(0); emit_testimm(temp,1); case1=out; emit_jne(0); // 0 - if (dops[i].opcode==0x2A) { // SWL - emit_writeword_indexed(tl,0,temp); + if (dops[i].opcode == 0x2A) { // SWL + // Write msb into least significant byte + if (dops[i].rs2) emit_rorimm(tl, 24, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (dops[i].opcode==0x2E) { // SWR - emit_writebyte_indexed(tl,3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write entire word + do_store_word(temp, 0, tl, offset_reg, 1); } - else - assert(0); - done0=out; + done0 = out; emit_jmp(0); // 1 set_jump_target(case1, out); - if (dops[i].opcode==0x2A) { // SWL - // Write 3 msb into three least significant bytes - if(dops[i].rs2) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,-1,temp); - if(dops[i].rs2) emit_rorimm(tl,16,tl); - emit_writebyte_indexed(tl,1,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + // Write two msb into two least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_hword(temp, -1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); } - else if (dops[i].opcode==0x2E) { // SWR - // Write two lsb into two most significant bytes - emit_writehword_indexed(tl,1,temp); + else if (dops[i].opcode == 0x2E) { // SWR + // Write 3 lsb into three most significant bytes + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, 1, tl, offset_reg, 0); + if (dops[i].rs2) emit_rorimm(tl, 24, tl); } done1=out; emit_jmp(0); - // 2 - set_jump_target(case2, out); + // 2,3 + set_jump_target(case23, out); emit_testimm(temp,1); - case3=out; + case3 = out; emit_jne(0); + // 2 if (dops[i].opcode==0x2A) { // SWL - // Write two msb into two least significant bytes - if(dops[i].rs2) emit_rorimm(tl,16,tl); - emit_writehword_indexed(tl,-2,temp); - if(dops[i].rs2) emit_rorimm(tl,16,tl); + // Write 3 msb into three least significant bytes + if (dops[i].rs2) emit_rorimm(tl, 8, tl); + do_store_hword(temp, -2, tl, offset_reg, 1); + if (dops[i].rs2) emit_rorimm(tl, 16, tl); + do_store_byte(temp, tl, offset_reg); + if (dops[i].rs2) emit_rorimm(tl, 8, tl); } - else if (dops[i].opcode==0x2E) { // SWR - // Write 3 lsb into three most significant bytes - emit_writebyte_indexed(tl,-1,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); - emit_writehword_indexed(tl,0,temp); - if(dops[i].rs2) emit_rorimm(tl,24,tl); + else if (dops[i].opcode == 0x2E) { // SWR + // Write two lsb into two most significant bytes + do_store_hword(temp, 0, tl, offset_reg, 1); } - done2=out; + done2 = out; emit_jmp(0); // 3 set_jump_target(case3, out); - if (dops[i].opcode==0x2A) { // SWL - // Write msb into least significant byte - if(dops[i].rs2) emit_rorimm(tl,24,tl); - emit_writebyte_indexed(tl,-3,temp); - if(dops[i].rs2) emit_rorimm(tl,8,tl); + if (dops[i].opcode == 0x2A) { // SWL + do_store_word(temp, -3, tl, offset_reg, 0); } - else if (dops[i].opcode==0x2E) { // SWR - // Write entire word - emit_writeword_indexed(tl,-3,temp); + else if (dops[i].opcode == 0x2E) { // SWR + do_store_byte(temp, tl, offset_reg); } set_jump_target(done0, out); set_jump_target(done1, out); set_jump_target(done2, out); + if (offset_reg == HOST_TEMPREG) + host_tempreg_release(); if(!c||!memtarget) - add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist); + add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist); if(!(i_regs->waswritten&(1<regmap,INVCP); assert(ir>=0); @@ -3169,7 +3335,7 @@ static void storelr_assemble(int i, const struct regstat *i_regs) } } -static void cop0_assemble(int i,struct regstat *i_regs) +static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) { if(dops[i].opcode2==0) // MFC0 { @@ -3190,7 +3356,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) emit_readword(&last_count,HOST_TEMPREG); emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_writeword(HOST_CCREG,&Count); } // What a mess. The status register (12) can enable interrupts, @@ -3225,7 +3391,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) if(copr==9||copr==11||copr==12||copr==13) { emit_readword(&Count,HOST_CCREG); emit_readword(&next_interupt,HOST_TEMPREG); - emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG); + emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG); emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG); emit_writeword(HOST_TEMPREG,&last_count); emit_storereg(CCREG,HOST_CCREG); @@ -3258,7 +3424,7 @@ static void cop0_assemble(int i,struct regstat *i_regs) } } -static void cop1_unusable(int i,struct regstat *i_regs) +static void cop1_unusable(int i, const struct regstat *i_regs) { // XXX: should just just do the exception instead //if(!cop1_usable) @@ -3269,12 +3435,12 @@ static void cop1_unusable(int i,struct regstat *i_regs) } } -static void cop1_assemble(int i,struct regstat *i_regs) +static void cop1_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } -static void c1ls_assemble(int i,struct regstat *i_regs) +static void c1ls_assemble(int i, const struct regstat *i_regs) { cop1_unusable(i, i_regs); } @@ -3297,7 +3463,7 @@ static void do_cop1stub(int n) wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty); if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); emit_movimm(start+(i-ds)*4,EAX); // Get PC - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... + emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle... emit_far_jump(ds?fp_exception_ds:fp_exception); } @@ -3333,7 +3499,7 @@ static void emit_log_gte_stall(int i, int stall, u_int reglist) emit_movimm(stall, 0); else emit_mov(HOST_TEMPREG, 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(log_gte_stall); restore_regs(reglist); } @@ -3356,10 +3522,12 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u //if (dops[j].is_ds) break; if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt) break; + if (j > 0 && ccadj[j - 1] > ccadj[j]) + break; } j = max(j, 0); } - cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]); + cycles_passed = ccadj[i] - ccadj[j]; if (other_gte_op_cycles >= 0) stall = other_gte_op_cycles - cycles_passed; else if (cycles_passed >= 44) @@ -3370,13 +3538,13 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 // too slow save_regs(reglist); emit_movimm(gte_cycletab[op], 0); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1); + emit_addimm(HOST_CCREG, ccadj[i], 1); emit_far_call(call_gteStall); restore_regs(reglist); #else host_tempreg_acquire(); emit_readword(&psxRegs.gteBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 44); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3396,7 +3564,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u for (j = i + 1; j < slen; j++) { if (cop2_is_stalling_op(j, &other_gte_op_cycles)) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles)) j++; @@ -3406,7 +3574,7 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u if (other_gte_op_cycles >= 0) // will handle stall when assembling that op return; - cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]); + cycles_passed = ccadj[min(j, slen -1)] - ccadj[i]; if (cycles_passed >= 44) return; assem_debug("; save gteBusyCycle\n"); @@ -3414,11 +3582,11 @@ static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u #if 0 emit_readword(&last_count, HOST_TEMPREG); emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG); - emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG); + emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG); emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #else - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle); #endif host_tempreg_release(); @@ -3440,7 +3608,7 @@ static int check_multdiv(int i, int *cycles) return 1; } -static void multdiv_prepare_stall(int i, const struct regstat *i_regs) +static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_) { int j, found = 0, c = 0; if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3454,7 +3622,7 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) break; if ((found = is_mflohi(j))) break; - if (is_jump(j)) { + if (dops[j].is_jump) { // check ds if (j + 1 < slen && (found = is_mflohi(j + 1))) j++; @@ -3468,7 +3636,7 @@ static void multdiv_prepare_stall(int i, const struct regstat *i_regs) assert(c > 0); assem_debug("; muldiv prepare stall %d\n", c); host_tempreg_acquire(); - emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + c, HOST_TEMPREG); + emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG); emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle); host_tempreg_release(); } @@ -3477,7 +3645,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) { int j, known_cycles = 0; u_int reglist = get_host_reglist(i_regs->regmap); - int rtmp = get_reg(i_regs->regmap, -1); + int rtmp = get_reg_temp(i_regs->regmap); if (rtmp < 0) rtmp = reglist_find_free(reglist); if (HACK_ENABLED(NDHACK_NO_STALLS)) @@ -3490,16 +3658,18 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) if (!dops[i].bt) { for (j = i - 1; j >= 0; j--) { if (dops[j].is_ds) break; - if (check_multdiv(j, &known_cycles) || dops[j].bt) + if (check_multdiv(j, &known_cycles)) break; if (is_mflohi(j)) // already handled by this op return; + if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j])) + break; } j = max(j, 0); } if (known_cycles > 0) { - known_cycles -= CLOCK_ADJUST(ccadj[i] - ccadj[j]); + known_cycles -= ccadj[i] - ccadj[j]; assem_debug("; muldiv stall resolved %d\n", known_cycles); if (known_cycles > 0) emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG); @@ -3508,7 +3678,7 @@ static void multdiv_do_stall(int i, const struct regstat *i_regs) assem_debug("; muldiv stall unresolved\n"); host_tempreg_acquire(); emit_readword(&psxRegs.muldivBusyCycle, rtmp); - emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp); + emit_addimm(rtmp, -ccadj[i], rtmp); emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG); emit_cmpimm(HOST_TEMPREG, 37); emit_cmovb_reg(rtmp, HOST_CCREG); @@ -3599,7 +3769,7 @@ static void cop2_put_dreg(u_int copr,signed char sl,signed char temp) } } -static void c2ls_assemble(int i, const struct regstat *i_regs) +static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) { int s,tl; int ar; @@ -3608,7 +3778,8 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) void *jaddr2=NULL; enum stub_type type; int agr=AGEN1+(i&1); - int fastio_reg_override=-1; + int offset_reg = -1; + int fastio_reg_override = -1; u_int reglist=get_host_reglist(i_regs->regmap); u_int copr=(source[i]>>16)&0x1f; s=get_reg(i_regs->regmap,dops[i].rs1); @@ -3623,7 +3794,7 @@ static void c2ls_assemble(int i, const struct regstat *i_regs) // get the address if (dops[i].opcode==0x3a) { // SWC2 ar=get_reg(i_regs->regmap,agr); - if(ar<0) ar=get_reg(i_regs->regmap,-1); + if(ar<0) ar=get_reg_temp(i_regs->regmap); reglist|=1<=0) a=fastio_reg_override; - emit_readword_indexed(0,a,tl); + jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar, + &offset_reg, &fastio_reg_override); + } + else if (ram_offset && memtarget) { + offset_reg = get_ro_reg(i_regs, 0); + } + switch (dops[i].opcode) { + case 0x32: { // LWC2 + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_load_word(a, tl, offset_reg); + break; } - if (dops[i].opcode==0x3a) { // SWC2 + case 0x3a: { // SWC2 #ifdef DESTRUCTIVE_SHIFT if(!offset&&!c&&s>=0) emit_mov(s,ar); #endif - int a=ar; - if(fastio_reg_override>=0) a=fastio_reg_override; - emit_writeword_indexed(tl,0,a); + int a = ar; + if (fastio_reg_override >= 0) + a = fastio_reg_override; + do_store_word(a, 0, tl, offset_reg, 1); + break; + } + default: + assert(0); } } - if(fastio_reg_override==HOST_TEMPREG) + if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG) host_tempreg_release(); if(jaddr2) - add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist); + add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); if(dops[i].opcode==0x3a) // SWC2 if(!(i_regs->waswritten&(1<>11) & 0x1f; - signed char temp = get_reg(i_regs->regmap, -1); + signed char temp = get_reg_temp(i_regs->regmap); if (!HACK_ENABLED(NDHACK_NO_STALLS)) { u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1); @@ -3776,9 +3954,9 @@ static void do_unalignedwritestub(int n) int cc=get_reg(i_regmap,CCREG); if(cc<0) emit_loadreg(CCREG,2); - emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2); + emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2); emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr)); - emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc); + emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc); if(cc<0) emit_storereg(CCREG,2); restore_regs(reglist); @@ -3793,7 +3971,7 @@ void multdiv_assemble(int i,struct regstat *i_regs) } #endif -static void mov_assemble(int i,struct regstat *i_regs) +static void mov_assemble(int i, const struct regstat *i_regs) { //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO @@ -3812,7 +3990,7 @@ static void mov_assemble(int i,struct regstat *i_regs) } // call interpreter, exception handler, things that change pc/regs/cycles ... -static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func) +static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func) { signed char ccreg=get_reg(i_regs->regmap,CCREG); assert(ccreg==HOST_CCREG); @@ -3822,33 +4000,39 @@ static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, vo emit_movimm(pc,3); // Get PC emit_readword(&last_count,2); emit_writeword(3,&psxRegs.pc); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX + emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG); emit_add(2,HOST_CCREG,2); emit_writeword(2,&psxRegs.cycle); emit_far_call(func); emit_far_jump(jump_to_new_pc); } -static void syscall_assemble(int i,struct regstat *i_regs) +static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_) { - emit_movimm(0x20,0); // cause code - emit_movimm(0,1); // not in delay slot - call_c_cpu_handler(i,i_regs,start+i*4,psxException); + // 'break' tends to be littered around to catch things like + // division by 0 and is almost never executed, so don't emit much code here + void *func = (dops[i].opcode2 == 0x0C) + ? (is_delayslot ? jump_syscall_ds : jump_syscall) + : (is_delayslot ? jump_break_ds : jump_break); + assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG); + emit_movimm(start + i*4, 2); // pc + emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG); + emit_far_jump(func); } -static void hlecall_assemble(int i,struct regstat *i_regs) +static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_) { void *hlefunc = psxNULL; uint32_t hleCode = source[i] & 0x03ffffff; if (hleCode < ARRAY_SIZE(psxHLEt)) hlefunc = psxHLEt[hleCode]; - call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc); } -static void intcall_assemble(int i,struct regstat *i_regs) +static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_) { - call_c_cpu_handler(i,i_regs,start+i*4,execI); + call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI); } static void speculate_mov(int rs,int rt) @@ -3943,45 +4127,109 @@ static void speculate_register_values(int i) #endif } -static void ds_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i, const struct regstat *i_regs); +static void rjump_assemble(int i, const struct regstat *i_regs); +static void cjump_assemble(int i, const struct regstat *i_regs); +static void sjump_assemble(int i, const struct regstat *i_regs); +static void pagespan_assemble(int i, const struct regstat *i_regs); + +static int assemble(int i, const struct regstat *i_regs, int ccadj_) { - speculate_register_values(i); - is_delayslot=1; - switch(dops[i].itype) { + int ds = 0; + switch (dops[i].itype) { case ALU: - alu_assemble(i,i_regs);break; + alu_assemble(i, i_regs); + break; case IMM16: - imm16_assemble(i,i_regs);break; + imm16_assemble(i, i_regs); + break; case SHIFT: - shift_assemble(i,i_regs);break; + shift_assemble(i, i_regs); + break; case SHIFTIMM: - shiftimm_assemble(i,i_regs);break; + shiftimm_assemble(i, i_regs); + break; case LOAD: - load_assemble(i,i_regs);break; + load_assemble(i, i_regs, ccadj_); + break; case LOADLR: - loadlr_assemble(i,i_regs);break; + loadlr_assemble(i, i_regs, ccadj_); + break; case STORE: - store_assemble(i,i_regs);break; + store_assemble(i, i_regs, ccadj_); + break; case STORELR: - storelr_assemble(i,i_regs);break; + storelr_assemble(i, i_regs, ccadj_); + break; case COP0: - cop0_assemble(i,i_regs);break; + cop0_assemble(i, i_regs, ccadj_); + break; case COP1: - cop1_assemble(i,i_regs);break; + cop1_assemble(i, i_regs); + break; case C1LS: - c1ls_assemble(i,i_regs);break; + c1ls_assemble(i, i_regs); + break; case COP2: - cop2_assemble(i,i_regs);break; + cop2_assemble(i, i_regs); + break; case C2LS: - c2ls_assemble(i,i_regs);break; + c2ls_assemble(i, i_regs, ccadj_); + break; case C2OP: - c2op_assemble(i,i_regs);break; + c2op_assemble(i, i_regs); + break; case MULTDIV: - multdiv_assemble(i,i_regs); - multdiv_prepare_stall(i,i_regs); + multdiv_assemble(i, i_regs); + multdiv_prepare_stall(i, i_regs, ccadj_); break; case MOV: - mov_assemble(i,i_regs);break; + mov_assemble(i, i_regs); + break; + case SYSCALL: + syscall_assemble(i, i_regs, ccadj_); + break; + case HLECALL: + hlecall_assemble(i, i_regs, ccadj_); + break; + case INTCALL: + intcall_assemble(i, i_regs, ccadj_); + break; + case UJUMP: + ujump_assemble(i, i_regs); + ds = 1; + break; + case RJUMP: + rjump_assemble(i, i_regs); + ds = 1; + break; + case CJUMP: + cjump_assemble(i, i_regs); + ds = 1; + break; + case SJUMP: + sjump_assemble(i, i_regs); + ds = 1; + break; + case SPAN: + pagespan_assemble(i, i_regs); + break; + case NOP: + case OTHER: + case NI: + // not handled, just skip + break; + default: + assert(0); + } + return ds; +} + +static void ds_assemble(int i, const struct regstat *i_regs) +{ + speculate_register_values(i); + is_delayslot = 1; + switch (dops[i].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -3991,8 +4239,11 @@ static void ds_assemble(int i,struct regstat *i_regs) case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(i, i_regs, ccadj[i]); } - is_delayslot=0; + is_delayslot = 0; } // Is the branch target a valid internal jump? @@ -4028,7 +4279,7 @@ static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,u for(hr=0;hr=0&&(pre[hr]&63)=0&&pre[hr]=0) { emit_mov(hr,nr); @@ -4042,26 +4293,18 @@ static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,u // Load the specified registers // This only loads the registers given as arguments because // we don't want to load things that will be overwritten -static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) +static inline void load_reg(signed char entry[], signed char regmap[], int rs) { - int hr; - // Load 32-bit regs - for(hr=0;hr=0) { - if(entry[hr]!=regmap[hr]) { - if(regmap[hr]==rs1||regmap[hr]==rs2) - { - if(regmap[hr]==0) { - emit_zeroreg(hr); - } - else - { - emit_loadreg(regmap[hr],hr); - } - } - } - } - } + int hr = get_reg(regmap, rs); + if (hr >= 0 && entry[hr] != regmap[hr]) + emit_loadreg(regmap[hr], hr); +} + +static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2) +{ + load_reg(entry, regmap, rs1); + if (rs1 != rs2) + load_reg(entry, regmap, rs2); } // Load registers prior to the start of a loop @@ -4069,41 +4312,26 @@ static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2) static void loop_preload(signed char pre[],signed char entry[]) { int hr; - for(hr=0;hr=0) { - if(get_reg(pre,entry[hr])<0) { - assem_debug("loop preload:\n"); - //printf("loop preload: %d\n",hr); - if(entry[hr]==0) { - emit_zeroreg(hr); - } - else if(entry[hr]= 0 && pre[hr] != r && get_reg(pre, r) < 0) { + assem_debug("loop preload:\n"); + if (r < TEMPREG) + emit_loadreg(r, hr); } } } // Generate address for load/store instruction // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads -void address_generation(int i,struct regstat *i_regs,signed char entry[]) +static void address_generation(int i, const struct regstat *i_regs, signed char entry[]) { - if(dops[i].itype==LOAD||dops[i].itype==LOADLR||dops[i].itype==STORE||dops[i].itype==STORELR||dops[i].itype==C1LS||dops[i].itype==C2LS) { + if (dops[i].is_load || dops[i].is_store) { int ra=-1; int agr=AGEN1+(i&1); if(dops[i].itype==LOAD) { ra=get_reg(i_regs->regmap,dops[i].rt1); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); assert(ra>=0); } if(dops[i].itype==LOADLR) { @@ -4111,14 +4339,14 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } if(dops[i].itype==STORE||dops[i].itype==STORELR) { ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } - if(dops[i].itype==C1LS||dops[i].itype==C2LS) { + if(dops[i].itype==C2LS) { if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2 ra=get_reg(i_regs->regmap,FTEMP); else { // SWC1/SDC1/SWC2/SDC2 ra=get_reg(i_regs->regmap,agr); - if(ra<0) ra=get_reg(i_regs->regmap,-1); + if(ra<0) ra=get_reg_temp(i_regs->regmap); } } int rs=get_reg(i_regs->regmap,dops[i].rs1); @@ -4167,7 +4395,7 @@ void address_generation(int i,struct regstat *i_regs,signed char entry[]) } } // Preload constants for next instruction - if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS||dops[i+1].itype==C2LS) { + if (dops[i+1].is_load || dops[i+1].is_store) { int agr,ra; // Actual address agr=AGEN1+((i+1)&1); @@ -4210,12 +4438,12 @@ static int get_final_value(int hr, int i, int *value) i++; } if(i>hr)&1)) { @@ -4295,7 +4523,7 @@ static void load_consts(signed char pre[],signed char regmap[],int i) } } -void load_all_consts(signed char regmap[], u_int dirty, int i) +static void load_all_consts(const signed char regmap[], u_int dirty, int i) { int hr; // Load 32-bit regs @@ -4316,7 +4544,7 @@ void load_all_consts(signed char regmap[], u_int dirty, int i) } // Write out all dirty registers (except cycle count) -static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty) +static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty) { int hr; for(hr=0;hr>2; @@ -4356,7 +4584,7 @@ void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr) } // Load all registers (except cycle count) -void load_all_regs(signed char i_regmap[]) +static void load_all_regs(const signed char i_regmap[]) { int hr; for(hr=0;hr0 && (i_regmap[hr]&63)0 && i_regmap[hr]0 && (i_regmap[hr]&63)0 && i_regmap[hr]0&&(dops[t-1].itype==RJUMP||dops[t-1].itype==UJUMP||dops[t-1].itype==CJUMP||dops[t-1].itype==SJUMP)) return 0; + //if(t>0&&(dops[t-1].is_jump) return 0; // Delay slots require additional processing, so do not match if(dops[t].is_ds) return 0; } @@ -4553,7 +4781,7 @@ static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr) } #ifdef DRC_DBG -static void drc_dbg_emit_do_cmp(int i) +static void drc_dbg_emit_do_cmp(int i, int ccadj_) { extern void do_insn_cmp(); //extern int cycle; @@ -4564,7 +4792,7 @@ static void drc_dbg_emit_do_cmp(int i) // write out changed consts to match the interpreter if (i > 0 && !dops[i].bt) { for (hr = 0; hr < HOST_REGS; hr++) { - int reg = regs[i-1].regmap[hr]; + int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr]; if (hr == EXCLUDE_REG || reg < 0) continue; if (!((regs[i-1].isconst >> hr) & 1)) @@ -4577,6 +4805,11 @@ static void drc_dbg_emit_do_cmp(int i) } emit_movimm(start+i*4,0); emit_writeword(0,&pcaddr); + int cc = get_reg(regs[i].regmap_entry, CCREG); + if (cc < 0) + emit_loadreg(CCREG, cc = 0); + emit_addimm(cc, ccadj_, 0); + emit_writeword(0, &psxRegs.cycle); emit_far_call(do_insn_cmp); //emit_readword(&cycle,0); //emit_addimm(0,2,0); @@ -4586,60 +4819,29 @@ static void drc_dbg_emit_do_cmp(int i) assem_debug("\\\\do_insn_cmp\n"); } #else -#define drc_dbg_emit_do_cmp(x) +#define drc_dbg_emit_do_cmp(x,y) #endif // Used when a branch jumps into the delay slot of another branch static void ds_assemble_entry(int i) { - int t=(ba[i]-start)>>2; + int t = (ba[i] - start) >> 2; + int ccadj_ = -CLOCK_ADJUST(1); if (!instr_addr[t]) instr_addr[t] = out; assem_debug("Assemble delay slot at %x\n",ba[i]); assem_debug("<->\n"); - drc_dbg_emit_do_cmp(t); + drc_dbg_emit_do_cmp(t, ccadj_); if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG) wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty); load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2); address_generation(t,®s[t],regs[t].regmap_entry); - if(dops[t].itype==STORE||dops[t].itype==STORELR||(dops[t].opcode&0x3b)==0x39||(dops[t].opcode&0x3b)==0x3a) - load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP); + if (ram_offset && (dops[t].is_load || dops[t].is_store)) + load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG); + if (dops[t].is_store) + load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP); is_delayslot=0; - switch(dops[t].itype) { - case ALU: - alu_assemble(t,®s[t]);break; - case IMM16: - imm16_assemble(t,®s[t]);break; - case SHIFT: - shift_assemble(t,®s[t]);break; - case SHIFTIMM: - shiftimm_assemble(t,®s[t]);break; - case LOAD: - load_assemble(t,®s[t]);break; - case LOADLR: - loadlr_assemble(t,®s[t]);break; - case STORE: - store_assemble(t,®s[t]);break; - case STORELR: - storelr_assemble(t,®s[t]);break; - case COP0: - cop0_assemble(t,®s[t]);break; - case COP1: - cop1_assemble(t,®s[t]);break; - case C1LS: - c1ls_assemble(t,®s[t]);break; - case COP2: - cop2_assemble(t,®s[t]);break; - case C2LS: - c2ls_assemble(t,®s[t]);break; - case C2OP: - c2op_assemble(t,®s[t]);break; - case MULTDIV: - multdiv_assemble(t,®s[t]); - multdiv_prepare_stall(i,®s[t]); - break; - case MOV: - mov_assemble(t,®s[t]);break; + switch (dops[t].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -4649,6 +4851,9 @@ static void ds_assemble_entry(int i) case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(t, ®s[t], ccadj_); } store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4); @@ -4678,9 +4883,10 @@ static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2) emit_movimm_from(imm1,rt1,imm2,rt2); } -void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) +static void do_cc(int i, const signed char i_regmap[], int *adj, + int addr, int taken, int invert) { - int count; + int count, count_plus2; void *jaddr; void *idle=NULL; int t=0; @@ -4692,14 +4898,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) if(internal_branch(ba[i])) { t=(ba[i]-start)>>2; - if(dops[t].is_ds) *adj=-1; // Branch into delay slot adds an extra cycle + if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle else *adj=ccadj[t]; } else { *adj=0; } - count=ccadj[i]; + count = ccadj[i]; + count_plus2 = count + CLOCK_ADJUST(2); if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) { // Idle loop if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG); @@ -4710,26 +4917,26 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) emit_jmp(0); } else if(*adj==0||invert) { - int cycles=CLOCK_ADJUST(count+2); + int cycles = count_plus2; // faster loop HACK #if 0 if (t&&*adj) { int rel=t-i; if(-NO_CYCLE_PENALTY_THR>2].regmap_entry); @@ -4984,7 +5191,7 @@ static void ujump_assemble_write_ra(int i) } } -static void ujump_assemble(int i,struct regstat *i_regs) +static void ujump_assemble(int i, const struct regstat *i_regs) { int ra_done=0; if(i==(ba[i]-start)>>2) assem_debug("idle loop\n"); @@ -5007,7 +5214,7 @@ static void ujump_assemble(int i,struct regstat *i_regs) uint64_t bc_unneeded=branch_regs[i].u; bc_unneeded|=1|(1LL<=0) emit_prefetchreg(temp); #endif do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal_branch(ba[i])) assem_debug("branch: internal\n"); @@ -5054,7 +5261,7 @@ static void rjump_assemble_write_ra(int i) #endif } -static void rjump_assemble(int i,struct regstat *i_regs) +static void rjump_assemble(int i, const struct regstat *i_regs) { int temp; int rs,cc; @@ -5129,7 +5336,7 @@ static void rjump_assemble(int i,struct regstat *i_regs) //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN); //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen //assert(adj==0); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs); if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10) // special case for RFE @@ -5151,9 +5358,9 @@ static void rjump_assemble(int i,struct regstat *i_regs) #endif } -static void cjump_assemble(int i,struct regstat *i_regs) +static void cjump_assemble(int i, const struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); @@ -5209,7 +5416,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) bc_unneeded|=1; wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); + load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); cc=get_reg(branch_regs[i].regmap,CCREG); assert(cc==HOST_CCREG); if(unconditional) @@ -5219,7 +5426,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(unconditional) { do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5238,7 +5445,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) } } else if(nop) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5246,7 +5453,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) else { void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); assert(s1l>=0); @@ -5301,7 +5508,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5311,7 +5518,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) @@ -5331,16 +5538,13 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) else { // In-order execution (branch first) - //if(dops[i].likely) printf("IOL\n"); - //else - //printf("IOE\n"); void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL; if(!unconditional&&!nop) { //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); @@ -5384,6 +5588,8 @@ static void cjump_assemble(int i,struct regstat *i_regs) // load regs load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); @@ -5395,7 +5601,7 @@ static void cjump_assemble(int i,struct regstat *i_regs) store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); assem_debug("cycle count (adj)\n"); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5414,18 +5620,19 @@ static void cjump_assemble(int i,struct regstat *i_regs) if(nottaken1) set_jump_target(nottaken1, out); set_jump_target(nottaken, out); assem_debug("2:\n"); - if(!dops[i].likely) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + // load regs + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!dops[i].likely) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5434,22 +5641,22 @@ static void cjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,dops[i].likely?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void sjump_assemble(int i,struct regstat *i_regs) +static void sjump_assemble(int i, const struct regstat *i_regs) { - signed char *i_regmap=i_regs->regmap; + const signed char *i_regmap = i_regs->regmap; int cc; int match; match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); - assem_debug("smatch=%d\n",match); + assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo); int s1l; int unconditional=0,nevertaken=0; int invert=0; @@ -5494,7 +5701,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) bc_unneeded|=1; wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded); load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); + load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG); if(dops[i].rt1==31) { int rt,return_address; rt=get_reg(branch_regs[i].regmap,31); @@ -5517,7 +5724,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(unconditional) { do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0); if(i!=(ba[i]-start)>>2 || source[i+1]!=0) { - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5536,7 +5743,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } } else if(nevertaken) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5544,7 +5751,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) else { void *nottaken = NULL; do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert); - if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); { assert(s1l>=0); if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL @@ -5575,7 +5782,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) { if(adj) { - emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + emit_addimm(cc,-adj,cc); add_to_linker(out,ba[i],internal); }else{ emit_addnop(13); @@ -5585,7 +5792,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) }else #endif { - if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc); + if(adj) emit_addimm(cc,-adj,cc); store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) @@ -5604,7 +5811,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) } if(adj) { - if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc); + if(!invert) emit_addimm(cc,adj,cc); } } // (!unconditional) } // if(ooo) @@ -5652,6 +5859,8 @@ static void sjump_assemble(int i,struct regstat *i_regs) // load regs load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); @@ -5663,7 +5872,7 @@ static void sjump_assemble(int i,struct regstat *i_regs) store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); do_cc(i,i_regmap,&adj,ba[i],TAKEN,0); assem_debug("cycle count (adj)\n"); - if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc); + if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc); load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]); if(internal) assem_debug("branch: internal\n"); @@ -5681,18 +5890,18 @@ static void sjump_assemble(int i,struct regstat *i_regs) if(!unconditional) { set_jump_target(nottaken, out); assem_debug("1:\n"); - if(!dops[i].likely) { - wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); - load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); - address_generation(i+1,&branch_regs[i],0); - load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG); - ds_assemble(i+1,&branch_regs[i]); - } + wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded); + load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2); + address_generation(i+1,&branch_regs[i],0); + if (ram_offset) + load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG); + load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP); + ds_assemble(i+1,&branch_regs[i]); cc=get_reg(branch_regs[i].regmap,CCREG); - if(cc==-1&&!dops[i].likely) { + if (cc == -1) { // Cycle count isn't in a register, temporarily load it then write it out emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG); void *jaddr=out; emit_jns(0); add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); @@ -5701,16 +5910,16 @@ static void sjump_assemble(int i,struct regstat *i_regs) else{ cc=get_reg(i_regmap,CCREG); assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); + emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc); void *jaddr=out; emit_jns(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,dops[i].likely?NULLDS:NOTTAKEN,0); + add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); } } } } -static void pagespan_assemble(int i,struct regstat *i_regs) +static void pagespan_assemble(int i, const struct regstat *i_regs) { int s1l=get_reg(i_regs->regmap,dops[i].rs1); int s2l=get_reg(i_regs->regmap,dops[i].rs2); @@ -5733,8 +5942,8 @@ static void pagespan_assemble(int i,struct regstat *i_regs) while(hrregmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { addr=hr++;break; } @@ -5744,8 +5953,8 @@ static void pagespan_assemble(int i,struct regstat *i_regs) while(hrregmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { alt=hr++;break; } @@ -5756,8 +5965,8 @@ static void pagespan_assemble(int i,struct regstat *i_regs) while(hrregmap[hr]&63)!=dops[i].rs1 && - (i_regs->regmap[hr]&63)!=dops[i].rs2 ) + i_regs->regmap[hr]!=dops[i].rs1 && + i_regs->regmap[hr]!=dops[i].rs2 ) { ntaddr=hr;break; } @@ -5766,9 +5975,9 @@ static void pagespan_assemble(int i,struct regstat *i_regs) } assert(hrregmap[HOST_CCREG]==CCREG); wb_dirtys(regs[i].regmap,regs[i].dirty); - if(dops[i].likely||unconditional) + if(unconditional) { emit_movimm(ba[i],HOST_BTREG); } @@ -5913,22 +6122,6 @@ static void pagespan_assemble(int i,struct regstat *i_regs) add_jump_out(target_addr,stub); } else set_jump_target(branch_addr, stub); - if(dops[i].likely) { - // Not-taken path - set_jump_target(nottaken, out); - wb_dirtys(regs[i].regmap,regs[i].dirty); - void *branch_addr=out; - emit_jmp(0); - int target_addr=start+i*4+8; - void *stub=out; - void *compiled_target_addr=check_addr(target_addr); - emit_extjump_ds(branch_addr, target_addr); - if(compiled_target_addr) { - set_jump_target(branch_addr, compiled_target_addr); - add_jump_out(target_addr,stub); - } - else set_jump_target(branch_addr, stub); - } } // Assemble the delay slot for the above @@ -5948,44 +6141,12 @@ static void pagespan_ds() emit_writeword(HOST_BTREG,&branch_target); load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2); address_generation(0,®s[0],regs[0].regmap_entry); - if(dops[0].itype==STORE||dops[0].itype==STORELR||(dops[0].opcode&0x3b)==0x39||(dops[0].opcode&0x3b)==0x3a) - load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP); + if (ram_offset && (dops[0].is_load || dops[0].is_store)) + load_reg(regs[0].regmap_entry,regs[0].regmap,ROREG); + if (dops[0].is_store) + load_reg(regs[0].regmap_entry,regs[0].regmap,INVCP); is_delayslot=0; - switch(dops[0].itype) { - case ALU: - alu_assemble(0,®s[0]);break; - case IMM16: - imm16_assemble(0,®s[0]);break; - case SHIFT: - shift_assemble(0,®s[0]);break; - case SHIFTIMM: - shiftimm_assemble(0,®s[0]);break; - case LOAD: - load_assemble(0,®s[0]);break; - case LOADLR: - loadlr_assemble(0,®s[0]);break; - case STORE: - store_assemble(0,®s[0]);break; - case STORELR: - storelr_assemble(0,®s[0]);break; - case COP0: - cop0_assemble(0,®s[0]);break; - case COP1: - cop1_assemble(0,®s[0]);break; - case C1LS: - c1ls_assemble(0,®s[0]);break; - case COP2: - cop2_assemble(0,®s[0]);break; - case C2LS: - c2ls_assemble(0,®s[0]);break; - case C2OP: - c2op_assemble(0,®s[0]);break; - case MULTDIV: - multdiv_assemble(0,®s[0]); - multdiv_prepare_stall(0,®s[0]); - break; - case MOV: - mov_assemble(0,®s[0]);break; + switch (dops[0].itype) { case SYSCALL: case HLECALL: case INTCALL: @@ -5995,10 +6156,13 @@ static void pagespan_ds() case CJUMP: case SJUMP: SysPrintf("Jump in the delay slot. This is probably a bug.\n"); + break; + default: + assemble(0, ®s[0], 0); } int btaddr=get_reg(regs[0].regmap,BTREG); if(btaddr<0) { - btaddr=get_reg(regs[0].regmap,-1); + btaddr=get_reg_temp(regs[0].regmap); emit_readword(&branch_target,btaddr); } assert(btaddr!=HOST_CCREG); @@ -6020,614 +6184,43 @@ static void pagespan_ds() load_regs_bt(regs[0].regmap,regs[0].dirty,start+4); } -// Basic liveness analysis for MIPS registers -void unneeded_registers(int istart,int iend,int r) +static void check_regmap(signed char *regmap) { - int i; - uint64_t u,gte_u,b,gte_b; - uint64_t temp_u,temp_gte_u=0; - uint64_t gte_u_unknown=0; - if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) - gte_u_unknown=~0ll; - if(iend==slen-1) { - u=1; - gte_u=gte_u_unknown; - }else{ - //u=unneeded_reg[iend+1]; - u=1; - gte_u=gte_unneeded[iend+1]; +#ifndef NDEBUG + int i,j; + for (i = 0; i < HOST_REGS; i++) { + if (regmap[i] < 0) + continue; + for (j = i + 1; j < HOST_REGS; j++) + assert(regmap[i] != regmap[j]); } +#endif +} - for (i=iend;i>=istart;i--) - { - //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) - { - // If subroutine call, flag return address as a possible branch target - if(dops[i].rt1==31 && i +static char insn[MAXBLOCK][10]; - if(ba[i]=(start+slen*4)) - { - // Branch out of this block, flush all regs - u=1; - gte_u=gte_u_unknown; - branch_unneeded_reg[i]=u; - // Merge in delay slot - u|=(1LL<>2].bt=1; - if(ba[i]<=start+i*4) { - // Backward branch - if(is_ujump(i)) - { - // Unconditional branch - temp_u=1; - temp_gte_u=0; - } else { - // Conditional branch (not taken case) - temp_u=unneeded_reg[i+2]; - temp_gte_u&=gte_unneeded[i+2]; - } - // Merge in delay slot - temp_u|=(1LL<>2,i-1,r+1); - }else{ - unneeded_reg[(ba[i]-start)>>2]=1; - gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; - } - } /*else*/ if(1) { - if (is_ujump(i)) - { - // Unconditional branch - u=unneeded_reg[(ba[i]-start)>>2]; - gte_u=gte_unneeded[(ba[i]-start)>>2]; - branch_unneeded_reg[i]=u; - // Merge in delay slot - u|=(1LL<>2]; - gte_b=gte_unneeded[(ba[i]-start)>>2]; - branch_unneeded_reg[i]=b; - // Branch delay slot - b|=(1LL<>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n"); - */ - } -} +#define set_mnemonic(i_, n_) \ + strcpy(insn[i_], n_) -// Write back dirty registers as soon as we will no longer modify them, -// so that we don't end up with lots of writes at the branches. -void clean_registers(int istart,int iend,int wr) +void print_regmap(const char *name, const signed char *regmap) { - int i; - int r; - u_int will_dirty_i,will_dirty_next,temp_will_dirty; - u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; - if(iend==slen-1) { - will_dirty_i=will_dirty_next=0; - wont_dirty_i=wont_dirty_next=0; - }else{ - will_dirty_i=will_dirty_next=will_dirty[iend+1]; - wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; - } - for (i=iend;i>=istart;i--) - { - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) - { - if(ba[i]=(start+slen*4)) - { - // Branch out of this block, flush all regs - if (is_ujump(i)) - { - // Unconditional branch - will_dirty_i=0; - wont_dirty_i=0; - // Merge in delay slot (will dirty) - for(r=0;r33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<33) temp_will_dirty&=~(1<0 && (regmap_pre[i][r]&63)<34) { - temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<>2,i-1,0); - }else{ - // Limit recursion. It can take an excessive amount - // of time if there are a lot of nested loops. - will_dirty[(ba[i]-start)>>2]=0; - wont_dirty[(ba[i]-start)>>2]=-1; - } - } - /*else*/ if(1) - { - if (is_ujump(i)) - { - // Unconditional branch - will_dirty_i=0; - wont_dirty_i=0; - //if(ba[i]>start+i*4) { // Disable recursion (for debugging) - for(r=0;r>2].regmap_entry[r]) { - will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { - will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<>2]>>(branch_regs[i].regmap[r]&63))&1)<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<start+i*4) { // Disable recursion (for debugging) - for(r=0;r>2].regmap_entry[r]) { - will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { - will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<>2]>>(target_reg&63))&1)<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<33) will_dirty_i&=~(1<istart) { - if(dops[i].itype!=RJUMP&&dops[i].itype!=UJUMP&&dops[i].itype!=CJUMP&&dops[i].itype!=SJUMP) - { - // Don't store a register immediately after writing it, - // may prevent dual-issue. - if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<>r)&1));*/} - } - } - } - } - else - { - if(i>r)&1));*/} - } - } - } - } - #endif - //} - } - // Deal with changed mappings - temp_will_dirty=will_dirty_i; - temp_wont_dirty=wont_dirty_i; - for(r=0;r=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) { - // Register moved to a different register - will_dirty_i&=~(1<>nr)&1)<>nr)&1)<0 && (regmap_pre[i][r]&63)<34) { - will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<>(regmap_pre[i][r]&63))&1)<>r)&1));*/ - } - } - } - } + char buf[5]; + int i, l; + fputs(name, stdout); + for (i = 0; i < HOST_REGS; i++) { + l = 0; + if (regmap[i] >= 0) + l = snprintf(buf, sizeof(buf), "$%d", regmap[i]); + for (; l < 3; l++) + buf[l] = ' '; + buf[l] = 0; + printf(" r%d=%s", i, buf); } + fputs("\n", stdout); } -#ifdef DISASM /* disassembly */ void disassemble_inst(int i) { @@ -6713,8 +6306,19 @@ void disassemble_inst(int i) //printf (" %s %8x\n",insn[i],source[i]); printf (" %x: %s\n",start+i*4,insn[i]); } + return; + printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n", + regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]); + print_regmap("pre: ", regmap_pre[i]); + print_regmap("entry: ", regs[i].regmap_entry); + print_regmap("map: ", regs[i].regmap); + if (dops[i].is_jump) { + print_regmap("bentry:", branch_regs[i].regmap_entry); + print_regmap("bmap: ", branch_regs[i].regmap); + } } #else +#define set_mnemonic(i_, n_) static void disassemble_inst(int i) {} #endif // DISASM @@ -6733,7 +6337,7 @@ static void new_dynarec_test(void) SysPrintf("linkage_arm* miscompilation/breakage detected.\n"); } - SysPrintf("testing if we can run recompiled code...\n"); + SysPrintf("testing if we can run recompiled code @%p...\n", out); ((volatile u_int *)out)[0]++; // make cache dirty for (i = 0; i < ARRAY_SIZE(ret); i++) { @@ -6763,7 +6367,6 @@ void new_dynarec_clear_full(void) memset(invalid_code,1,sizeof(invalid_code)); memset(hash_table,0xff,sizeof(hash_table)); memset(mini_ht,-1,sizeof(mini_ht)); - memset(restore_candidate,0,sizeof(restore_candidate)); memset(shadow,0,sizeof(shadow)); copy=shadow; expirep=16384; // Expiry pointer, +2 blocks @@ -6771,6 +6374,8 @@ void new_dynarec_clear_full(void) literalcount=0; stop_after_jal=0; inv_code_start=inv_code_end=~0; + hack_addr=0; + f1_hack=0; // TLB for(n=0;n<4096;n++) ll_clear(jump_in+n); for(n=0;n<4096;n++) ll_clear(jump_out+n); @@ -6782,16 +6387,24 @@ void new_dynarec_clear_full(void) void new_dynarec_init(void) { - SysPrintf("Init new dynarec\n"); + SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc)); +#ifdef _3DS + check_rosalina(); +#endif #ifdef BASE_ADDR_DYNAMIC #ifdef VITA - sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2); - if (sceBlock < 0) - SysPrintf("sceKernelAllocMemBlockForVM failed\n"); + sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc)); + if (sceBlock <= 0) + SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock); int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc); if (ret < 0) - SysPrintf("sceKernelGetMemBlockBase failed\n"); + SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret); + sceKernelOpenVMDomain(); + sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache); + #elif defined(_MSC_VER) + ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE, + PAGE_EXECUTE_READWRITE); #else uintptr_t desired_addr = 0; #ifdef __ELF__ @@ -6809,7 +6422,8 @@ void new_dynarec_init(void) #else #ifndef NO_WRITE_EXEC // not all systems allow execute in data segment by default - if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops), + // size must be 4K aligned for 3DS? + if (mprotect(ndrc, sizeof(*ndrc), PROT_READ | PROT_WRITE | PROT_EXEC) != 0) SysPrintf("mprotect() failed: %s\n", strerror(errno)); #endif @@ -6823,11 +6437,11 @@ void new_dynarec_init(void) #endif arch_init(); new_dynarec_test(); -#ifndef RAM_FIXED ram_offset=(uintptr_t)rdram-0x80000000; -#endif if (ram_offset!=0) SysPrintf("warning: RAM is not directly mapped, performance will suffer\n"); + SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n"); + SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out); } void new_dynarec_cleanup(void) @@ -6835,8 +6449,9 @@ void new_dynarec_cleanup(void) int n; #ifdef BASE_ADDR_DYNAMIC #ifdef VITA - sceKernelFreeMemBlock(sceBlock); - sceBlock = -1; + // sceBlock is managed by retroarch's bootstrap code + //sceKernelFreeMemBlock(sceBlock); + //sceBlock = -1; #else if (munmap(ndrc, sizeof(*ndrc)) < 0) SysPrintf("munmap() failed\n"); @@ -6848,13 +6463,11 @@ void new_dynarec_cleanup(void) #ifdef ROM_COPY if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");} #endif + new_dynarec_print_stats(); } static u_int *get_source_start(u_int addr, u_int *limit) { - if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 0; - if (addr < 0x00200000 || (0xa0000000 <= addr && addr < 0xa0200000)) { @@ -6869,7 +6482,7 @@ static u_int *get_source_start(u_int addr, u_int *limit) // BIOS. The multiplier should be much higher as it's uncached 8bit mem, // but timings in PCSX are too tied to the interpreter's BIAS if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M)) - cycle_multiplier_override = 200; + cycle_multiplier_active = 200; *limit = (addr & 0xfff00000) | 0x80000; return (u_int *)((u_char *)psxR + (addr&0x7ffff)); @@ -6981,259 +6594,255 @@ void new_dynarec_load_blocks(const void *save, int size) memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save)); } -int new_recompile_block(u_int addr) +void new_dynarec_print_stats(void) { - u_int pagelimit = 0; - u_int state_rflags = 0; - int i; - - assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); - //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr); - //if(debug) - //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29); - - // this is just for speculation - for (i = 1; i < 32; i++) { - if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) - state_rflags |= 1 << i; - } - - start = (u_int)addr&~3; - //assert(((u_int)addr&1)==0); // start-in-delay-slot flag - new_dynarec_did_compile=1; - if (Config.HLE && start == 0x80001000) // hlecall - { - // XXX: is this enough? Maybe check hleSoftCall? - void *beginning=start_block(); - u_int page=get_page(start); +#ifdef STAT_PRINT + printf("cc %3d,%3d,%3d lu%3d,%3d c%3d inv%3d,%3d tc_offs %zu\n", + stat_bc_pre, stat_bc_direct, stat_bc_restore, + stat_jump_in_lookups, stat_restore_tries, stat_restore_compares, + stat_inv_addr_calls, stat_inv_hits, + out - ndrc->translation_cache); + stat_bc_direct = stat_bc_pre = stat_bc_restore = + stat_jump_in_lookups = stat_restore_tries = stat_restore_compares = + stat_inv_addr_calls = stat_inv_hits = 0; +#endif +} - invalid_code[start>>12]=0; - emit_movimm(start,0); - emit_writeword(0,&pcaddr); - emit_far_jump(new_dyna_leave); - literal_pool(0); - end_block(beginning); - ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); +static int apply_hacks(void) +{ + int i; + if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS)) return 0; + /* special hack(s) */ + for (i = 0; i < slen - 4; i++) + { + // lui a4, 0xf200; jal ; addu a0, 2; slti v0, 28224 + if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP + && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a + && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2) + { + SysPrintf("PE2 hack @%08x\n", start + (i+3)*4); + dops[i + 3].itype = NOP; + } } - - source = get_source_start(start, &pagelimit); - if (source == NULL) { - SysPrintf("Compile at bogus memory address: %08x\n", addr); - abort(); + i = slen; + if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008 + && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809 + && dops[i-7].itype == STORE) + { + i = i-8; + if (dops[i].itype == IMM16) + i--; + // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6 + if (dops[i].itype == STORELR && dops[i].rs1 == 6 + && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6) + { + SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr); + f1_hack = 1; + return 1; + } } + return 0; +} - /* Pass 1: disassemble */ - /* Pass 2: register dependencies, branch targets */ - /* Pass 3: register allocation */ - /* Pass 4: branch dependencies */ - /* Pass 5: pre-alloc */ - /* Pass 6: optimize clean/dirty state */ - /* Pass 7: flag 32-bit registers */ - /* Pass 8: assembly */ - /* Pass 9: linker */ - /* Pass 10: garbage collection / free memory */ - - int j; - int done=0; +static noinline void pass1_disassemble(u_int pagelimit) +{ + int i, j, done = 0, ni_count = 0; unsigned int type,op,op2; - //printf("addr = %x source = %x %x\n", addr,source,source[0]); - - /* Pass 1 disassembly */ - - for(i=0;!done;i++) { - dops[i].bt=0; - dops[i].likely=0; - dops[i].ooo=0; + for (i = 0; !done; i++) + { + memset(&dops[i], 0, sizeof(dops[i])); op2=0; minimum_free_regs[i]=0; dops[i].opcode=op=source[i]>>26; switch(op) { - case 0x00: strcpy(insn[i],"special"); type=NI; + case 0x00: set_mnemonic(i, "special"); type=NI; op2=source[i]&0x3f; switch(op2) { - case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break; - case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break; - case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break; - case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break; - case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break; - case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break; - case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break; - case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break; - case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break; - case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break; - case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break; - case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break; - case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break; - case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break; - case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break; - case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break; - case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break; - case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break; - case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break; - case 0x20: strcpy(insn[i],"ADD"); type=ALU; break; - case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break; - case 0x22: strcpy(insn[i],"SUB"); type=ALU; break; - case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break; - case 0x24: strcpy(insn[i],"AND"); type=ALU; break; - case 0x25: strcpy(insn[i],"OR"); type=ALU; break; - case 0x26: strcpy(insn[i],"XOR"); type=ALU; break; - case 0x27: strcpy(insn[i],"NOR"); type=ALU; break; - case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break; - case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break; - case 0x30: strcpy(insn[i],"TGE"); type=NI; break; - case 0x31: strcpy(insn[i],"TGEU"); type=NI; break; - case 0x32: strcpy(insn[i],"TLT"); type=NI; break; - case 0x33: strcpy(insn[i],"TLTU"); type=NI; break; - case 0x34: strcpy(insn[i],"TEQ"); type=NI; break; - case 0x36: strcpy(insn[i],"TNE"); type=NI; break; + case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break; + case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break; + case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break; + case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break; + case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break; + case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break; + case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break; + case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break; + case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break; + case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break; + case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break; + case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break; + case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break; + case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break; + case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break; + case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break; + case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break; + case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break; + case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break; + case 0x20: set_mnemonic(i, "ADD"); type=ALU; break; + case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break; + case 0x22: set_mnemonic(i, "SUB"); type=ALU; break; + case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break; + case 0x24: set_mnemonic(i, "AND"); type=ALU; break; + case 0x25: set_mnemonic(i, "OR"); type=ALU; break; + case 0x26: set_mnemonic(i, "XOR"); type=ALU; break; + case 0x27: set_mnemonic(i, "NOR"); type=ALU; break; + case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break; + case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break; + case 0x30: set_mnemonic(i, "TGE"); type=NI; break; + case 0x31: set_mnemonic(i, "TGEU"); type=NI; break; + case 0x32: set_mnemonic(i, "TLT"); type=NI; break; + case 0x33: set_mnemonic(i, "TLTU"); type=NI; break; + case 0x34: set_mnemonic(i, "TEQ"); type=NI; break; + case 0x36: set_mnemonic(i, "TNE"); type=NI; break; #if 0 - case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break; - case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break; - case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break; - case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break; - case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break; - case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break; - case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break; - case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break; - case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break; - case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break; - case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break; - case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break; - case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break; - case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break; - case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break; - case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break; - case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break; + case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break; + case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break; + case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break; + case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break; + case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break; + case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break; + case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break; + case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break; + case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break; + case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break; + case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break; + case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break; + case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break; + case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break; + case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break; + case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break; + case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break; #endif } break; - case 0x01: strcpy(insn[i],"regimm"); type=NI; + case 0x01: set_mnemonic(i, "regimm"); type=NI; op2=(source[i]>>16)&0x1f; switch(op2) { - case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break; - case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break; - //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break; - //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break; - //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break; - //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break; - //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break; - //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break; - //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break; - //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break; - case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break; - case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break; - //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break; - //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break; + case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break; + case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break; + //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break; + //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break; + //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break; + //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break; + //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break; + //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break; + //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break; + //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break; + case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break; + case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break; + //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break; + //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break; } break; - case 0x02: strcpy(insn[i],"J"); type=UJUMP; break; - case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break; - case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break; - case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break; - case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break; - case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break; - case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break; - case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break; - case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break; - case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break; - case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break; - case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break; - case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break; - case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break; - case 0x10: strcpy(insn[i],"cop0"); type=NI; + case 0x02: set_mnemonic(i, "J"); type=UJUMP; break; + case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break; + case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break; + case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break; + case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break; + case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break; + case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break; + case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break; + case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break; + case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break; + case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break; + case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break; + case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break; + case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break; + case 0x10: set_mnemonic(i, "cop0"); type=NI; op2=(source[i]>>21)&0x1f; switch(op2) { - case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break; - case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break; - case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break; - case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break; - case 0x10: strcpy(insn[i],"RFE"); type=COP0; break; + case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break; + case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break; + case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break; + case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break; + case 0x10: set_mnemonic(i, "RFE"); type=COP0; break; } break; - case 0x11: strcpy(insn[i],"cop1"); type=COP1; + case 0x11: set_mnemonic(i, "cop1"); type=COP1; op2=(source[i]>>21)&0x1f; break; #if 0 - case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break; - case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break; - case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break; - case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break; - case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break; - case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break; - case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break; - case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break; + case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break; + case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break; + case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break; + case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break; + case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break; + case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break; + case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break; + case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break; #endif - case 0x20: strcpy(insn[i],"LB"); type=LOAD; break; - case 0x21: strcpy(insn[i],"LH"); type=LOAD; break; - case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break; - case 0x23: strcpy(insn[i],"LW"); type=LOAD; break; - case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break; - case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break; - case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break; + case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; + case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; + case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break; + case 0x23: set_mnemonic(i, "LW"); type=LOAD; break; + case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break; + case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break; + case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break; #if 0 - case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break; + case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break; #endif - case 0x28: strcpy(insn[i],"SB"); type=STORE; break; - case 0x29: strcpy(insn[i],"SH"); type=STORE; break; - case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break; - case 0x2B: strcpy(insn[i],"SW"); type=STORE; break; + case 0x28: set_mnemonic(i, "SB"); type=STORE; break; + case 0x29: set_mnemonic(i, "SH"); type=STORE; break; + case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break; + case 0x2B: set_mnemonic(i, "SW"); type=STORE; break; #if 0 - case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break; - case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break; + case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break; + case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break; #endif - case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break; - case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break; - case 0x30: strcpy(insn[i],"LL"); type=NI; break; - case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break; + case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break; + case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break; + case 0x30: set_mnemonic(i, "LL"); type=NI; break; + case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break; #if 0 - case 0x34: strcpy(insn[i],"LLD"); type=NI; break; - case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break; - case 0x37: strcpy(insn[i],"LD"); type=LOAD; break; + case 0x34: set_mnemonic(i, "LLD"); type=NI; break; + case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break; + case 0x37: set_mnemonic(i, "LD"); type=LOAD; break; #endif - case 0x38: strcpy(insn[i],"SC"); type=NI; break; - case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break; + case 0x38: set_mnemonic(i, "SC"); type=NI; break; + case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break; #if 0 - case 0x3C: strcpy(insn[i],"SCD"); type=NI; break; - case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break; - case 0x3F: strcpy(insn[i],"SD"); type=STORE; break; + case 0x3C: set_mnemonic(i, "SCD"); type=NI; break; + case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break; + case 0x3F: set_mnemonic(i, "SD"); type=STORE; break; #endif - case 0x12: strcpy(insn[i],"COP2"); type=NI; + case 0x12: set_mnemonic(i, "COP2"); type=NI; op2=(source[i]>>21)&0x1f; //if (op2 & 0x10) if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns if (gte_handlers[source[i]&0x3f]!=NULL) { +#ifdef DISASM if (gte_regnames[source[i]&0x3f]!=NULL) strcpy(insn[i],gte_regnames[source[i]&0x3f]); else snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f); +#endif type=C2OP; } } else switch(op2) { - case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break; - case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break; - case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break; - case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break; + case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break; + case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break; + case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break; + case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break; } break; - case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break; - case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break; - case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break; - default: strcpy(insn[i],"???"); type=NI; - SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr); + case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; + case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; + case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break; + default: set_mnemonic(i, "???"); type=NI; + SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start); break; } dops[i].itype=type; dops[i].opcode2=op2; /* Get registers/immediates */ - dops[i].lt1=0; + dops[i].use_lt1=0; gte_rs[i]=gte_rt[i]=0; switch(type) { case LOAD: @@ -7302,7 +6911,6 @@ int new_recompile_block(u_int addr) if(op&2) { // BGTZ/BLEZ dops[i].rs2=0; } - dops[i].likely=(op>>4)?1:0; break; case SJUMP: dops[i].rs1=(source[i]>>21)&0x1f; @@ -7313,7 +6921,6 @@ int new_recompile_block(u_int addr) dops[i].rt1=31; // NOTE: If the branch is not taken, r31 is still overwritten } - dops[i].likely=(op2&2)?1:0; break; case ALU: dops[i].rs1=(source[i]>>21)&0x1f; // source @@ -7457,13 +7064,18 @@ int new_recompile_block(u_int addr) else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1)) dops[i].itype = type = UJUMP; + dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP); + dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0 + dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2 + dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2 + /* messy cases to just pass over to the interpreter */ - if (i > 0 && is_jump(i-1)) { + if (i > 0 && dops[i-1].is_jump) { int do_in_intrp=0; // branch in delay slot? - if (is_jump(i)) { + if (dops[i].is_jump) { // don't handle first branch and call interpreter if it's hit - SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; } // basic load delay detection @@ -7471,31 +7083,47 @@ int new_recompile_block(u_int addr) int t=(ba[i-1]-start)/4; if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) { // jump target wants DS result - potential load delay effect - SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("load delay @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; dops[t+1].bt=1; // expected return from interpreter } else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&& - !(i>=3&&is_jump(i-3))) { + !(i>=3&&dops[i-3].is_jump)) { // v0 overwrite like this is a sign of trouble, bail out - SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr); + SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start); do_in_intrp=1; } } - if(do_in_intrp) { - dops[i-1].rs1=CCREG; - dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0; - ba[i-1]=-1; - dops[i-1].itype=INTCALL; - done=2; + if (do_in_intrp) { + memset(&dops[i-1], 0, sizeof(dops[i-1])); + dops[i-1].itype = INTCALL; + dops[i-1].rs1 = CCREG; + ba[i-1] = -1; + done = 2; i--; // don't compile the DS } } /* Is this the end of the block? */ - if (i > 0 && is_ujump(i-1)) { - if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL) - done=2; + if (i > 0 && dops[i-1].is_ujump) { + if (dops[i-1].rt1 == 0) { // not jal + int found_bbranch = 0, t = (ba[i-1] - start) / 4; + if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) { + // scan for a branch back to i+1 + for (j = t; j < t + 64; j++) { + int tmpop = source[j] >> 26; + if (tmpop == 1 || ((tmpop & ~3) == 4)) { + int t2 = j + 1 + (int)(signed short)source[j]; + if (t2 == i + 1) { + //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4); + found_bbranch = 1; + break; + } + } + } + } + if (!found_bbranch) + done = 2; } else { if(stop_after_jal) done=1; @@ -7507,9 +7135,9 @@ int new_recompile_block(u_int addr) // Don't get too close to the limit if(i>MAXBLOCK/2) done=1; } - if(dops[i].itype==SYSCALL&&stop_after_jal) done=1; - if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2; - if(done==2) { + if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL) + done = stop_after_jal ? 1 : 2; + if (done == 2) { // Does the block continue due to a branch? for(j=i-1;j>=0;j--) { @@ -7523,39 +7151,193 @@ int new_recompile_block(u_int addr) assert(start+i*4 8 || dops[i].opcode == 0x11)) { done=stop_after_jal=1; SysPrintf("Disabled speculative precompilation\n"); } } slen=i; - if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP||dops[i-1].itype==RJUMP) { + if (dops[i-1].is_jump) { if(start+i*4==pagelimit) { dops[i-1].itype=SPAN; } } - assert(slen>0); - - /* Pass 2 - Register dependencies and branch targets */ - - unneeded_registers(0,slen-1,0); - - /* Pass 3 - Register allocation */ + assert(slen>0); +} + +// Basic liveness analysis for MIPS registers +static noinline void pass2_unneeded_regs(int istart,int iend,int r) +{ + int i; + uint64_t u,gte_u,b,gte_b; + uint64_t temp_u,temp_gte_u=0; + uint64_t gte_u_unknown=0; + if (HACK_ENABLED(NDHACK_GTE_UNNEEDED)) + gte_u_unknown=~0ll; + if(iend==slen-1) { + u=1; + gte_u=gte_u_unknown; + }else{ + //u=unneeded_reg[iend+1]; + u=1; + gte_u=gte_unneeded[iend+1]; + } + + for (i=iend;i>=istart;i--) + { + //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r); + if(dops[i].is_jump) + { + // If subroutine call, flag return address as a possible branch target + if(dops[i].rt1==31 && i=(start+slen*4)) + { + // Branch out of this block, flush all regs + u=1; + gte_u=gte_u_unknown; + branch_unneeded_reg[i]=u; + // Merge in delay slot + u|=(1LL<>2].bt=1; + if(ba[i]<=start+i*4) { + // Backward branch + if(dops[i].is_ujump) + { + // Unconditional branch + temp_u=1; + temp_gte_u=0; + } else { + // Conditional branch (not taken case) + temp_u=unneeded_reg[i+2]; + temp_gte_u&=gte_unneeded[i+2]; + } + // Merge in delay slot + temp_u|=(1LL<>2,i-1,r+1); + }else{ + unneeded_reg[(ba[i]-start)>>2]=1; + gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown; + } + } /*else*/ if(1) { + if (dops[i].is_ujump) + { + // Unconditional branch + u=unneeded_reg[(ba[i]-start)>>2]; + gte_u=gte_unneeded[(ba[i]-start)>>2]; + branch_unneeded_reg[i]=u; + // Merge in delay slot + u|=(1LL<>2]; + gte_b=gte_unneeded[(ba[i]-start)>>2]; + branch_unneeded_reg[i]=b; + // Branch delay slot + b|=(1LL<>r)&1) { + if(r==HIREG) printf(" HI"); + else if(r==LOREG) printf(" LO"); + else printf(" r%d",r); + } + } + printf("\n"); + */ + } +} +static noinline void pass3_register_alloc(u_int addr) +{ struct regstat current; // Current register allocations/status - current.dirty=0; - current.u=unneeded_reg[0]; + clear_all_regs(current.regmap_entry); clear_all_regs(current.regmap); - alloc_reg(¤t,0,CCREG); - dirty_reg(¤t,CCREG); - current.isconst=0; - current.wasconst=0; - current.waswritten=0; + current.wasdirty = current.dirty = 0; + current.u = unneeded_reg[0]; + alloc_reg(¤t, 0, CCREG); + dirty_reg(¤t, CCREG); + current.wasconst = 0; + current.isconst = 0; + current.loadedconst = 0; + current.waswritten = 0; int ds=0; int cc=0; - int hr=-1; + int hr; + int i, j; - if((u_int)addr&1) { + if (addr & 1) { // First instruction is delay slot cc=-1; dops[1].bt=1; @@ -7568,7 +7350,6 @@ int new_recompile_block(u_int addr) { if(dops[i].bt) { - int hr; for(hr=0;hr=TEMPREG){ + if(or<0||r>=TEMPREG){ regs[i].regmap_entry[hr]=-1; } else @@ -7900,7 +7687,7 @@ int new_recompile_block(u_int addr) // Just move it to a different register regs[i].regmap_entry[hr]=r; // If it was dirty before, it's still dirty - if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63); + if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r); } } else @@ -8106,7 +7893,7 @@ int new_recompile_block(u_int addr) break; } - if (is_ujump(i-1)) + if (dops[i-1].is_ujump) { if(dops[i-1].rt1==31) // JAL/JALR { @@ -8147,8 +7934,8 @@ int new_recompile_block(u_int addr) } // Count cycles in between branches - ccadj[i]=cc; - if(i>0&&(dops[i-1].itype==RJUMP||dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP||dops[i].itype==SYSCALL||dops[i].itype==HLECALL)) + ccadj[i] = CLOCK_ADJUST(cc); + if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL)) { cc=0; } @@ -8190,15 +7977,19 @@ int new_recompile_block(u_int addr) if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1; regs[i].waswritten=current.waswritten; } +} - /* Pass 4 - Cull unused host registers */ - - uint64_t nr=0; +static noinline void pass4_cull_unused_regs(void) +{ + u_int last_needed_regs[4] = {0,0,0,0}; + u_int nr=0; + int i; for (i=slen-1;i>=0;i--) { int hr; - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + __builtin_prefetch(regs[i-2].regmap); + if(dops[i].is_jump) { if(ba[i]=(start+slen*4)) { @@ -8219,10 +8010,10 @@ int new_recompile_block(u_int addr) } } // Conditional branch may need registers for following instructions - if (!is_ujump(i)) + if (!dops[i].is_ujump) { if(i=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1< 0 && !dops[i].bt && regs[i].wasdirty) for(hr=0;hr0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) { + if((regs[i].wasdirty>>hr)&1) { if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) { - if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) { - if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<>hr)&1)) { if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1; - if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 && - (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && - (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG) - { - if (!is_ujump(i)) - { - if(dops[i].likely) { - regs[i].regmap[hr]=-1; - regs[i].isconst&=~(1<0) { - int map=-1,temp=-1; - if(dops[i].itype==STORE || dops[i].itype==STORELR || - (dops[i].opcode&0x3b)==0x39 || (dops[i].opcode&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2 - map=INVCP; - } - if(dops[i].itype==LOADLR || dops[i].itype==STORELR || - dops[i].itype==C1LS || dops[i].itype==C2LS) - temp=FTEMP; - if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 && + int map1 = -1, map2 = -1, temp=-1; + if (dops[i].is_load || dops[i].is_store) + map1 = ROREG; + if (dops[i].is_store) + map2 = INVCP; + if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS) + temp = FTEMP; + if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 && regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 && - (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map && - (dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)) + regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 && + //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG) + regs[i].regmap[hr] != CCREG) { if(i>2; - if(t>0&&(dops[t-1].itype!=UJUMP&&dops[t-1].itype!=RJUMP&&dops[t-1].itype!=CJUMP&&dops[t-1].itype!=SJUMP)) // loop_preload can't handle jumps into delay slots + if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated for(hr=0;hr %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); if(r<34&&((unneeded_reg[j]>>r)&1)) break; assert(r < 64); - if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63) %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r); int k; if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) { + if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break; if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break; - if(r>63) { - if(get_reg(regs[i].regmap,r&63)<0) break; - if(get_reg(branch_regs[i].regmap,r&63)<0) break; - } k=i; while(k>1&®s[k-1].regmap[hr]==-1) { if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) { @@ -8506,7 +8285,7 @@ int new_recompile_block(u_int addr) //printf("no-match due to different register\n"); break; } - if(dops[k-2].itype==UJUMP||dops[k-2].itype==RJUMP||dops[k-2].itype==CJUMP||dops[k-2].itype==SJUMP) { + if (dops[k-2].is_jump) { //printf("no-match due to branch\n"); break; } @@ -8514,7 +8293,6 @@ int new_recompile_block(u_int addr) if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) { break; } - assert(r < 64); k--; } if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) { @@ -8555,7 +8333,7 @@ int new_recompile_block(u_int addr) branch_regs[i].dirty|=(1<=0) { if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) @@ -8792,8 +8574,11 @@ int new_recompile_block(u_int addr) ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) { hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1); - if(hr<0) hr=get_reg(regs[i+1].regmap,-1); - else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<=0); if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { @@ -8844,13 +8629,14 @@ int new_recompile_block(u_int addr) } } if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) { + hr = -1; if(dops[i+1].itype==LOAD) hr=get_reg(regs[i+1].regmap,dops[i+1].rt1); if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2 hr=get_reg(regs[i+1].regmap,FTEMP); if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1)); - if(hr<0) hr=get_reg(regs[i+1].regmap,-1); + if(hr<0) hr=get_reg_temp(regs[i+1].regmap); } if(hr>=0&®s[i].regmap[hr]<0) { int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1); @@ -8868,9 +8654,527 @@ int new_recompile_block(u_int addr) } } } +} + +// Write back dirty registers as soon as we will no longer modify them, +// so that we don't end up with lots of writes at the branches. +static noinline void pass6_clean_registers(int istart, int iend, int wr) +{ + static u_int wont_dirty[MAXBLOCK]; + static u_int will_dirty[MAXBLOCK]; + int i; + int r; + u_int will_dirty_i,will_dirty_next,temp_will_dirty; + u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty; + if(iend==slen-1) { + will_dirty_i=will_dirty_next=0; + wont_dirty_i=wont_dirty_next=0; + }else{ + will_dirty_i=will_dirty_next=will_dirty[iend+1]; + wont_dirty_i=wont_dirty_next=wont_dirty[iend+1]; + } + for (i=iend;i>=istart;i--) + { + signed char rregmap_i[RRMAP_SIZE]; + u_int hr_candirty = 0; + assert(HOST_REGS < 32); + make_rregs(regs[i].regmap, rregmap_i, &hr_candirty); + __builtin_prefetch(regs[i-1].regmap); + if(dops[i].is_jump) + { + signed char branch_rregmap_i[RRMAP_SIZE]; + u_int branch_hr_candirty = 0; + make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty); + if(ba[i]=(start+slen*4)) + { + // Branch out of this block, flush all regs + will_dirty_i = 0; + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + will_dirty_i &= branch_hr_candirty; + if (dops[i].is_ujump) + { + // Unconditional branch + wont_dirty_i = 0; + // Merge in delay slot (will dirty) + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + will_dirty_i &= hr_candirty; + } + else + { + // Conditional branch + wont_dirty_i = wont_dirty_next; + // Merge in delay slot (will dirty) + // (the original code had no explanation why these 2 are commented out) + //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + will_dirty_i &= hr_candirty; + } + // Merge in delay slot (wont dirty) + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + wont_dirty_i &= ~(1u << 31); + if(wr) { + #ifndef DESTRUCTIVE_WRITEBACK + branch_regs[i].dirty&=wont_dirty_i; + #endif + branch_regs[i].dirty|=will_dirty_i; + } + } + else + { + // Internal branch + if(ba[i]<=start+i*4) { + // Backward branch + if (dops[i].is_ujump) + { + // Unconditional branch + temp_will_dirty=0; + temp_wont_dirty=0; + // Merge in delay slot (will dirty) + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_will_dirty &= branch_hr_candirty; + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_will_dirty &= hr_candirty; + } else { + // Conditional branch (not taken case) + temp_will_dirty=will_dirty_next; + temp_wont_dirty=wont_dirty_next; + // Merge in delay slot (will dirty) + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_will_dirty &= branch_hr_candirty; + //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_will_dirty &= hr_candirty; + } + // Merge in delay slot (wont dirty) + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31); + temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31); + temp_wont_dirty &= ~(1u << 31); + // Deal with changed mappings + if(i0 && regmap_pre[i][r]<34) { + temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>2,i-1,0); + }else{ + // Limit recursion. It can take an excessive amount + // of time if there are a lot of nested loops. + will_dirty[(ba[i]-start)>>2]=0; + wont_dirty[(ba[i]-start)>>2]=-1; + } + } + /*else*/ if(1) + { + if (dops[i].is_ujump) + { + // Unconditional branch + will_dirty_i=0; + wont_dirty_i=0; + //if(ba[i]>start+i*4) { // Disable recursion (for debugging) + for(r=0;r>2].regmap_entry[r]) { + will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { + will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<>2]>>branch_regs[i].regmap[r])&1)<start+i*4) // Disable recursion (for debugging) + for(r=0;r>2].regmap_entry[r]) { + will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<>2]&(1<=0) { + will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<>2]>>target_reg)&1)< istart && !dops[i].is_jump) { + // Don't store a register immediately after writing it, + // may prevent dual-issue. + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31); + wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31); + } + // Save it + will_dirty[i]=will_dirty_i; + wont_dirty[i]=wont_dirty_i; + // Mark registers that won't be dirtied as not dirty + if(wr) { + regs[i].dirty|=will_dirty_i; + #ifndef DESTRUCTIVE_WRITEBACK + regs[i].dirty&=wont_dirty_i; + if(dops[i].is_jump) + { + if (i < iend-1 && !dops[i].is_ujump) { + for(r=0;r>r)&1));*/} + } + } + } + } + else + { + if(i>r)&1));*/} + } + } + } + } + #endif + } + // Deal with changed mappings + temp_will_dirty=will_dirty_i; + temp_wont_dirty=wont_dirty_i; + for(r=0;r=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) { + // Register moved to a different register + will_dirty_i&=~(1<>nr)&1)<>nr)&1)<0 && regmap_pre[i][r]<34) { + will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<>regmap_pre[i][r])&1)<>r)&1));*/ + } + } + } + } + } +} + +static noinline void pass10_expire_blocks(void) +{ + int i, end; + end = (((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16)) + 16384) & 65535; + while (expirep != end) + { + int shift=TARGET_SIZE_2-3; // Divide into 8 blocks + uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block + uintptr_t base_offs_s = base_offs >> shift; + inv_debug("EXP: Phase %d\n",expirep); + switch((expirep>>11)&3) + { + case 0: + // Clear jump_in and jump_dirty + ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift); + ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift); + ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift); + ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift); + break; + case 1: + // Clear pointers + ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift); + ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift); + break; + case 2: + // Clear hash table + for(i=0;i<32;i++) { + struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i]; + uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache; + uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; + if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { + inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]); + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; + } + o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache; + o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; + if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { + inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]); + ht_bin->vaddr[0] = ht_bin->vaddr[1]; + ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; + ht_bin->vaddr[1] = -1; + ht_bin->tcaddr[1] = NULL; + } + } + break; + case 3: + // Clear jump_out + if((expirep&2047)==0) + do_clear_cache(); + ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift); + ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift); + break; + } + expirep=(expirep+1)&65535; + } +} + +int new_recompile_block(u_int addr) +{ + u_int pagelimit = 0; + u_int state_rflags = 0; + int i; + + assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out); + + // this is just for speculation + for (i = 1; i < 32; i++) { + if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000) + state_rflags |= 1 << i; + } + + start = (u_int)addr&~3; + //assert(((u_int)addr&1)==0); // start-in-delay-slot flag + new_dynarec_did_compile=1; + if (Config.HLE && start == 0x80001000) // hlecall + { + // XXX: is this enough? Maybe check hleSoftCall? + void *beginning=start_block(); + u_int page=get_page(start); + + invalid_code[start>>12]=0; + emit_movimm(start,0); + emit_writeword(0,&pcaddr); + emit_far_jump(new_dyna_leave); + literal_pool(0); + end_block(beginning); + ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning); + return 0; + } + else if (f1_hack && hack_addr == 0) { + void *beginning = start_block(); + u_int page = get_page(start); + emit_movimm(start, 0); + emit_writeword(0, &hack_addr); + emit_readword(&psxRegs.GPR.n.sp, 0); + emit_readptr(&mem_rtab, 1); + emit_shrimm(0, 12, 2); + emit_readptr_dualindexedx_ptrlen(1, 2, 1); + emit_addimm(0, 0x18, 0); + emit_adds_ptr(1, 1, 1); + emit_ldr_dualindexed(1, 0, 0); + emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp) + emit_far_call(get_addr_ht); + emit_jmpreg(0); // jr k0 + literal_pool(0); + end_block(beginning); + + ll_add_flags(jump_in + page, start, state_rflags, beginning); + SysPrintf("F1 hack to %08x\n", start); + return 0; + } + + cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT + ? cycle_multiplier_override : cycle_multiplier; + + source = get_source_start(start, &pagelimit); + if (source == NULL) { + if (addr != hack_addr) { + SysPrintf("Compile at bogus memory address: %08x\n", addr); + hack_addr = addr; + } + //abort(); + return -1; + } + + /* Pass 1: disassemble */ + /* Pass 2: register dependencies, branch targets */ + /* Pass 3: register allocation */ + /* Pass 4: branch dependencies */ + /* Pass 5: pre-alloc */ + /* Pass 6: optimize clean/dirty state */ + /* Pass 7: flag 32-bit registers */ + /* Pass 8: assembly */ + /* Pass 9: linker */ + /* Pass 10: garbage collection / free memory */ + + /* Pass 1 disassembly */ + + pass1_disassemble(pagelimit); + + int clear_hack_addr = apply_hacks(); + + /* Pass 2 - Register dependencies and branch targets */ + + pass2_unneeded_regs(0,slen-1,0); + + /* Pass 3 - Register allocation */ + + pass3_register_alloc(addr); + + /* Pass 4 - Cull unused host registers */ + + pass4_cull_unused_regs(); + + /* Pass 5 - Pre-allocate registers */ + + pass5a_preallocate1(); + pass5b_preallocate2(); /* Pass 6 - Optimize clean/dirty state */ - clean_registers(0,slen-1,1); + pass6_clean_registers(0, slen-1, 1); /* Pass 7 - Identify 32-bit registers */ for (i=slen-1;i>=0;i--) @@ -8890,145 +9194,12 @@ int new_recompile_block(u_int addr) dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception } -#ifdef DISASM - /* Debug/disassembly */ - for(i=0;i>r)&1) { - if(r==HIREG) printf(" HI"); - else if(r==LOREG) printf(" LO"); - else printf(" r%d",r); - } - } - printf("\n"); - #if defined(__i386__) || defined(__x86_64__) - printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]); - #endif - #ifdef __arm__ - printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]); - #endif - #if defined(__i386__) || defined(__x86_64__) - printf("needs: "); - if(needed_reg[i]&1) printf("eax "); - if((needed_reg[i]>>1)&1) printf("ecx "); - if((needed_reg[i]>>2)&1) printf("edx "); - if((needed_reg[i]>>3)&1) printf("ebx "); - if((needed_reg[i]>>5)&1) printf("ebp "); - if((needed_reg[i]>>6)&1) printf("esi "); - if((needed_reg[i]>>7)&1) printf("edi "); - printf("\n"); - printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]); - printf("dirty: "); - if(regs[i].wasdirty&1) printf("eax "); - if((regs[i].wasdirty>>1)&1) printf("ecx "); - if((regs[i].wasdirty>>2)&1) printf("edx "); - if((regs[i].wasdirty>>3)&1) printf("ebx "); - if((regs[i].wasdirty>>5)&1) printf("ebp "); - if((regs[i].wasdirty>>6)&1) printf("esi "); - if((regs[i].wasdirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]); - printf("dirty: "); - if(regs[i].wasdirty&1) printf("r0 "); - if((regs[i].wasdirty>>1)&1) printf("r1 "); - if((regs[i].wasdirty>>2)&1) printf("r2 "); - if((regs[i].wasdirty>>3)&1) printf("r3 "); - if((regs[i].wasdirty>>4)&1) printf("r4 "); - if((regs[i].wasdirty>>5)&1) printf("r5 "); - if((regs[i].wasdirty>>6)&1) printf("r6 "); - if((regs[i].wasdirty>>7)&1) printf("r7 "); - if((regs[i].wasdirty>>8)&1) printf("r8 "); - if((regs[i].wasdirty>>9)&1) printf("r9 "); - if((regs[i].wasdirty>>10)&1) printf("r10 "); - if((regs[i].wasdirty>>12)&1) printf("r12 "); - #endif - printf("\n"); - disassemble_inst(i); - //printf ("ccadj[%d] = %d\n",i,ccadj[i]); - #if defined(__i386__) || defined(__x86_64__) - printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]); - if(regs[i].dirty&1) printf("eax "); - if((regs[i].dirty>>1)&1) printf("ecx "); - if((regs[i].dirty>>2)&1) printf("edx "); - if((regs[i].dirty>>3)&1) printf("ebx "); - if((regs[i].dirty>>5)&1) printf("ebp "); - if((regs[i].dirty>>6)&1) printf("esi "); - if((regs[i].dirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]); - if(regs[i].dirty&1) printf("r0 "); - if((regs[i].dirty>>1)&1) printf("r1 "); - if((regs[i].dirty>>2)&1) printf("r2 "); - if((regs[i].dirty>>3)&1) printf("r3 "); - if((regs[i].dirty>>4)&1) printf("r4 "); - if((regs[i].dirty>>5)&1) printf("r5 "); - if((regs[i].dirty>>6)&1) printf("r6 "); - if((regs[i].dirty>>7)&1) printf("r7 "); - if((regs[i].dirty>>8)&1) printf("r8 "); - if((regs[i].dirty>>9)&1) printf("r9 "); - if((regs[i].dirty>>10)&1) printf("r10 "); - if((regs[i].dirty>>12)&1) printf("r12 "); - #endif - printf("\n"); - if(regs[i].isconst) { - printf("constants: "); - #if defined(__i386__) || defined(__x86_64__) - if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]); - if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]); - if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]); - if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]); - if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]); - if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]); - if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]); - #endif - #if defined(__arm__) || defined(__aarch64__) - int r; - for (r = 0; r < ARRAY_SIZE(constmap[i]); r++) - if ((regs[i].isconst >> r) & 1) - printf(" r%d=%x", r, (u_int)constmap[i][r]); - #endif - printf("\n"); - } - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) { - #if defined(__i386__) || defined(__x86_64__) - printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]); - if(branch_regs[i].dirty&1) printf("eax "); - if((branch_regs[i].dirty>>1)&1) printf("ecx "); - if((branch_regs[i].dirty>>2)&1) printf("edx "); - if((branch_regs[i].dirty>>3)&1) printf("ebx "); - if((branch_regs[i].dirty>>5)&1) printf("ebp "); - if((branch_regs[i].dirty>>6)&1) printf("esi "); - if((branch_regs[i].dirty>>7)&1) printf("edi "); - #endif - #ifdef __arm__ - printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]); - if(branch_regs[i].dirty&1) printf("r0 "); - if((branch_regs[i].dirty>>1)&1) printf("r1 "); - if((branch_regs[i].dirty>>2)&1) printf("r2 "); - if((branch_regs[i].dirty>>3)&1) printf("r3 "); - if((branch_regs[i].dirty>>4)&1) printf("r4 "); - if((branch_regs[i].dirty>>5)&1) printf("r5 "); - if((branch_regs[i].dirty>>6)&1) printf("r6 "); - if((branch_regs[i].dirty>>7)&1) printf("r7 "); - if((branch_regs[i].dirty>>8)&1) printf("r8 "); - if((branch_regs[i].dirty>>9)&1) printf("r9 "); - if((branch_regs[i].dirty>>10)&1) printf("r10 "); - if((branch_regs[i].dirty>>12)&1) printf("r12 "); - #endif - } - } -#endif // DISASM - /* Pass 8 - Assembly */ linkcount=0;stubcount=0; - ds=0;is_delayslot=0; + is_delayslot=0; u_int dirty_pre=0; void *beginning=start_block(); + int ds = 0; if((u_int)addr&1) { ds=1; pagespan_ds(); @@ -9055,6 +9226,10 @@ int new_recompile_block(u_int addr) } for(i=0;i\n"); - drc_dbg_emit_do_cmp(i); + drc_dbg_emit_do_cmp(i, ccadj[i]); + if (clear_hack_addr) { + emit_movimm(0, 0); + emit_writeword(0, &hack_addr); + clear_hack_addr = 0; + } // load regs if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG) @@ -9091,15 +9271,17 @@ int new_recompile_block(u_int addr) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2); address_generation(i,®s[i],regs[i].regmap_entry); load_consts(regmap_pre[i],regs[i].regmap,i); - if(dops[i].itype==RJUMP||dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP) + if(dops[i].is_jump) { // Load the delay slot registers if necessary if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0)) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1); if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0)) load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2); - if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) - load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP); + if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) + load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG); + if (dops[i+1].is_store) + load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP); } else if(i+1 1) { - if(!is_ujump(i-2)&&dops[i-1].itype!=SPAN) { - assert(dops[i-1].itype!=UJUMP&&dops[i-1].itype!=CJUMP&&dops[i-1].itype!=SJUMP&&dops[i-1].itype!=RJUMP); + if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) { + assert(!dops[i-1].is_jump); assert(i==slen); if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) { store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); } - else if(!dops[i-2].likely) + else { store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4); assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG); } - else - { - store_regs_bt(regs[i-2].regmap,regs[i-2].dirty,start+i*4); - assert(regs[i-2].regmap[HOST_CCREG]==CCREG); - } add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9209,11 +9338,11 @@ int new_recompile_block(u_int addr) else { assert(i>0); - assert(dops[i-1].itype!=UJUMP&&dops[i-1].itype!=CJUMP&&dops[i-1].itype!=SJUMP&&dops[i-1].itype!=RJUMP); + assert(!dops[i-1].is_jump); store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4); if(regs[i-1].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG); - emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG); + emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG); add_to_linker(out,start+i*4,0); emit_jmp(0); } @@ -9339,73 +9468,16 @@ int new_recompile_block(u_int addr) out = ndrc->translation_cache; // Trap writes to any of the pages we compiled - for(i=start>>12;i<=(start+slen*4)>>12;i++) { - invalid_code[i]=0; - } - inv_code_start=inv_code_end=~0; - - // for PCSX we need to mark all mirrors too - if(get_page(start)<(RAM_SIZE>>12)) - for(i=start>>12;i<=(start+slen*4)>>12;i++) - invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]= - invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]= - invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0; + mark_valid_code(start, slen*4); /* Pass 10 - Free memory by expiring oldest blocks */ - int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535; - while(expirep!=end) - { - int shift=TARGET_SIZE_2-3; // Divide into 8 blocks - uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block - uintptr_t base_offs_s = base_offs >> shift; - inv_debug("EXP: Phase %d\n",expirep); - switch((expirep>>11)&3) - { - case 0: - // Clear jump_in and jump_dirty - ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift); - break; - case 1: - // Clear pointers - ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift); - ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift); - break; - case 2: - // Clear hash table - for(i=0;i<32;i++) { - struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i]; - uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache; - uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { - inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]); - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; - } - o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache; - o2 = o1 - MAX_OUTPUT_BLOCK_SIZE; - if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) { - inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]); - ht_bin->vaddr[0] = ht_bin->vaddr[1]; - ht_bin->tcaddr[0] = ht_bin->tcaddr[1]; - ht_bin->vaddr[1] = -1; - ht_bin->tcaddr[1] = NULL; - } - } - break; - case 3: - // Clear jump_out - if((expirep&2047)==0) - do_clear_cache(); - ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift); - ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift); - break; - } - expirep=(expirep+1)&65535; - } + pass10_expire_blocks(); + +#ifdef ASSEM_PRINT + fflush(stdout); +#endif + stat_inc(stat_bc_direct); return 0; }