X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fnew_dynarec.c;h=d7c243655a254cb63348d2528fde17686e163814;hb=4ee246ed0e02c61f0b33251d86ea74a4a0380a47;hp=dcf940d3ad9af9eeeba5e11c032abde17e84aa6b;hpb=a22ccd6a80307ef5f711332f68de96949cdeee76;p=pcsx_rearmed.git diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c index dcf940d3..d7c24365 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c @@ -81,7 +81,7 @@ static Jit g_jit; #endif #define RAM_SIZE 0x200000 -#define MAXBLOCK 4096 +#define MAXBLOCK 2048 #define MAX_OUTPUT_BLOCK_SIZE 262144 #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2) #define PAGE_COUNT 1024 @@ -242,8 +242,13 @@ static struct decoded_insn u_char is_delay_load:1; // is_load + MFC/CFC u_char is_exception:1; // unconditional, also interp. fallback u_char may_except:1; // might generate an exception + u_char ls_type:2; // load/store type (ls_width_type) } dops[MAXBLOCK]; +enum ls_width_type { + LS_8 = 0, LS_16, LS_32, LS_LR +}; + static struct compile_info { int imm; @@ -2109,28 +2114,18 @@ static void multdiv_alloc(struct regstat *current,int i) clear_const(current,dops[i].rs2); alloc_cc(current,i); // for stalls dirty_reg(current,CCREG); - if(dops[i].rs1&&dops[i].rs2) - { - current->u&=~(1LL<u&=~(1LL<u &= ~(1ull << HIREG); + current->u &= ~(1ull << LOREG); + alloc_reg(current, i, HIREG); + alloc_reg(current, i, LOREG); + dirty_reg(current, HIREG); + dirty_reg(current, LOREG); + if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u) { - // Multiply by zero is zero. - // MIPS does not have a divide by zero exception. - alloc_reg(current,i,HIREG); - alloc_reg(current,i,LOREG); - dirty_reg(current,HIREG); - dirty_reg(current,LOREG); - if (dops[i].rs1 && ((dops[i].opcode2 & 0x3e) == 0x1a)) // div(u) 0 - alloc_reg(current, i, dops[i].rs1); + alloc_reg(current, i, dops[i].rs1); + alloc_reg(current, i, dops[i].rs2); } + // else multiply by zero is zero } #endif @@ -3218,7 +3213,7 @@ static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_) static void do_invstub(int n) { literal_pool(20); - assem_debug("do_invstub\n"); + assem_debug("do_invstub %x\n", start + stubs[n].e*4); u_int reglist = stubs[n].a; u_int addrr = stubs[n].b; int ofs_start = stubs[n].c; @@ -3295,9 +3290,13 @@ static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglis imm_min -= cinfo[i].imm; imm_max -= cinfo[i].imm; add_stub(INVCODE_STUB, jaddr, out, reglist|(1<regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); offset=cinfo[i].imm; if(s>=0) { c=(i_regs->wasconst>>s)&1; - if(c) { - memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; + if (c) { + addr_const = constmap[i][s] + offset; + memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); } } assert(tl>=0); assert(addr >= 0); if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<regmap,dops[i].rs2,ccadj_,reglist); } + if (!c || is_ram_addr(addr_const)) + do_store_smc_check(i, i_regs, reglist, addr); + if (c && !memtarget) + inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist); // basic current block modification detection.. // not looking back as that should be in mips cache already // (see Spyro2 title->attract mode) - if(c&&start+i*4regmap==regs[i].regmap); // not delay slot if(i_regs->regmap==regs[i].regmap) { load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i); @@ -3407,18 +3400,21 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) void *done0, *done1, *done2; int memtarget=0,c=0; int offset_reg = -1; - u_int reglist=get_host_reglist(i_regs->regmap); + u_int addr_const = ~0; + u_int reglist = get_host_reglist(i_regs->regmap); tl=get_reg(i_regs->regmap,dops[i].rs2); s=get_reg(i_regs->regmap,dops[i].rs1); offset=cinfo[i].imm; if(s>=0) { - c=(i_regs->isconst>>s)&1; - if(c) { - memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE; + c = (i_regs->isconst >> s) & 1; + if (c) { + addr_const = constmap[i][s] + offset; + memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); } } assert(tl>=0); assert(addr >= 0); + reglist |= 1u << addr; if(!c) { emit_cmpimm(addr, RAM_SIZE); jaddr=out; @@ -3458,14 +3454,14 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) if (dops[i].opcode == 0x2A) { // SWL // Write two msb into two least significant bytes if (dops[i].rs2) emit_rorimm(tl, 16, tl); - do_store_hword(addr, -1, tl, offset_reg, 0); + do_store_hword(addr, -1, tl, offset_reg, 1); if (dops[i].rs2) emit_rorimm(tl, 16, tl); } else if (dops[i].opcode == 0x2E) { // SWR // Write 3 lsb into three most significant bytes do_store_byte(addr, tl, offset_reg); if (dops[i].rs2) emit_rorimm(tl, 8, tl); - do_store_hword(addr, 1, tl, offset_reg, 0); + do_store_hword(addr, 1, tl, offset_reg, 1); if (dops[i].rs2) emit_rorimm(tl, 24, tl); } done1=out; @@ -3493,7 +3489,7 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) // 3 set_jump_target(case3, out); if (dops[i].opcode == 0x2A) { // SWL - do_store_word(addr, -3, tl, offset_reg, 0); + do_store_word(addr, -3, tl, offset_reg, 1); } else if (dops[i].opcode == 0x2E) { // SWR do_store_byte(addr, tl, offset_reg); @@ -3503,9 +3499,10 @@ static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_) set_jump_target(done2, out); if (offset_reg == HOST_TEMPREG) host_tempreg_release(); - if(!c||!memtarget) + if (!c || !memtarget) add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist); - do_store_smc_check(i, i_regs, reglist, addr); + if (!c || is_ram_addr(addr_const)) + do_store_smc_check(i, i_regs, reglist, addr); } static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_) @@ -3897,6 +3894,7 @@ static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) enum stub_type type; int offset_reg = -1; int fastio_reg_override = -1; + u_int addr_const = ~0; u_int reglist=get_host_reglist(i_regs->regmap); u_int copr=(source[i]>>16)&0x1f; s=get_reg(i_regs->regmap,dops[i].rs1); @@ -3913,8 +3911,13 @@ static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) if (dops[i].opcode==0x3a) { // SWC2 reglist |= 1<=0) c=(i_regs->wasconst>>s)&1; - memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE); + if (s >= 0) { + c = (i_regs->isconst >> s) & 1; + if (c) { + addr_const = constmap[i][s] + offset; + memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE); + } + } cop2_do_stall_check(0, i, i_regs, reglist); @@ -3963,9 +3966,9 @@ static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_) host_tempreg_release(); if(jaddr2) add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist); - if(dops[i].opcode==0x3a) // SWC2 + if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2 do_store_smc_check(i, i_regs, reglist, ar); - if (dops[i].opcode==0x32) { // LWC2 + if (dops[i].opcode == 0x32) { // LWC2 host_tempreg_acquire(); cop2_put_dreg(copr,tl,HOST_TEMPREG); host_tempreg_release(); @@ -4529,12 +4532,6 @@ static void address_generation(int i, const struct regstat *i_regs, signed char cinfo[i].addr = rs; add_offset = 0; } - else if (dops[i].itype == STORELR) { // overwrites addr - assert(ra >= 0); - assert(rs != ra); - emit_mov(rs, ra); - cinfo[i].addr = ra; - } else cinfo[i].addr = rs; if (add_offset) { @@ -4631,11 +4628,13 @@ static void load_consts(signed char pre[],signed char regmap[],int i) if(i==0||dops[i].bt) regs[i].loadedconst=0; else { - for(hr=0;hr=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr] - &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1)) + for (hr = 0; hr < HOST_REGS; hr++) { + if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr]) + continue; + if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1) + && regmap[hr] == regs[i-1].regmap[hr]) { - regs[i].loadedconst|=1<> 21) & 0x1f; break; - case 0x20: set_mnemonic(i, "LB"); type=LOAD; break; - case 0x21: set_mnemonic(i, "LH"); type=LOAD; break; - case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break; - case 0x23: set_mnemonic(i, "LW"); type=LOAD; break; - case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break; - case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break; - case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break; - case 0x28: set_mnemonic(i, "SB"); type=STORE; break; - case 0x29: set_mnemonic(i, "SH"); type=STORE; break; - case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break; - case 0x2B: set_mnemonic(i, "SW"); type=STORE; break; - case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break; - case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break; - case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break; + case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break; + case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break; + case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break; + case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break; + case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break; + case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break; + case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break; + case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break; + case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break; + case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break; + case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break; + case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break; + case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break; + case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break; case 0x3B: if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) { set_mnemonic(i, "HLECALL"); @@ -6682,8 +6681,9 @@ static void disassemble_one(int i, u_int src) } if (type == INTCALL) SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start); - dops[i].itype=type; - dops[i].opcode2=op2; + dops[i].itype = type; + dops[i].opcode2 = op2; + dops[i].ls_type = ls_type; /* Get registers/immediates */ dops[i].use_lt1=0; gte_rs[i]=gte_rt[i]=0; @@ -6829,6 +6829,7 @@ static void disassemble_one(int i, u_int src) static noinline void pass1_disassemble(u_int pagelimit) { int i, j, done = 0, ni_count = 0; + int ds_next = 0; for (i = 0; !done; i++) { @@ -6836,6 +6837,7 @@ static noinline void pass1_disassemble(u_int pagelimit) unsigned int type, op, op2; disassemble_one(i, source[i]); + dops[i].is_ds = ds_next; ds_next = 0; type = dops[i].itype; op = dops[i].opcode; op2 = dops[i].opcode2; @@ -6868,6 +6870,7 @@ static noinline void pass1_disassemble(u_int pagelimit) dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL; dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8; + ds_next = dops[i].is_jump; if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU && ((cinfo[i].imm & 1) || Config.PreciseExceptions)) @@ -6972,12 +6975,13 @@ static noinline void pass1_disassemble(u_int pagelimit) // Don't recompile stuff that's already compiled if(check_addr(start+i*4+4)) done=1; // Don't get too close to the limit - if(i>MAXBLOCK/2) done=1; + if (i > MAXBLOCK - 64) + done = 1; } if (dops[i].itype == HLECALL) - stop = 1; + done = 1; else if (dops[i].itype == INTCALL) - stop = 2; + done = 2; else if (dops[i].is_exception) done = stop_after_jal ? 1 : 2; if (done == 2) { @@ -6992,7 +6996,8 @@ static noinline void pass1_disassemble(u_int pagelimit) //assert(i 8 || dops[i].opcode == 0x11)) { done=stop_after_jal=1; @@ -7155,6 +7160,31 @@ static noinline void pass2_unneeded_regs(int istart,int iend,int r) } } +static noinline void pass2a_unneeded_other(void) +{ + int i, j; + for (i = 0; i < slen; i++) + { + // remove redundant alignment checks + if (dops[i].may_except && (dops[i].is_load || dops[i].is_store) + && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds) + { + int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type; + int mask = ls_type == LS_32 ? 3 : 1; + lsb &= mask; + for (j = i + 1; j < slen; j++) { + if (dops[j].bt || dops[j].is_jump) + break; + if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base + && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb) + dops[j].may_except = 0; + if (dops[j].rt1 == base) + break; + } + } + } +} + static noinline void pass3_register_alloc(u_int addr) { struct regstat current; // Current register allocations/status @@ -7219,7 +7249,7 @@ static noinline void pass3_register_alloc(u_int addr) abort(); } } - dops[i].is_ds=ds; + assert(dops[i].is_ds == ds); if(ds) { ds=0; // Skip delay slot, already allocated as part of branch // ...but we need to alloc it in case something jumps here @@ -8356,6 +8386,7 @@ static noinline void pass5b_preallocate2(void) regs[i+2].wasdirty&=~(1<=0); + #if 0 // what is this for? double allocs $0 in ps1_rom.bin if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0) { regs[i].regmap[hr]=dops[i+1].rs1; @@ -8367,6 +8398,7 @@ static noinline void pass5b_preallocate2(void) regs[i+1].wasdirty&=~(1<