X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fpatches%2Ftrace_drc_chk;h=da8616988ed87ef540422f812dc98940fb56f3da;hb=HEAD;hp=93ca59802e05197fa2d3b1cc3ad2bf77df6b6be1;hpb=37387d8b2b8b9705ca42bd7582ed48d88aeafb9b;p=pcsx_rearmed.git diff --git a/libpcsxcore/new_dynarec/patches/trace_drc_chk b/libpcsxcore/new_dynarec/patches/trace_drc_chk index 93ca5980..99d1fde8 100644 --- a/libpcsxcore/new_dynarec/patches/trace_drc_chk +++ b/libpcsxcore/new_dynarec/patches/trace_drc_chk @@ -1,186 +1,35 @@ -diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S -index 1d8cefa..528929f 100644 ---- a/libpcsxcore/new_dynarec/linkage_arm.S -+++ b/libpcsxcore/new_dynarec/linkage_arm.S -@@ -438,7 +438,7 @@ FUNCTION(cc_interrupt): - str r1, [fp, #LO_pending_exception] - and r2, r2, r10, lsr #17 - add r3, fp, #LO_restore_candidate -- str r10, [fp, #LO_cycle] /* PCSX cycles */ -+@@@ str r10, [fp, #LO_cycle] /* PCSX cycles */ - @@ str r10, [fp, #LO_reg_cop0+36] /* Count */ - ldr r4, [r2, r3] - mov r10, lr -@@ -528,7 +528,7 @@ FUNCTION(new_dyna_leave): - ldr r0, [fp, #LO_last_count] - add r12, fp, #28 - add r10, r0, r10 -- str r10, [fp, #LO_cycle] -+@@@ str r10, [fp, #LO_cycle] - ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc} - .size new_dyna_leave, .-new_dyna_leave - -@@ -645,7 +645,7 @@ FUNCTION(new_dyna_start): - \readop r0, [r1, r3, lsl #\tab_shift] - .endif - movcc pc, lr -- str r2, [fp, #LO_cycle] -+@@@ str r2, [fp, #LO_cycle] - bx r1 - .endm - -@@ -680,7 +680,7 @@ FUNCTION(jump_handler_read32): - mov r0, r1 - add r2, r2, r12 - push {r2, lr} -- str r2, [fp, #LO_cycle] -+@@@ str r2, [fp, #LO_cycle] - blx r3 - - ldr r0, [fp, #LO_next_interupt] -@@ -708,7 +708,7 @@ FUNCTION(jump_handler_write_h): - add r2, r2, r12 - mov r0, r1 - push {r2, lr} -- str r2, [fp, #LO_cycle] -+@@@ str r2, [fp, #LO_cycle] - blx r3 - - ldr r0, [fp, #LO_next_interupt] -diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S -index 7df82b4..79298e4 100644 ---- a/libpcsxcore/new_dynarec/linkage_arm64.S -+++ b/libpcsxcore/new_dynarec/linkage_arm64.S -@@ -123,7 +123,7 @@ FUNCTION(cc_interrupt): - str wzr, [rFP, #LO_pending_exception] - and w2, w2, rCC, lsr #17 - add x3, rFP, #LO_restore_candidate -- str rCC, [rFP, #LO_cycle] /* PCSX cycles */ -+## str rCC, [rFP, #LO_cycle] /* PCSX cycles */ - # str rCC, [rFP, #LO_reg_cop0+36] /* Count */ - ldr w19, [x3, w2, uxtw] - mov x21, lr -@@ -231,7 +231,7 @@ FUNCTION(new_dyna_start): - FUNCTION(new_dyna_leave): - ldr w0, [rFP, #LO_last_count] - add rCC, rCC, w0 -- str rCC, [rFP, #LO_cycle] -+## str rCC, [rFP, #LO_cycle] - ldp x19, x20, [sp, #16*1] - ldp x21, x22, [sp, #16*2] - ldp x23, x24, [sp, #16*3] -@@ -249,7 +249,7 @@ FUNCTION(new_dyna_leave): - /* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */ - ldr w4, [rFP, #LO_last_count] - add w4, w4, w2 -- str w4, [rFP, #LO_cycle] -+## str w4, [rFP, #LO_cycle] - .endm - - .macro memhandler_post diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c -index 2f77516..21481bc 100644 +index 300a84c8..e4343533 100644 --- a/libpcsxcore/new_dynarec/new_dynarec.c +++ b/libpcsxcore/new_dynarec/new_dynarec.c -@@ -521,6 +521,9 @@ static int doesnt_expire_soon(void *tcaddr) - // This is called from the recompiled JR/JALR instructions - void noinline *get_addr(u_int vaddr) +@@ -345,7 +345,7 @@ static struct compile_info + #define stat_clear(s) + #endif + +- #define HACK_ENABLED(x) ((ndrc_g.hacks | ndrc_g.hacks_pergame) & (x)) ++ #define HACK_ENABLED(x) ((NDHACK_NO_STALLS|NDHACK_NO_COMPAT_HACKS) & (x)) + + /* registers that may be allocated */ + /* 1-31 gpr */ +@@ -626,6 +626,7 @@ static int cycle_multiplier_active; + + static int CLOCK_ADJUST(int x) + { ++ return x * 2; + int m = cycle_multiplier_active; + int s = (x >> 31) | 1; + return (x * m + s * 50) / 100; +@@ -837,6 +838,9 @@ static noinline u_int generate_exception(u_int pc) + static void noinline *get_addr(struct ht_entry *ht, const u_int vaddr, + enum ndrc_compile_mode compile_mode) { +#ifdef DRC_DBG +printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc); +#endif - u_int page=get_page(vaddr); - u_int vpage=get_vpage(vaddr); - struct ll_entry *head; -@@ -4790,13 +4793,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert) - #endif - emit_addimm_and_set_flags(cycles,HOST_CCREG); - jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - } - else - { - emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2)); - jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - } - add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0); - } -@@ -5204,7 +5209,8 @@ static void rjump_assemble(int i,struct regstat *i_regs) - // special case for RFE - emit_jmp(0); - else -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1); - #ifdef USE_MINI_HT - if(dops[i].rs1==31) { -@@ -5309,7 +5315,8 @@ static void cjump_assemble(int i,struct regstat *i_regs) - else if(nop) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - } - else { -@@ -5496,7 +5503,8 @@ static void cjump_assemble(int i,struct regstat *i_regs) - emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - emit_storereg(CCREG,HOST_CCREG); - } -@@ -5505,7 +5513,8 @@ static void cjump_assemble(int i,struct regstat *i_regs) - assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - } - } -@@ -5607,7 +5616,8 @@ static void sjump_assemble(int i,struct regstat *i_regs) - else if(nevertaken) { - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - } - else { -@@ -5763,7 +5773,8 @@ static void sjump_assemble(int i,struct regstat *i_regs) - emit_loadreg(CCREG,HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - emit_storereg(CCREG,HOST_CCREG); - } -@@ -5772,7 +5783,8 @@ static void sjump_assemble(int i,struct regstat *i_regs) - assert(cc==HOST_CCREG); - emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc); - void *jaddr=out; -- emit_jns(0); -+ //emit_jns(0); -+ emit_jmp(0); - add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0); - } - } -@@ -6211,7 +6223,7 @@ void unneeded_registers(int istart,int iend,int r) + u_int start_page = get_page_prev(vaddr); + u_int i, page, end_page = get_page(vaddr); + void *found_clean = NULL; +@@ -7421,7 +7425,7 @@ static noinline void pass2b_unneeded_regs(int istart, int iend, int r) // R0 is always unneeded u|=1; // Save it @@ -189,36 +38,16 @@ index 2f77516..21481bc 100644 gte_unneeded[i]=gte_u; /* printf("ur (%d,%d) %x: ",istart,iend,start+i*4); -@@ -8756,6 +8768,7 @@ int new_recompile_block(u_int addr) - - // This allocates registers (if possible) one instruction prior - // to use, which can avoid a load-use penalty on certain CPUs. -+#if 0 - for(i=0;in.Cause &= ~0x400; ++ u32 c2 = cp0->n.Cause & ~0x400; + if (psxHu32(0x1070) & psxHu32(0x1074)) +- cp0->n.Cause |= 0x400; +- if (((cp0->n.Cause | 1) & cp0->n.SR & 0x401) == 0x401) ++ c2 |= 0x400; ++ if (((c2 | 1) & cp0->n.SR & 0x401) == 0x401) { ++ cp0->n.Cause = c2; + psxException(0, 0, cp0); ++ } + } + + void gen_interupt(psxCP0Regs *cp0) +diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c +index 68d79321..50a38f8d 100644 +--- a/libpcsxcore/psxinterpreter.c ++++ b/libpcsxcore/psxinterpreter.c +@@ -243,7 +243,7 @@ static inline void addCycle(psxRegisters *regs) + { + assert(regs->subCycleStep >= 0x10000); + regs->subCycle += regs->subCycleStep; +- regs->cycle += regs->subCycle >> 16; ++ regs->cycle += 2; //regs->subCycle >> 16; + regs->subCycle &= 0xffff; + } + +@@ -440,7 +440,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) { + regs->CP0.n.Target = pc_final; + regs->branching = 0; + ++ psxRegs.cycle += 2; + psxBranchTest(); ++ psxRegs.cycle -= 2; } + + static void doBranchReg(psxRegisters *regs, u32 tar) { +@@ -973,7 +975,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) { + } + } + +-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); } ++OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); } + + // no exception + static inline void psxNULLne(psxRegisters *regs) { +@@ -1132,6 +1134,7 @@ OP(psxHLE) { + dloadFlush(regs_); + psxHLEt[hleCode](); + regs_->branchSeen = 1; ++ regs_->cycle -= 2; + } + + static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = { +@@ -1182,18 +1185,20 @@ static void intReset() { + static inline void execI_(u8 **memRLUT, psxRegisters *regs) { + u32 pc = regs->pc; + +- addCycle(regs); ++ //addCycle(regs); + dloadStep(regs); + + regs->pc += 4; + regs->code = fetch(regs, memRLUT, pc); + psxBSC[regs->code >> 26](regs, regs->code); ++ psxRegs.cycle += 2; ++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check + } + + static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { + u32 pc = regs->pc; + +- addCycle(regs); ++ //addCycle(regs); + dloadStep(regs); + + if (execBreakCheck(regs, pc)) +@@ -1202,6 +1207,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) { + regs->pc += 4; + regs->code = fetch(regs, memRLUT, pc); + psxBSC[regs->code >> 26](regs, regs->code); ++ psxRegs.cycle += 2; ++ fetchNoCache(regs, memRLUT, regs->pc); // bus err check + } + + static void intExecute(psxRegisters *regs) { +@@ -1218,20 +1225,28 @@ static void intExecuteBp(psxRegisters *regs) { + execIbp(memRLUT, regs); + } + ++ extern int last_count; ++ void do_insn_cmp(void); + static void intExecuteBlock(psxRegisters *regs, enum blockExecCaller caller) { + u8 **memRLUT = psxMemRLUT; + ++ last_count = 0; + regs->branchSeen = 0; +- while (!regs->branchSeen) ++ while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) { ++ do_insn_cmp(); + execI_(memRLUT, regs); ++ } + } + + static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) { + u8 **memRLUT = psxMemRLUT; + ++ last_count = 0; + regs->branchSeen = 0; +- while (!regs->branchSeen) ++ while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) { ++ do_insn_cmp(); + execIbp(memRLUT, regs); ++ } + } + + static void intClear(u32 Addr, u32 Size) { +@@ -1263,7 +1278,7 @@ static void setupCop(u32 sr) + else + psxBSC[17] = psxCOPd; + if (sr & (1u << 30)) +- psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall; ++ psxBSC[18] = psxCOP2; + else + psxBSC[18] = psxCOPd; + if (sr & (1u << 31)) +@@ -1282,7 +1297,7 @@ void intApplyConfig() { + assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall); + assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall); + +- if (Config.DisableStalls) { ++ if (1) { + psxBSC[18] = psxCOP2; + psxBSC[50] = gteLWC2; + psxBSC[58] = gteSWC2; +@@ -1365,8 +1380,12 @@ static void intShutdown() { + // single step (may do several ops in case of a branch or load delay) + // called by asm/dynarec + void execI(psxRegisters *regs) { ++ printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, regs->next_interupt); ++ last_count = 0; + do { + execIbp(psxMemRLUT, regs); ++ if (regs->dloadReg[0] || regs->dloadReg[1]) ++ do_insn_cmp(); + } while (regs->dloadReg[0] || regs->dloadReg[1]); + } +