X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fpatches%2Ftrace_intr;fp=libpcsxcore%2Fnew_dynarec%2Fpatches%2Ftrace_intr;h=57ce9c699719f158597dcfa48b5c561a9b11dd34;hb=a151a8d8331cf743eabeab23ce52e9b7726239e5;hp=0000000000000000000000000000000000000000;hpb=dd114d7d8e8d30bde79eb72d3ae1afc2f06cebb7;p=pcsx_rearmed.git diff --git a/libpcsxcore/new_dynarec/patches/trace_intr b/libpcsxcore/new_dynarec/patches/trace_intr new file mode 100644 index 00000000..57ce9c69 --- /dev/null +++ b/libpcsxcore/new_dynarec/patches/trace_intr @@ -0,0 +1,230 @@ +diff --git a/libpcsxcore/new_dynarec/emu_if.c b/libpcsxcore/new_dynarec/emu_if.c +index 2c82f58..8572981 100644 +--- a/libpcsxcore/new_dynarec/emu_if.c ++++ b/libpcsxcore/new_dynarec/emu_if.c +@@ -417,13 +417,17 @@ static void ari64_shutdown() + { + new_dynarec_cleanup(); + new_dyna_pcsx_mem_shutdown(); ++ (void)ari64_execute; + } + ++extern void intExecuteT(); ++extern void intExecuteBlockT(); ++ + R3000Acpu psxRec = { + ari64_init, + ari64_reset, +- ari64_execute, +- ari64_execute_until, ++ intExecuteT, ++ intExecuteBlockT, + ari64_clear, + #ifdef ICACHE_EMULATION + ari64_notify, +@@ -489,7 +493,7 @@ static u32 memcheck_read(u32 a) + return *(u32 *)(psxM + (a & 0x1ffffc)); + } + +-#if 0 ++#if 1 + void do_insn_trace(void) + { + static psxRegisters oldregs; +diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c +index dbcb989..0716f5e 100644 +--- a/libpcsxcore/psxhw.c ++++ b/libpcsxcore/psxhw.c +@@ -373,13 +373,14 @@ void psxHwWrite8(u32 add, u8 value) { + case 0x1f801803: cdrWrite3(value); break; + + default: ++ if (add < 0x1f802000) + psxHu8(add) = value; + #ifdef PSXHW_LOG + PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value); + #endif + return; + } +- psxHu8(add) = value; ++ //psxHu8(add) = value; + #ifdef PSXHW_LOG + PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value); + #endif +@@ -504,6 +505,7 @@ void psxHwWrite16(u32 add, u16 value) { + return; + } + ++ if (add < 0x1f802000) + psxHu16ref(add) = SWAPu16(value); + #ifdef PSXHW_LOG + PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value); +@@ -699,9 +701,9 @@ void psxHwWrite32(u32 add, u32 value) { + return; + + case 0x1f801820: +- mdecWrite0(value); break; ++ mdecWrite0(value); return; + case 0x1f801824: +- mdecWrite1(value); break; ++ mdecWrite1(value); return; + + case 0x1f801100: + #ifdef PSXHW_LOG +@@ -759,6 +761,7 @@ void psxHwWrite32(u32 add, u32 value) { + return; + } + ++ if (add < 0x1f802000) + psxHu32ref(add) = SWAPu32(value); + #ifdef PSXHW_LOG + PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value); +diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c +index 02e00a9..a007dc5 100644 +--- a/libpcsxcore/psxinterpreter.c ++++ b/libpcsxcore/psxinterpreter.c +@@ -512,8 +512,9 @@ static void doBranch(u32 tar) { + debugI(); + + psxRegs.pc += 4; +- psxRegs.cycle += BIAS; + ++ (void)tmp; ++#if 0 + // check for load delay + tmp = psxRegs.code >> 26; + switch (tmp) { +@@ -547,13 +548,15 @@ static void doBranch(u32 tar) { + } + break; + } +- ++#endif + psxBSC[psxRegs.code >> 26](); + + branch = 0; + psxRegs.pc = branchPC; + + psxBranchTest(); ++ ++ psxRegs.cycle += BIAS; + } + + /********************************************************* +@@ -636,12 +639,13 @@ void psxMULTU() { + psxRegs.GPR.n.hi = (u32)((res >> 32) & 0xffffffff); + } + ++#define doBranchNotTaken() do { psxRegs.cycle -= BIAS; execI(); psxBranchTest(); psxRegs.cycle += BIAS; } while(0) + /********************************************************* + * Register branch logic * + * Format: OP rs, offset * + *********************************************************/ +-#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); +-#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } } ++#define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_); else doBranchNotTaken(); ++#define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } else doBranchNotTaken(); } + + void psxBGEZ() { RepZBranchi32(>=) } // Branch if Rs >= 0 + void psxBGEZAL() { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link +@@ -711,7 +715,7 @@ void psxRFE() { + * Register branch logic * + * Format: OP rs, rt, offset * + *********************************************************/ +-#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); ++#define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_); else doBranchNotTaken(); + + void psxBEQ() { RepBranchi32(==) } // Branch if Rs == Rt + void psxBNE() { RepBranchi32(!=) } // Branch if Rs != Rt +@@ -895,6 +899,9 @@ void MTC0(int reg, u32 val) { + case 12: // Status + psxRegs.CP0.r[12] = val; + psxTestSWInts(); ++#ifndef __arm__ ++ psxBranchTest(); ++#endif + break; + + case 13: // Cause +@@ -1057,6 +1064,23 @@ void intExecuteBlock() { + while (!branch2) execI(); + } + ++extern void do_insn_trace(void); ++ ++void intExecuteT() { ++ for (;;) { ++ do_insn_trace(); ++ execI(); ++ } ++} ++ ++void intExecuteBlockT() { ++ branch2 = 0; ++ while (!branch2) { ++ do_insn_trace(); ++ execI(); ++ } ++} ++ + static void intClear(u32 Addr, u32 Size) { + } + +diff --git a/libpcsxcore/psxmem.c b/libpcsxcore/psxmem.c +index c09965d..135a5d0 100644 +--- a/libpcsxcore/psxmem.c ++++ b/libpcsxcore/psxmem.c +@@ -219,11 +219,13 @@ void psxMemShutdown() { + } + + static int writeok = 1; ++u32 last_io_addr; + + u8 psxMemRead8(u32 mem) { + char *p; + u32 t; + ++ last_io_addr = mem; + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { + if ((mem & 0xffff) < 0x400) +@@ -249,6 +251,7 @@ u16 psxMemRead16(u32 mem) { + char *p; + u32 t; + ++ last_io_addr = mem; + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { + if ((mem & 0xffff) < 0x400) +@@ -274,6 +277,7 @@ u32 psxMemRead32(u32 mem) { + char *p; + u32 t; + ++ last_io_addr = mem; + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { + if ((mem & 0xffff) < 0x400) +@@ -299,6 +303,7 @@ void psxMemWrite8(u32 mem, u8 value) { + char *p; + u32 t; + ++ last_io_addr = mem; + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { + if ((mem & 0xffff) < 0x400) +@@ -326,6 +331,7 @@ void psxMemWrite16(u32 mem, u16 value) { + char *p; + u32 t; + ++ last_io_addr = mem; + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) { + if ((mem & 0xffff) < 0x400) +@@ -353,6 +359,7 @@ void psxMemWrite32(u32 mem, u32 value) { + char *p; + u32 t; + ++ last_io_addr = mem; + // if ((mem&0x1fffff) == 0x71E18 || value == 0x48088800) SysPrintf("t2fix!!\n"); + t = mem >> 16; + if (t == 0x1f80 || t == 0x9f80 || t == 0xbf80) {