X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fnew_dynarec%2Fpcsxmem.c;h=f4b1d90e8e660e978141c649e1e74b8aa304af31;hb=979b861b31ef1f5033db5bd4433b842944300a3e;hp=190f8fc7b1dfa239f2bbe751fa716324411c8d55;hpb=bc7c5acb6eb1ac9adc6b4381a2c2b2baffd5aebe;p=pcsx_rearmed.git diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c index 190f8fc7..f4b1d90e 100644 --- a/libpcsxcore/new_dynarec/pcsxmem.c +++ b/libpcsxcore/new_dynarec/pcsxmem.c @@ -101,7 +101,11 @@ static void io_write_sio32(u32 value) static void map_rcnt_rcount0(u32 mode) { - if (mode & 0x100) { // pixel clock + if (mode & 0x001) { // sync mode + map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); + map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); + } + else if (mode & 0x100) { // pixel clock map_item(&mem_iortab[IOMEM32(0x1100)], rcnt0_read_count_m1, 1); map_item(&mem_iortab[IOMEM16(0x1100)], rcnt0_read_count_m1, 1); } @@ -113,7 +117,11 @@ static void map_rcnt_rcount0(u32 mode) static void map_rcnt_rcount1(u32 mode) { - if (mode & 0x100) { // hcnt + if (mode & 0x001) { // sync mode + map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); + map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); + } + else if (mode & 0x100) { // hcnt map_item(&mem_iortab[IOMEM32(0x1110)], rcnt1_read_count_m1, 1); map_item(&mem_iortab[IOMEM16(0x1110)], rcnt1_read_count_m1, 1); } @@ -125,7 +133,7 @@ static void map_rcnt_rcount1(u32 mode) static void map_rcnt_rcount2(u32 mode) { - if (mode & 0x01) { // gate + if ((mode & 7) == 1 || (mode & 7) == 7) { // sync mode map_item(&mem_iortab[IOMEM32(0x1120)], &psxH[0x1000], 0); map_item(&mem_iortab[IOMEM16(0x1120)], &psxH[0x1000], 0); } @@ -146,7 +154,6 @@ static void map_rcnt_rcount2(u32 mode) #endif #define make_rcnt_funcs(i) \ -static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \ static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \ static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \ static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \ @@ -157,43 +164,6 @@ make_rcnt_funcs(0) make_rcnt_funcs(1) make_rcnt_funcs(2) -static void io_write_ireg16(u32 value) -{ - psxHu16ref(0x1070) &= value; -} - -static void io_write_imask16(u32 value) -{ - psxHu16ref(0x1074) = value; - if (psxHu16ref(0x1070) & value) - new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); -} - -static void io_write_ireg32(u32 value) -{ - psxHu32ref(0x1070) &= value; -} - -static void io_write_imask32(u32 value) -{ - psxHu32ref(0x1074) = value; - if (psxHu32ref(0x1070) & value) - new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1); -} - -static void io_write_dma_icr32(u32 value) -{ - u32 tmp = value & 0x00ff803f; - tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000; - if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000) - || tmp & HW_DMA_ICR_BUS_ERROR) { - if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT)) - psxHu32ref(0x1070) |= SWAP32(8); - tmp |= HW_DMA_ICR_IRQ_SENT; - } - HW_DMA_ICR = SWAPu32(tmp); -} - #define make_dma_func(n) \ static void io_write_chcr##n(u32 value) \ { \ @@ -210,6 +180,29 @@ make_dma_func(3) make_dma_func(4) make_dma_func(6) +static u32 io_spu_read8_even(u32 addr) +{ + return SPU_readRegister(addr, psxRegs.cycle) & 0xff; +} + +static u32 io_spu_read8_odd(u32 addr) +{ + return SPU_readRegister(addr, psxRegs.cycle) >> 8; +} + +static u32 io_spu_read16(u32 addr) +{ + return SPU_readRegister(addr, psxRegs.cycle); +} + +static u32 io_spu_read32(u32 addr) +{ + u32 ret; + ret = SPU_readRegister(addr, psxRegs.cycle); + ret |= SPU_readRegister(addr + 2, psxRegs.cycle) << 16; + return ret; +} + static void io_spu_write16(u32 value) { // meh @@ -225,27 +218,6 @@ static void io_spu_write32(u32 value) wfunc(a + 2, value >> 16, psxRegs.cycle); } -static u32 io_gpu_read_status(void) -{ - u32 v; - - // meh2, syncing for img bit, might want to avoid it.. - gpuSyncPluginSR(); - v = HW_GPU_STATUS; - - // XXX: because of large timeslices can't use hSyncCount, using rough - // approximization instead. Perhaps better use hcounter code here or something. - if (hSyncCount < 240 && (HW_GPU_STATUS & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS) - v |= PSXGPU_LCF & (psxRegs.cycle << 20); - return v; -} - -static void io_gpu_write_status(u32 value) -{ - GPU_writeStatus(value); - gpuSyncPluginSR(); -} - void new_dyna_pcsx_mem_isolate(int enable) { int i; @@ -274,9 +246,6 @@ static u32 read_biu(u32 addr) if (addr != 0xfffe0130) return read_mem_dummy(addr); - FILE *f = fopen("/tmp/psxbiu.bin", "wb"); - fwrite(psxM, 1, 0x200000, f); - fclose(f); memprintf("read_biu %08x @%08x %u\n", psxRegs.biuReg, psxRegs.pc, psxRegs.cycle); return psxRegs.biuReg; @@ -385,17 +354,17 @@ void new_dyna_pcsx_mem_init(void) } map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1); - map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1); + map_item(&mem_iortab[IOMEM32(0x1100)], psxRcntRcount0, 1); map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1); map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1); - map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1); + map_item(&mem_iortab[IOMEM32(0x1110)], psxRcntRcount1, 1); map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1); map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1); - map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1); + map_item(&mem_iortab[IOMEM32(0x1120)], psxRcntRcount2, 1); map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1); map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1); // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); - map_item(&mem_iortab[IOMEM32(0x1814)], io_gpu_read_status, 1); + map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1); map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1); map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1); @@ -404,13 +373,13 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1); map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1); map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1); - map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1); + map_item(&mem_iortab[IOMEM16(0x1100)], psxRcntRcount0, 1); map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1); map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1); - map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1); + map_item(&mem_iortab[IOMEM16(0x1110)], psxRcntRcount1, 1); map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1); map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1); - map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1); + map_item(&mem_iortab[IOMEM16(0x1120)], psxRcntRcount2, 1); map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1); map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1); @@ -420,17 +389,24 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1); map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1); + for (i = 0x1c00; i < 0x2000; i += 2) { + map_item(&mem_iortab[IOMEM8(i)], io_spu_read8_even, 1); + map_item(&mem_iortab[IOMEM8(i+1)], io_spu_read8_odd, 1); + map_item(&mem_iortab[IOMEM16(i)], io_spu_read16, 1); + map_item(&mem_iortab[IOMEM32(i)], io_spu_read32, 1); + } + // write(u32 data) map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1); - map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1); - map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1); + map_item(&mem_iowtab[IOMEM32(0x1070)], psxHwWriteIstat, 1); + map_item(&mem_iowtab[IOMEM32(0x1074)], psxHwWriteImask, 1); map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1); map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1); map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1); map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1); map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1); map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1); - map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1); + map_item(&mem_iowtab[IOMEM32(0x10f4)], psxHwWriteDmaIcr32, 1); map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1); map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1); map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1); @@ -441,7 +417,7 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1); map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1); // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); - map_item(&mem_iowtab[IOMEM32(0x1814)], io_gpu_write_status, 1); + map_item(&mem_iowtab[IOMEM32(0x1814)], psxHwWriteGpuSR, 1); map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1); map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1); @@ -450,8 +426,8 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1); map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1); map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1); - map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1); - map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1); + map_item(&mem_iowtab[IOMEM16(0x1070)], psxHwWriteIstat, 1); + map_item(&mem_iowtab[IOMEM16(0x1074)], psxHwWriteImask, 1); map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1); map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1); map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1); @@ -468,7 +444,7 @@ void new_dyna_pcsx_mem_init(void) map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1); map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1); - for (i = 0x1c00; i < 0x1e00; i += 2) { + for (i = 0x1c00; i < 0x2000; i += 2) { map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1); map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1); } @@ -489,15 +465,13 @@ void new_dyna_pcsx_mem_init(void) void new_dyna_pcsx_mem_reset(void) { - int i; - // plugins might change so update the pointers map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1); - - for (i = 0x1c00; i < 0x1e00; i += 2) - map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1); - map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1); + if (Config.hacks.gpu_busy_hack) + map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSRbusyHack, 1); + else + map_item(&mem_iortab[IOMEM32(0x1814)], psxHwReadGpuSR, 1); } void new_dyna_pcsx_mem_shutdown(void)