X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fpsxhw.c;h=f5efa22bd7c704295f006b0846295a789e11bfc6;hb=2f59faba23ff29fd7679d217947d1574d271b5a6;hp=fb365c07d1fa9758bf6dc0c70a3dc223651598b4;hpb=11d23573173ec4b5074eb35665c6012a46034d5c;p=pcsx_rearmed.git

diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index fb365c07..f5efa22b 100644
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -22,6 +22,7 @@
 */
 
 #include "psxhw.h"
+#include "psxevents.h"
 #include "mdec.h"
 #include "cdrom.h"
 #include "gpu.h"
@@ -32,13 +33,17 @@
 #define PAD_LOG(...)
 #endif
 
+static u32 (*psxHwReadGpuSRptr)(void) = psxHwReadGpuSR;
+
 void psxHwReset() {
 	memset(psxH, 0, 0x10000);
 
 	mdecInit(); // initialize mdec decoder
 	cdrReset();
 	psxRcntInit();
-	HW_GPU_STATUS = SWAP32(0x14802000);
+	HW_GPU_STATUS = SWAP32(0x10802000);
+	psxHwReadGpuSRptr = Config.hacks.gpu_busy
+		? psxHwReadGpuSRbusyHack : psxHwReadGpuSR;
 }
 
 void psxHwWriteIstat(u32 value)
@@ -58,7 +63,7 @@ void psxHwWriteImask(u32 value)
 	if (stat & value) {
 		//if ((psxRegs.CP0.n.SR & 0x401) == 0x401)
 		//	log_unhandled("irq on unmask @%08x\n", psxRegs.pc);
-		new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
+		set_event(PSXINT_NEWDRC_CHECK, 1);
 	}
 	psxRegs.CP0.n.Cause &= ~0x400;
 	if (stat & value)
@@ -78,6 +83,45 @@ void psxHwWriteDmaIcr32(u32 value)
 	HW_DMA_ICR = SWAPu32(tmp);
 }
 
+void psxHwWriteGpuSR(u32 value)
+{
+	u32 old_sr = HW_GPU_STATUS, new_sr;
+	GPU_writeStatus(value);
+	gpuSyncPluginSR();
+	new_sr = HW_GPU_STATUS;
+	// "The Next Tetris" seems to rely on the field order after enable
+	if ((old_sr ^ new_sr) & new_sr & SWAP32(PSXGPU_ILACE))
+		frame_counter |= 1;
+}
+
+u32 psxHwReadGpuSR(void)
+{
+	u32 v, c = psxRegs.cycle;
+
+	// meh2, syncing for img bit, might want to avoid it..
+	gpuSyncPluginSR();
+	v = SWAP32(HW_GPU_STATUS);
+	v |= ((s32)(psxRegs.gpuIdleAfter - c) >> 31) & PSXGPU_nBUSY;
+
+	// XXX: because of large timeslices can't use hSyncCount, using rough
+	// approximization instead. Perhaps better use hcounter code here or something.
+	if (hSyncCount < 240 && (v & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
+		v |= PSXGPU_LCF & (c << 20);
+	return v;
+}
+
+// a hack due to poor timing of gpu idle bit
+// to get rid of this, GPU draw times, DMAs, cpu timing has to fall within
+// certain timing window or else games like "ToHeart" softlock
+u32 psxHwReadGpuSRbusyHack(void)
+{
+	u32 v = psxHwReadGpuSR();
+	static u32 hack;
+	if (!(hack++ & 3))
+		v &= ~PSXGPU_nBUSY;
+	return v;
+}
+
 u8 psxHwRead8(u32 add) {
 	unsigned char hard;
 
@@ -120,8 +164,11 @@ u8 psxHwRead8(u32 add) {
 			log_unhandled("unhandled r8  %08x @%08x\n", add, psxRegs.pc);
 			// falthrough
 		default:
-			if (0x1f801c00 <= add && add < 0x1f802000)
-				log_unhandled("spu r8 %02x @%08x\n", add, psxRegs.pc);
+			if (0x1f801c00 <= add && add < 0x1f802000) {
+				u16 val = SPU_readRegister(add & ~1, psxRegs.cycle);
+				hard = (add & 1) ? val >> 8 : val;
+				break;
+			}
 			hard = psxHu8(add); 
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
@@ -253,7 +300,7 @@ u16 psxHwRead16(u32 add) {
 			// falthrough
 		default:
 			if (0x1f801c00 <= add && add < 0x1f802000)
-				return SPU_readRegister(add);
+				return SPU_readRegister(add, psxRegs.cycle);
 			hard = psxHu16(add);
 #ifdef PSXHW_LOG
 			PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
@@ -299,10 +346,7 @@ u32 psxHwRead32(u32 add) {
 #endif
 			return hard;
 		case 0x1f801814:
-			gpuSyncPluginSR();
-			hard = SWAP32(HW_GPU_STATUS);
-			if (hSyncCount < 240 && (hard & PSXGPU_ILACE_BITS) != PSXGPU_ILACE_BITS)
-				hard |= PSXGPU_LCF & (psxRegs.cycle << 20);
+			hard = psxHwReadGpuSRptr();
 #ifdef PSXHW_LOG
 			PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
 #endif
@@ -411,8 +455,8 @@ u32 psxHwRead32(u32 add) {
 			// falthrough
 		default:
 			if (0x1f801c00 <= add && add < 0x1f802000) {
-				hard = SPU_readRegister(add);
-				hard |= SPU_readRegister(add + 2) << 16;
+				hard = SPU_readRegister(add, psxRegs.cycle);
+				hard |= SPU_readRegister(add + 2, psxRegs.cycle) << 16;
 				return hard;
 			}
 			hard = psxHu32(add);
@@ -429,33 +473,15 @@ u32 psxHwRead32(u32 add) {
 
 void psxHwWrite8(u32 add, u8 value) {
 	switch (add & 0x1fffffff) {
-		case 0x1f801040: sioWrite8(value); break;
+		case 0x1f801040: sioWrite8(value); break;
+		case 0x1f8010f6:
+			// nocash documents it as forced w32, but still games use this?
+			break;
 		case 0x1f801800: cdrWrite0(value); break;
 		case 0x1f801801: cdrWrite1(value); break;
 		case 0x1f801802: cdrWrite2(value); break;
 		case 0x1f801803: cdrWrite3(value); break;
 
-		case 0x1f801041: case 0x1f801042: case 0x1f801043:
-		case 0x1f801044: case 0x1f801045:
-		case 0x1f801046: case 0x1f801047:
-		case 0x1f801048: case 0x1f801049:
-		case 0x1f80104a: case 0x1f80104b:
-		case 0x1f80104c: case 0x1f80104d:
-		case 0x1f80104e: case 0x1f80104f:
-		case 0x1f801050: case 0x1f801051:
-		case 0x1f801054: case 0x1f801055:
-		case 0x1f801058: case 0x1f801059:
-		case 0x1f80105a: case 0x1f80105b:
-		case 0x1f80105c: case 0x1f80105d:
-		case 0x1f801100: case 0x1f801101:
-		case 0x1f801104: case 0x1f801105:
-		case 0x1f801108: case 0x1f801109:
-		case 0x1f801110: case 0x1f801111:
-		case 0x1f801114: case 0x1f801115:
-		case 0x1f801118: case 0x1f801119:
-		case 0x1f801120: case 0x1f801121:
-		case 0x1f801124: case 0x1f801125:
-		case 0x1f801128: case 0x1f801129:
 		case 0x1f801810: case 0x1f801811:
 		case 0x1f801812: case 0x1f801813:
 		case 0x1f801814: case 0x1f801815:
@@ -473,6 +499,8 @@ void psxHwWrite8(u32 add, u8 value) {
 					SPU_writeRegister(add, value, psxRegs.cycle);
 				return;
 			}
+			else if (0x1f801000 <= add && add < 0x1f801800)
+				log_unhandled("unhandled w8  %08x @%08x\n", add, psxRegs.pc);
 
 			psxHu8(add) = value;
 #ifdef PSXHW_LOG
@@ -768,8 +796,7 @@ void psxHwWrite32(u32 add, u32 value) {
 #ifdef PSXHW_LOG
 			PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
 #endif
-			GPU_writeStatus(value);
-			gpuSyncPluginSR();
+			psxHwWriteGpuSR(value);
 			return;
 
 		case 0x1f801820: