X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=libpcsxcore%2Fpsxinterpreter.c;h=76a6a3d46e7c150c80a0c74197681f51abc1aa93;hb=424e6d52a21bc1b609a964c109d3241232d52eb7;hp=3d0836459ba9207edbac98af1441061d1fe03236;hpb=ee8fd5674f74f307878f2dabef7641a837fb2a99;p=pcsx_rearmed.git

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 3d083645..76a6a3d4 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -391,6 +391,7 @@ static void psxDelayTest(int reg, u32 bpc) {
 		case 3:
 			delayWrite(reg, bpc); return;
 	}
+	// DS
 	psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code);
 
 	branch = 0;
@@ -537,7 +538,7 @@ static void doBranch(u32 tar) {
 	addCycle();
 
 	// check for load delay
-	tmp = psxRegs.code >> 26;
+	tmp = code >> 26;
 	switch (tmp) {
 		case 0x10: // COP0
 			switch (_Rs_) {
@@ -570,7 +571,7 @@ static void doBranch(u32 tar) {
 			break;
 	}
 
-	psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code);
+	psxBSC[code >> 26](&psxRegs, code);
 
 	branch = 0;
 	psxRegs.pc = branchPC;
@@ -686,8 +687,15 @@ OP(psxMULTU_stall) {
 * Register branch logic                                  *
 * Format:  OP rs, offset                                 *
 *********************************************************/
-#define RepZBranchi32(op)      if(_i32(_rRs_) op 0) doBranch(_BranchTarget_);
-#define RepZBranchLinki32(op)  { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } }
+#define RepZBranchi32(op) \
+	if(_i32(_rRs_) op 0) \
+		doBranch(_BranchTarget_);
+#define RepZBranchLinki32(op)  { \
+	s32 temp = _i32(_rRs_); \
+	_SetLink(31); \
+	if(temp op 0) \
+		doBranch(_BranchTarget_); \
+}
 
 OP(psxBGEZ)   { RepZBranchi32(>=) }      // Branch if Rs >= 0
 OP(psxBGEZAL) { RepZBranchLinki32(>=) }  // Branch if Rs >= 0 and link
@@ -750,19 +758,19 @@ OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs
 *********************************************************/
 OP(psxBREAK) {
 	regs_->pc -= 4;
-	psxException(0x24, branch);
+	psxException(0x24, branch, &regs_->CP0);
 }
 
 OP(psxSYSCALL) {
 	regs_->pc -= 4;
-	psxException(0x20, branch);
+	psxException(0x20, branch, &regs_->CP0);
 }
 
 static inline void psxTestSWInts(psxRegisters *regs_) {
 	if (regs_->CP0.n.Cause & regs_->CP0.n.Status & 0x0300 &&
 	   regs_->CP0.n.Status & 0x1) {
 		regs_->CP0.n.Cause &= ~0x7c;
-		psxException(regs_->CP0.n.Cause, branch);
+		psxException(regs_->CP0.n.Cause, branch, &regs_->CP0);
 	}
 }
 
@@ -911,7 +919,9 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 //	SysPrintf("MTC0 %d: %x\n", reg, val);
 	switch (reg) {
 		case 12: // Status
-			regs_->CP0.r[12] = val;
+			if ((regs_->CP0.n.Status ^ val) & (1 << 16))
+				psxMemOnIsolate((val >> 16) & 1);
+			regs_->CP0.n.Status = val;
 			psxTestSWInts(regs_);
 			break;
 
@@ -1018,12 +1028,15 @@ static void psxBASIC(struct psxCP2Regs *cp2regs) {
 }
 
 OP(psxREGIMM) {
-	switch (_Rt_) {
-		case 0x00: psxBLTZ(regs_, code);   break;
-		case 0x01: psxBGEZ(regs_, code);   break;
+	u32 rt = _Rt_;
+	switch (rt) {
 		case 0x10: psxBLTZAL(regs_, code); break;
 		case 0x11: psxBGEZAL(regs_, code); break;
-		default:   psxNULL_();             break;
+		default:
+			if (rt & 1)
+				psxBGEZ(regs_, code);
+			else
+				psxBLTZ(regs_, code);
 	}
 }
 
@@ -1076,7 +1089,6 @@ static int intInit() {
 }
 
 static void intReset() {
-	memset(&ICache, 0xff, sizeof(ICache));
 }
 
 static inline void execI_(u8 **memRLUT, psxRegisters *regs_) {
@@ -1101,7 +1113,7 @@ static void intExecute() {
 		execI_(memRLUT, regs_);
 }
 
-void intExecuteBlock() {
+void intExecuteBlock(enum blockExecCaller caller) {
 	psxRegisters *regs_ = &psxRegs;
 	u8 **memRLUT = psxMemRLUT;
 
@@ -1113,11 +1125,15 @@ void intExecuteBlock() {
 static void intClear(u32 Addr, u32 Size) {
 }
 
-void intNotify (int note, void *data) {
-	/* Gameblabla - Only clear the icache if it's isolated */
-	if (note == R3000ACPU_NOTIFY_CACHE_ISOLATED)
-	{
+static void intNotify(enum R3000Anote note, void *data) {
+	switch (note) {
+	case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core?
+	case R3000ACPU_NOTIFY_AFTER_LOAD:
 		memset(&ICache, 0xff, sizeof(ICache));
+		break;
+	case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
+	case R3000ACPU_NOTIFY_BEFORE_SAVE:
+		break;
 	}
 }