X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2F32x.c;h=0a72ddb75d4e933b7a295345bafa3815a3429c7b;hb=4a1fb1832381958386c1dc91a8a5422af386441d;hp=54f8f9b7be9abb14bc071b201f38e114b8698ce4;hpb=4d5dfee86139e1596228db111ce2f30c22c93ddd;p=picodrive.git

diff --git a/pico/32x/32x.c b/pico/32x/32x.c
index 54f8f9b..0a72ddb 100644
--- a/pico/32x/32x.c
+++ b/pico/32x/32x.c
@@ -29,6 +29,7 @@ static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
   }
 }
 
+// MUST specify active_sh2 when called from sh2 memhandlers
 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
 {
   int irqs, mlvl = 0, slvl = 0;
@@ -49,13 +50,19 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
     slvl++;
   slvl *= 2;
 
-  mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 != NULL);
-  if (mrun)
+  mrun = sh2_irl_irq(&msh2, mlvl, active_sh2 == &msh2);
+  if (mrun) {
     p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
+    if (active_sh2 == &msh2)
+      sh2_end_run(active_sh2, 1);
+  }
 
-  srun = sh2_irl_irq(&ssh2, slvl, active_sh2 != NULL);
-  if (srun)
+  srun = sh2_irl_irq(&ssh2, slvl, active_sh2 == &ssh2);
+  if (srun) {
     p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
+    if (active_sh2 == &ssh2)
+      sh2_end_run(active_sh2, 1);
+  }
 
   elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
 }
@@ -66,9 +73,9 @@ void Pico32xStartup(void)
 
   // TODO: OOM handling
   PicoAHW |= PAHW_32X;
-  sh2_init(&msh2, 0);
+  sh2_init(&msh2, 0, &ssh2);
   msh2.irq_callback = sh2_irq_cb;
-  sh2_init(&ssh2, 1);
+  sh2_init(&ssh2, 1, &msh2);
   ssh2.irq_callback = sh2_irq_cb;
 
   PicoMemSetup32x();
@@ -78,9 +85,6 @@ void Pico32xStartup(void)
   if (!Pico.m.pal)
     Pico32x.vdp_regs[0] |= P32XV_nPAL;
 
-  PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
-  PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
-
   rendstatus_old = -1;
 
   emu_32x_startup();
@@ -93,6 +97,8 @@ void p32x_reset_sh2s(void)
 
   sh2_reset(&msh2);
   sh2_reset(&ssh2);
+  sh2_peripheral_reset(&msh2);
+  sh2_peripheral_reset(&ssh2);
 
   // if we don't have BIOS set, perform it's work here.
   // MSH2
@@ -149,7 +155,7 @@ void PicoPower32x(void)
   memset(&Pico32x, 0, sizeof(Pico32x));
 
   Pico32x.regs[0] = P32XS_REN|P32XS_nRES; // verified
-  Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_HBLK|P32XV_PEN;
+  Pico32x.vdp_regs[0x0a/2] = P32XV_VBLK|P32XV_PEN;
   Pico32x.sh2_regs[0] = P32XS2_ADEN;
 }
 
@@ -268,8 +274,7 @@ void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after)
   p32x_event_schedule(now, event, after);
 
   left_to_next = (event_time_next - now) * 3;
-  if (sh2_cycles_left(sh2) > left_to_next)
-    sh2_end_run(sh2, left_to_next);
+  sh2_end_run(sh2, left_to_next);
 }
 
 static void run_events(unsigned int until)
@@ -317,8 +322,8 @@ static inline void run_sh2(SH2 *sh2, int m68k_cycles)
   pevt_log_sh2_o(sh2, EVT_RUN_START);
   sh2->state |= SH2_STATE_RUN;
   cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
-  elprintf(EL_32X, "%csh2 +run %u %d",
-    sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles);
+  elprintf(EL_32X, "%csh2 +run %u %d @%08x",
+    sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles, sh2->pc);
 
   done = sh2_execute(sh2, cycles);
 
@@ -333,7 +338,7 @@ static inline void run_sh2(SH2 *sh2, int m68k_cycles)
 // note: recursive call
 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
 {
-  SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
+  SH2 *osh2 = sh2->other_sh2;
   int left_to_event;
   int m68k_cycles;