X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2F32x.c;h=ab522e41a6d6840d16175e61ff5ad9d1dbd1475a;hb=a76fad41291b7be0b42554353d6775dcdff065e0;hp=f29f327543816b245aee3c21f3af6401e938ea8d;hpb=61801d5bc85c82afc5548fc25fc890bb56f4e763;p=picodrive.git

diff --git a/pico/32x/32x.c b/pico/32x/32x.c
index f29f327..ab522e4 100644
--- a/pico/32x/32x.c
+++ b/pico/32x/32x.c
@@ -17,12 +17,12 @@ SH2 sh2s[2];
 static int REGPARM(2) sh2_irq_cb(SH2 *sh2, int level)
 {
   if (sh2->pending_irl > sh2->pending_int_irq) {
-    elprintf(EL_32X, "%csh2 ack/irl %d @ %08x",
-      sh2->is_slave ? 's' : 'm', level, sh2->pc);
+    elprintf_sh2(sh2, EL_32X, "ack/irl %d @ %08x",
+      level, sh2_pc(sh2));
     return 64 + sh2->pending_irl / 2;
   } else {
-    elprintf(EL_32X, "%csh2 ack/int %d/%d @ %08x",
-      sh2->is_slave ? 's' : 'm', level, sh2->pending_int_vector, sh2->pc);
+    elprintf_sh2(sh2, EL_32X, "ack/int %d/%d @ %08x",
+      level, sh2->pending_int_vector, sh2_pc(sh2));
     sh2->pending_int_irq = 0; // auto-clear
     sh2->pending_level = sh2->pending_irl;
     return sh2->pending_int_vector;
@@ -39,13 +39,13 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
     m68k_cycles = sh2_cycles_done_m68k(active_sh2);
 
   // msh2
-  irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
+  irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[0];
   while ((irqs >>= 1))
     mlvl++;
   mlvl *= 2;
 
   // ssh2
-  irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[1]) & ((Pico32x.sh2irq_mask[1] << 3) | P32XI_VRES);
+  irqs = Pico32x.sh2irqs | Pico32x.sh2irqi[1];
   while ((irqs >>= 1))
     slvl++;
   slvl *= 2;
@@ -67,6 +67,33 @@ void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
   elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
 }
 
+// the mask register is inconsistent, CMD is supposed to be a mask,
+// while others are actually irq trigger enables?
+// TODO: test on hw..
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask)
+{
+  Pico32x.sh2irqs |= mask & P32XI_VRES;
+  Pico32x.sh2irqi[0] |= mask & (Pico32x.sh2irq_mask[0] << 3);
+  Pico32x.sh2irqi[1] |= mask & (Pico32x.sh2irq_mask[1] << 3);
+
+  p32x_update_irls(sh2, m68k_cycles);
+}
+
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles)
+{
+  if ((Pico32x.sh2irq_mask[0] & 2) && (Pico32x.regs[2 / 2] & 1))
+    Pico32x.sh2irqi[0] |= P32XI_CMD;
+  else
+    Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+
+  if ((Pico32x.sh2irq_mask[1] & 2) && (Pico32x.regs[2 / 2] & 2))
+    Pico32x.sh2irqi[1] |= P32XI_CMD;
+  else
+    Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+
+  p32x_update_irls(sh2, m68k_cycles);
+}
+
 void Pico32xStartup(void)
 {
   elprintf(EL_STATUS|EL_32X, "32X startup");
@@ -174,8 +201,7 @@ void PicoReset32x(void)
 {
   if (PicoAHW & PAHW_32X) {
     msh2.m68krcycles_done = ssh2.m68krcycles_done = SekCyclesDoneT();
-    Pico32x.sh2irqs |= P32XI_VRES;
-    p32x_update_irls(NULL, SekCyclesDoneT2());
+    p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VRES);
     p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
     p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
     p32x_pwm_ctl_changed();
@@ -222,12 +248,30 @@ static void p32x_start_blank(void)
     Pico32xSwapDRAM(Pico32x.pending_fb ^ 1);
   }
 
-  Pico32x.sh2irqs |= P32XI_VINT;
-  p32x_update_irls(NULL, SekCyclesDoneT2());
+  p32x_trigger_irq(NULL, SekCyclesDoneT2(), P32XI_VINT);
   p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
   p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
 }
 
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles)
+{
+  // rather rough, 32x hint is useless in practice
+  int after;
+
+  if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 4))
+    return; // nobody cares
+  // note: when Pico.m.scanline is 224, SH2s might
+  // still be at scanline 93 (or so)
+  if (!(Pico32x.sh2_regs[0] & 0x80) && Pico.m.scanline > 224)
+    return;
+
+  after = (Pico32x.sh2_regs[4 / 2] + 1) * 488;
+  if (sh2 != NULL)
+    p32x_event_schedule_sh2(sh2, P32X_EVENT_HINT, after);
+  else
+    p32x_event_schedule(m68k_cycles, P32X_EVENT_HINT, after);
+}
+
 // compare cycles, handling overflows
 // check if a > b
 #define CYCLES_GT(a, b) \
@@ -244,6 +288,12 @@ static void fillend_event(unsigned int now)
   p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, now);
 }
 
+static void hint_event(unsigned int now)
+{
+  p32x_trigger_irq(NULL, now, P32XI_HINT);
+  p32x_schedule_hint(NULL, now);
+}
+
 typedef void (event_cb)(unsigned int now);
 
 unsigned int event_times[P32X_EVENT_COUNT];
@@ -251,6 +301,7 @@ static unsigned int event_time_next;
 static event_cb *event_cbs[] = {
   [P32X_EVENT_PWM]      = p32x_pwm_irq_event,
   [P32X_EVENT_FILLEND]  = fillend_event,
+  [P32X_EVENT_HINT]     = hint_event,
 };
 
 // schedule event at some time 'after', in m68k clocks
@@ -323,16 +374,16 @@ static inline void run_sh2(SH2 *sh2, int m68k_cycles)
   pevt_log_sh2_o(sh2, EVT_RUN_START);
   sh2->state |= SH2_STATE_RUN;
   cycles = C_M68K_TO_SH2(*sh2, m68k_cycles);
-  elprintf(EL_32X, "%csh2 +run %u %d @%08x",
-    sh2->is_slave?'s':'m', sh2->m68krcycles_done, cycles, sh2->pc);
+  elprintf_sh2(sh2, EL_32X, "+run %u %d @%08x",
+    sh2->m68krcycles_done, cycles, sh2->pc);
 
   done = sh2_execute(sh2, cycles);
 
   sh2->m68krcycles_done += C_SH2_TO_M68K(*sh2, done);
   sh2->state &= ~SH2_STATE_RUN;
   pevt_log_sh2_o(sh2, EVT_RUN_END);
-  elprintf(EL_32X, "%csh2 -run %u %d",
-    sh2->is_slave?'s':'m', sh2->m68krcycles_done, done);
+  elprintf_sh2(sh2, EL_32X, "-run %u %d",
+    sh2->m68krcycles_done, done);
 }
 
 // sync other sh2 to this one
@@ -355,8 +406,8 @@ void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
     return;
   }
 
-  elprintf(EL_32X, "%csh2 sync to %u %d",
-    osh2->is_slave?'s':'m', m68k_target, m68k_cycles);
+  elprintf_sh2(osh2, EL_32X, "sync to %u %d",
+    m68k_target, m68k_cycles);
 
   run_sh2(osh2, m68k_cycles);
 
@@ -472,6 +523,8 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
 
 #define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
   SekRunM68k(m68k_cycles); \
+  if (Pico32x.emu_flags & P32XF_Z80_32X_IO) \
+    PicoSyncZ80(SekCycleCnt); \
   if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
     p32x_sync_sh2s(SekCyclesDoneT2()); \
 } while (0)
@@ -481,10 +534,14 @@ void sync_sh2s_lockstep(unsigned int m68k_target)
 
 void PicoFrame32x(void)
 {
+  Pico.m.scanline = 0;
+
   Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
   if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
     Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
 
+  if (!(Pico32x.sh2_regs[0] & 0x80))
+    p32x_schedule_hint(NULL, SekCyclesDoneT2());
   p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
   p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);