X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2Fmemory.c;h=0e19d69188e367c4760f21741be6a81f63d738a8;hb=4a1fb1832381958386c1dc91a8a5422af386441d;hp=6d6bbb76eb9c6bcfd8eee11b53f6d5b2087de47b;hpb=df63f1a6ff674808e641b67e3e60027b1e05c781;p=picodrive.git

diff --git a/pico/32x/memory.c b/pico/32x/memory.c
index 6d6bbb7..0e19d69 100644
--- a/pico/32x/memory.c
+++ b/pico/32x/memory.c
@@ -93,12 +93,12 @@ void p32x_m68k_poll_event(u32 flags)
   m68k_poll.addr = m68k_poll.cnt = 0;
 }
 
-static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
+static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags, int maxcnt)
 {
   int cycles_left = sh2_cycles_left(sh2);
 
   if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
-    if (sh2->poll_cnt++ > 3) {
+    if (sh2->poll_cnt++ > maxcnt) {
       if (!(sh2->state & flags))
         elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
           sh2->state, sh2->state | flags);
@@ -171,213 +171,6 @@ static u32 sh2_comm_faker(u32 a)
 }
 #endif
 
-// DMAC handling
-struct dma_chan {
-  unsigned int sar, dar;  // src, dst addr
-  unsigned int tcr;       // transfer count
-  unsigned int chcr;      // chan ctl
-  // -- dm dm sm sm  ts ts ar am  al ds dl tb  ta ie te de
-  // ts - transfer size: 1, 2, 4, 16 bytes
-  // ar - auto request if 1, else dreq signal
-  // ie - irq enable
-  // te - transfer end
-  // de - dma enable
-  #define DMA_AR (1 << 9)
-  #define DMA_IE (1 << 2)
-  #define DMA_TE (1 << 1)
-  #define DMA_DE (1 << 0)
-};
-
-struct dmac {
-  struct dma_chan chan[2];
-  unsigned int vcrdma0;
-  unsigned int unknown0;
-  unsigned int vcrdma1;
-  unsigned int unknown1;
-  unsigned int dmaor;
-  // -- pr ae nmif dme
-  // pr - priority: chan0 > chan1 or round-robin
-  // ae - address error
-  // nmif - nmi occurred
-  // dme - DMA master enable
-  #define DMA_DME  (1 << 0)
-};
-
-static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
-{
-  char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
-  struct dmac *dmac = (void *)(regs + 0x180);
-  int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
-  int vector = (chan == &dmac->chan[0]) ?
-               dmac->vcrdma0 : dmac->vcrdma1;
-
-  elprintf(EL_32X, "dmac irq %d %d", level, vector);
-  sh2_internal_irq(sh2, level, vector & 0x7f);
-}
-
-static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
-{
-  chan->chcr |= DMA_TE; // DMA has ended normally
-
-  p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
-  if (chan->chcr & DMA_IE)
-    dmac_te_irq(sh2, chan);
-}
-
-static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
-{
-  u32 size, d;
-
-  size = (chan->chcr >> 10) & 3;
-  switch (size) {
-  case 0:
-    d = p32x_sh2_read8(chan->sar, sh2);
-    p32x_sh2_write8(chan->dar, d, sh2);
-  case 1:
-    d = p32x_sh2_read16(chan->sar, sh2);
-    p32x_sh2_write16(chan->dar, d, sh2);
-    break;
-  case 2:
-    d = p32x_sh2_read32(chan->sar, sh2);
-    p32x_sh2_write32(chan->dar, d, sh2);
-    break;
-  case 3:
-    elprintf(EL_32X|EL_ANOMALY, "TODO: 16byte DMA");
-    chan->sar += 16; // always?
-    chan->tcr -= 4;
-    return;
-  }
-  chan->tcr--;
-
-  size = 1 << size;
-  if (chan->chcr & (1 << 15))
-    chan->dar -= size;
-  if (chan->chcr & (1 << 14))
-    chan->dar += size;
-  if (chan->chcr & (1 << 13))
-    chan->sar -= size;
-  if (chan->chcr & (1 << 12))
-    chan->sar += size;
-}
-
-static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
-{
-  unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
-  int i;
-
-  // debug/sanity checks
-  if (chan->tcr != *dreqlen)
-    elprintf(EL_32X|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
-      chan->tcr, *dreqlen);
-  // note: DACK is not connected, single addr mode should not be used
-  if ((chan->chcr & 0x3f08) != 0x0400)
-    elprintf(EL_32X|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
-  if (chan->sar != 0x20004012)
-    elprintf(EL_32X|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
-
-  // HACK: assume bus is busy and SH2 is halted
-  sh2->state |= SH2_STATE_SLEEP;
-
-  for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
-    elprintf(EL_32X, "dmaw [%08x] %04x, left %d",
-      chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
-    p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
-    chan->dar += 2;
-    chan->tcr--;
-    (*dreqlen)--;
-  }
-
-  if (Pico32x.dmac0_fifo_ptr != i)
-    memmove(Pico32x.dmac_fifo, &Pico32x.dmac_fifo[i],
-      (Pico32x.dmac0_fifo_ptr - i) * 2);
-  Pico32x.dmac0_fifo_ptr -= i;
-
-  Pico32x.regs[6 / 2] &= ~P32XS_FULL;
-  if (*dreqlen == 0)
-    Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
-  if (chan->tcr == 0)
-    dmac_transfer_complete(sh2, chan);
-  else
-    sh2_end_run(sh2, 16);
-}
-
-static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
-{
-  // debug/sanity checks
-  if ((chan->chcr & 0xc308) != 0x0000)
-    elprintf(EL_32X|EL_ANOMALY, "dreq1: bad control: %04x", chan->chcr);
-  if ((chan->dar & ~0xf) != 0x20004030)
-    elprintf(EL_32X|EL_ANOMALY, "dreq1: bad dar?: %08x\n", chan->dar);
-
-  dmac_transfer_one(sh2, chan);
-  if (chan->tcr == 0)
-    dmac_transfer_complete(sh2, chan);
-}
-
-static void dreq0_trigger(void)
-{
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
-
-  elprintf(EL_32X, "dreq0_trigger\n");
-  if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
-    dreq0_do(&msh2, &mdmac->chan[0]);
-  }
-  if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[0].chcr & 3) == DMA_DE) {
-    dreq0_do(&ssh2, &sdmac->chan[0]);
-  }
-}
-
-void p32x_dreq1_trigger(void)
-{
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
-  int hit = 0;
-
-  elprintf(EL_32X, "dreq1_trigger\n");
-  if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[1].chcr & 3) == DMA_DE) {
-    dreq1_do(&msh2, &mdmac->chan[1]);
-    hit = 1;
-  }
-  if ((sdmac->dmaor & DMA_DME) && (sdmac->chan[1].chcr & 3) == DMA_DE) {
-    dreq1_do(&ssh2, &sdmac->chan[1]);
-    hit = 1;
-  }
-
-  if (!hit)
-    elprintf(EL_32X|EL_ANOMALY, "dreq1: nobody cared");
-}
-
-// DMA trigger by SH2 register write
-static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
-{
-  elprintf(EL_32X, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
-    chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
-  chan->tcr &= 0xffffff;
-
-  if (chan->chcr & DMA_AR) {
-    // auto-request transfer
-    while ((int)chan->tcr > 0)
-      dmac_transfer_one(sh2, chan);
-    dmac_transfer_complete(sh2, chan);
-    return;
-  }
-
-  // DREQ0 is only sent after first 4 words are written.
-  // we do multiple of 4 words to avoid messing up alignment
-  if (chan->sar == 0x20004012) {
-    if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
-      elprintf(EL_32X, "68k -> sh2 DMA");
-      dreq0_trigger();
-    }
-    return;
-  }
-
-  elprintf(EL_32X|EL_ANOMALY, "unhandled DMA: "
-    "%08x->%08x, cnt %d, chcr %04x @%06x",
-    chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
-}
-
 // ------------------------------------------------------------------
 // 68k regs
 
@@ -405,7 +198,7 @@ static u32 p32x_reg_read16(u32 a)
       Pico32x.comm_dirty_sh2 &= ~comreg;
     else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
       SekSetStop(1);
-      SekEndTimeslice(16);
+      SekEndRun(16);
     }
     dr2 = SekDar(2);
     goto out;
@@ -420,7 +213,7 @@ static u32 p32x_reg_read16(u32 a)
   }
 
   if ((a & 0x30) == 0x30)
-    return p32x_pwm_read16(a, SekCyclesDoneT());
+    return p32x_pwm_read16(a, NULL, SekCyclesDoneT());
 
 out:
   return Pico32x.regs[a / 2];
@@ -444,15 +237,21 @@ static void p32x_reg_write8(u32 a, u32 d)
       r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
       return;
     case 3: // irq ctl
-      if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+      if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
         p32x_sync_sh2s(SekCyclesDoneT());
-        Pico32x.sh2irqi[0] |= P32XI_CMD;
-        p32x_update_irls(NULL);
+        if (d & 1)
+          Pico32x.sh2irqi[0] |= P32XI_CMD;
+        else
+          Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+        p32x_update_irls(NULL, SekCyclesDoneT2());
       }
-      if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+      if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) {
         p32x_sync_sh2s(SekCyclesDoneT());
-        Pico32x.sh2irqi[1] |= P32XI_CMD;
-        p32x_update_irls(NULL);
+        if (d & 2)
+          Pico32x.sh2irqi[1] |= P32XI_CMD;
+        else
+          Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+        p32x_update_irls(NULL, SekCyclesDoneT2());
       }
       return;
     case 5: // bank
@@ -518,10 +317,12 @@ static void p32x_reg_write16(u32 a, u32 d)
       if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
         Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
         if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
-          dreq0_trigger();
+          p32x_dreq0_trigger();
         if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
           r[6 / 2] |= P32XS_FULL;
       }
+      else
+        elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO overflow!");
       break;
   }
 
@@ -553,7 +354,7 @@ static void p32x_reg_write16(u32 a, u32 d)
   }
   // PWM
   else if ((a & 0x30) == 0x30) {
-    p32x_pwm_write16(a, d, SekCyclesDoneT());
+    p32x_pwm_write16(a, d, NULL, SekCyclesDoneT());
     return;
   }
 
@@ -564,9 +365,22 @@ static void p32x_reg_write16(u32 a, u32 d)
 // VDP regs
 static u32 p32x_vdp_read16(u32 a)
 {
+  u32 d;
   a &= 0x0e;
 
-  return Pico32x.vdp_regs[a / 2];
+  d = Pico32x.vdp_regs[a / 2];
+  if (a == 0x0a) {
+    // tested: FEN seems to be randomly pulsing on hcnt 0x80-0xf0,
+    // most often at 0xb1-0xb5, even during vblank,
+    // what's the deal with that?
+    // we'll just fake it along with hblank for now
+    Pico32x.vdp_fbcr_fake++;
+    if (Pico32x.vdp_fbcr_fake & 4)
+      d |= P32XV_HBLK;
+    if ((Pico32x.vdp_fbcr_fake & 7) == 0)
+      d |= P32XV_nFEN;
+  }
+  return d;
 }
 
 static void p32x_vdp_write8(u32 a, u32 d)
@@ -633,17 +447,18 @@ static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
 // ------------------------------------------------------------------
 // SH2 regs
 
-static u32 p32x_sh2reg_read16(u32 a, int cpuid)
+static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
 {
   u16 *r = Pico32x.regs;
   a &= 0xfe; // ?
 
   switch (a) {
     case 0x00: // adapter/irq ctl
-      return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
+      return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
+        | Pico32x.sh2irq_mask[sh2->is_slave];
     case 0x04: // H count (often as comm too)
-      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
-      sh2s_sync_on_read(&sh2s[cpuid]);
+      sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
+      sh2s_sync_on_read(sh2);
       return Pico32x.sh2_regs[4 / 2];
     case 0x10: // DREQ len
       return r[a / 2];
@@ -658,22 +473,22 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     if (Pico32x.comm_dirty_68k & comreg)
       Pico32x.comm_dirty_68k &= ~comreg;
     else
-      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
-    sh2s_sync_on_read(&sh2s[cpuid]);
+      sh2_poll_detect(sh2, a, SH2_STATE_CPOLL, 3);
+    sh2s_sync_on_read(sh2);
     return r[a / 2];
   }
   if ((a & 0x30) == 0x30) {
-    return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
+    return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
   }
 
   return 0;
 }
 
-static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
 {
   a &= 0xff;
 
-  sh2s[cpuid].poll_addr = 0;
+  sh2->poll_addr = 0;
 
   switch (a) {
     case 0: // FM
@@ -683,20 +498,20 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
     case 1: // HEN/irq masks
       if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
         elprintf(EL_ANOMALY|EL_32X, "HEN");
-      Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
+      Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x8f;
       Pico32x.sh2_regs[0] &= ~0x80;
       Pico32x.sh2_regs[0] |= d & 0x80;
       if (d & 1)
-        p32x_pwm_schedule_sh2(&sh2s[cpuid]);
-      p32x_update_irls(&sh2s[cpuid]);
+        p32x_pwm_schedule_sh2(sh2);
+      p32x_update_irls(sh2, 0);
       return;
     case 5: // H count
       d &= 0xff;
       if (Pico32x.sh2_regs[4 / 2] != d) {
         Pico32x.sh2_regs[4 / 2] = d;
-        p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-          sh2_cycles_done_m68k(&sh2s[cpuid]));
-        sh2_end_run(&sh2s[cpuid], 4);
+        p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+          sh2_cycles_done_m68k(sh2));
+        sh2_end_run(sh2, 4);
       }
       return;
   }
@@ -709,19 +524,19 @@ static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
 
     r8[a ^ 1] = d;
     p32x_m68k_poll_event(P32XF_68KCPOLL);
-    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(sh2));
     comreg = 1 << (a & 0x0f) / 2;
     Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
 }
 
-static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
 {
   a &= 0xfe;
 
-  sh2s[cpuid].poll_addr = 0;
+  sh2->poll_addr = 0;
 
   // comm
   if ((a & 0x30) == 0x20) {
@@ -731,15 +546,15 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
 
     Pico32x.regs[a / 2] = d;
     p32x_m68k_poll_event(P32XF_68KCPOLL);
-    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
-      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(sh2));
     comreg = 1 << (a & 0x0f) / 2;
     Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
   // PWM
   else if ((a & 0x30) == 0x30) {
-    p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
+    p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
     return;
   }
 
@@ -751,158 +566,22 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
     case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
     case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
     case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
-    case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
+    case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls;
     case 0x1c:
       Pico32x.sh2irqs &= ~P32XI_PWM;
-      p32x_pwm_schedule_sh2(&sh2s[cpuid]);
+      p32x_pwm_schedule_sh2(sh2);
       goto irls;
   }
 
-  p32x_sh2reg_write8(a | 1, d, cpuid);
+  p32x_sh2reg_write8(a | 1, d, sh2);
   return;
 
 irls:
-  p32x_update_irls(&sh2s[cpuid]);
+  p32x_update_irls(sh2, 0);
 }
 
 // ------------------------------------------------------------------
-// SH2 internal peripherals
-// we keep them in little endian format
-static u32 sh2_peripheral_read8(u32 a, int id)
-{
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  u32 d;
-
-  a &= 0x1ff;
-  d = PREG8(r, a);
-
-  elprintf(EL_32X, "%csh2 peri r8  [%08x]       %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static u32 sh2_peripheral_read16(u32 a, int id)
-{
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  u32 d;
-
-  a &= 0x1ff;
-  d = r[(a / 2) ^ 1];
-
-  elprintf(EL_32X, "%csh2 peri r16 [%08x]     %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static u32 sh2_peripheral_read32(u32 a, int id)
-{
-  u32 d;
-  a &= 0x1fc;
-  d = Pico32xMem->sh2_peri_regs[id][a / 4];
-
-  elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
-{
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w8  [%08x]       %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1ff;
-  PREG8(r, a) = d;
-
-  // X-men SCI hack
-  if ((a == 2 &&  (d & 0x20)) || // transmiter enabled
-      (a == 4 && !(d & 0x80))) { // valid data in TDR
-    void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
-    if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
-      int level = PREG8(oregs, 0x60) >> 4;
-      int vector = PREG8(oregs, 0x63) & 0x7f;
-      elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
-      sh2_internal_irq(&sh2s[id ^ 1], level, vector);
-      return 1;
-    }
-  }
-  return 0;
-}
-
-static int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
-{
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w16 [%08x]     %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1ff;
-
-  // evil WDT
-  if (a == 0x80) {
-    if ((d & 0xff00) == 0xa500) { // WTCSR
-      PREG8(r, 0x80) = d;
-      p32x_timers_recalc();
-    }
-    if ((d & 0xff00) == 0x5a00) // WTCNT
-      PREG8(r, 0x81) = d;
-    return 0;
-  }
-
-  r[(a / 2) ^ 1] = d;
-  return 0;
-}
-
-static void sh2_peripheral_write32(u32 a, u32 d, int id)
-{
-  u32 *r = Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1fc;
-  r[a / 4] = d;
-
-  switch (a) {
-    // division unit (TODO: verify):
-    case 0x104: // DVDNT: divident L, starts divide
-      elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
-      if (r[0x100 / 4]) {
-        signed int divisor = r[0x100 / 4];
-                       r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
-        r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
-      }
-      else
-        r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
-      break;
-    case 0x114:
-      elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
-        id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
-      if (r[0x100 / 4]) {
-        signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
-        signed int divisor = r[0x100 / 4];
-        // XXX: undocumented mirroring to 0x118,0x11c?
-        r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
-        divident /= divisor;
-        r[0x11c / 4] = r[0x114 / 4] = divident;
-        divident >>= 31;
-        if ((unsigned long long)divident + 1 > 1) {
-          //elprintf(EL_32X, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
-          r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
-        }
-      }
-      else
-        r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
-      break;
-  }
-
-  // perhaps starting a DMA?
-  if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
-    struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
-    if (!(dmac->dmaor & DMA_DME))
-      return;
-
-    if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[0]);
-    if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[1]);
-  }
-}
-
-// ------------------------------------------------------------------
-// 32x handlers
+// 32x 68k handlers
 
 // after ADEN
 static u32 PicoRead8_32x_on(u32 a)
@@ -1141,6 +820,44 @@ void PicoWrite16_32x(u32 a, u32 d)
   elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
 }
 
+/* quirk: in both normal and overwrite areas only nonzero values go through */
+#define sh2_write8_dramN(n) \
+  if ((d & 0xff) != 0) { \
+    u8 *dram = (u8 *)Pico32xMem->dram[n]; \
+    dram[(a & 0x1ffff) ^ 1] = d; \
+  }
+
+static void m68k_write8_dram0_ow(u32 a, u32 d)
+{
+  sh2_write8_dramN(0);
+}
+
+static void m68k_write8_dram1_ow(u32 a, u32 d)
+{
+  sh2_write8_dramN(1);
+}
+
+#define sh2_write16_dramN(n) \
+  u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
+  if (!(a & 0x20000)) { \
+    *pd = d; \
+    return; \
+  } \
+  /* overwrite */ \
+  if (!(d & 0xff00)) d |= *pd & 0xff00; \
+  if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
+  *pd = d;
+
+static void m68k_write16_dram0_ow(u32 a, u32 d)
+{
+  sh2_write16_dramN(0);
+}
+
+static void m68k_write16_dram1_ow(u32 a, u32 d)
+{
+  sh2_write16_dramN(1);
+}
+
 // -----------------------------------------------------------------
 
 // hint vector is writeable
@@ -1196,33 +913,33 @@ static void bank_switch(int b)
 // -----------------------------------------------------------------
 
 // read8
-static u32 sh2_read8_unmapped(u32 a, int id)
+static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped r8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, 0, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
   return 0;
 }
 
-static u32 sh2_read8_cs0(u32 a, int id)
+static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
 {
   u32 d = 0;
 
   // 0x3ff00 is veridied
   if ((a & 0x3ff00) == 0x4000) {
-    d = p32x_sh2reg_read16(a, id);
+    d = p32x_sh2reg_read16(a, sh2);
     goto out_16to8;
   }
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+    sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
     goto out_16to8;
   }
 
   // TODO: mirroring?
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+  if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
     return Pico32xMem->sh2_rom_m[a ^ 1];
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+  if (sh2->is_slave  && a < sizeof(Pico32xMem->sh2_rom_s))
     return Pico32xMem->sh2_rom_s[a ^ 1];
 
   if ((a & 0x3fe00) == 0x4200) {
@@ -1230,7 +947,7 @@ static u32 sh2_read8_cs0(u32 a, int id)
     goto out_16to8;
   }
 
-  return sh2_read8_unmapped(a, id);
+  return sh2_read8_unmapped(a, sh2);
 
 out_16to8:
   if (a & 1)
@@ -1239,29 +956,29 @@ out_16to8:
     d >>= 8;
 
   elprintf(EL_32X, "%csh2 r8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
   return d;
 }
 
-static u32 sh2_read8_da(u32 a, int id)
+static u32 sh2_read8_da(u32 a, SH2 *sh2)
 {
-  return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+  return sh2->data_array[(a & 0xfff) ^ 1];
 }
 
 // read16
-static u32 sh2_read16_unmapped(u32 a, int id)
+static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped r16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, 0, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
   return 0;
 }
 
-static u32 sh2_read16_cs0(u32 a, int id)
+static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
 {
   u32 d = 0;
 
   if ((a & 0x3ff00) == 0x4000) {
-    d = p32x_sh2reg_read16(a, id);
+    d = p32x_sh2reg_read16(a, sh2);
     if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
       return d;
     goto out;
@@ -1269,13 +986,13 @@ static u32 sh2_read16_cs0(u32 a, int id)
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+    sh2_poll_detect(sh2, a, SH2_STATE_VPOLL, 7);
     goto out;
   }
 
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+  if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
     return *(u16 *)(Pico32xMem->sh2_rom_m + a);
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+  if (sh2->is_slave  && a < sizeof(Pico32xMem->sh2_rom_s))
     return *(u16 *)(Pico32xMem->sh2_rom_s + a);
 
   if ((a & 0x3fe00) == 0x4200) {
@@ -1283,183 +1000,159 @@ static u32 sh2_read16_cs0(u32 a, int id)
     goto out;
   }
 
-  return sh2_read16_unmapped(a, id);
+  return sh2_read16_unmapped(a, sh2);
 
 out:
   elprintf(EL_32X, "%csh2 r16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
   return d;
 }
 
-static u32 sh2_read16_da(u32 a, int id)
+static u32 sh2_read16_da(u32 a, SH2 *sh2)
 {
-  return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+  return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
 }
 
-static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+// writes
+static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
 {
-  return 0;
 }
 
 // write8
-static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped w8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
-  return 0;
+    sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
 }
 
-static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_32X, "%csh2 w8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+    sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
 
   if (Pico32x.regs[0] & P32XS_FM) {
     if ((a & 0x3ff00) == 0x4100) {
-      sh2s[id].poll_addr = 0;
+      sh2->poll_addr = 0;
       p32x_vdp_write8(a, d);
-      return 0;
+      return;
     }
   }
 
   if ((a & 0x3ff00) == 0x4000) {
-    p32x_sh2reg_write8(a, d, id);
-    return 1;
+    p32x_sh2reg_write8(a, d, sh2);
+    return;
   }
 
-  return sh2_write8_unmapped(a, d, id);
+  sh2_write8_unmapped(a, d, sh2);
 }
 
-/* quirk: in both normal and overwrite areas only nonzero values go through */
-#define sh2_write8_dramN(n) \
-  if ((d & 0xff) != 0) { \
-    u8 *dram = (u8 *)Pico32xMem->dram[n]; \
-    dram[(a & 0x1ffff) ^ 1] = d; \
-  } \
-  return 0;
-
-static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write8_dramN(0);
 }
 
-static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write8_dramN(1);
 }
 
-static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0x3ffff;
 #ifdef DRC_SH2
   int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
   if (t)
-    sh2_drc_wcheck_ram(a, t, id);
+    sh2_drc_wcheck_ram(a, t, sh2->is_slave);
 #endif
   Pico32xMem->sdram[a1 ^ 1] = d;
-  return 0;
 }
 
-static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0xfff;
 #ifdef DRC_SH2
+  int id = sh2->is_slave;
   int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
   if (t)
     sh2_drc_wcheck_da(a, t, id);
 #endif
-  Pico32xMem->data_array[id][a1 ^ 1] = d;
-  return 0;
+  sh2->data_array[a1 ^ 1] = d;
 }
 
 // write16
-static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
 {
   elprintf(EL_UIO, "%csh2 unmapped w16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
-  return 0;
+    sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
 }
 
-static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
 {
   if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
     elprintf(EL_32X, "%csh2 w16 [%08x]     %04x @%06x",
-      id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+      sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
 
   if (Pico32x.regs[0] & P32XS_FM) {
     if ((a & 0x3ff00) == 0x4100) {
-      sh2s[id].poll_addr = 0;
-      p32x_vdp_write16(a, d, &sh2s[id]);
-      return 0;
+      sh2->poll_addr = 0;
+      p32x_vdp_write16(a, d, sh2);
+      return;
     }
 
     if ((a & 0x3fe00) == 0x4200) {
       Pico32xMem->pal[(a & 0x1ff) / 2] = d;
       Pico32x.dirty_pal = 1;
-      return 0;
+      return;
     }
   }
 
   if ((a & 0x3ff00) == 0x4000) {
-    p32x_sh2reg_write16(a, d, id);
-    return 1;
+    p32x_sh2reg_write16(a, d, sh2);
+    return;
   }
 
-  return sh2_write16_unmapped(a, d, id);
+  sh2_write16_unmapped(a, d, sh2);
 }
 
-#define sh2_write16_dramN(n) \
-  u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
-  if (!(a & 0x20000)) { \
-    *pd = d; \
-    return 0; \
-  } \
-  /* overwrite */ \
-  if (!(d & 0xff00)) d |= *pd & 0xff00; \
-  if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
-  *pd = d; \
-  return 0
-
-static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write16_dramN(0);
 }
 
-static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
 {
   sh2_write16_dramN(1);
 }
 
-static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0x3ffff;
 #ifdef DRC_SH2
   int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
   if (t)
-    sh2_drc_wcheck_ram(a, t, id);
+    sh2_drc_wcheck_ram(a, t, sh2->is_slave);
 #endif
   ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
-  return 0;
 }
 
-static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
 {
   u32 a1 = a & 0xfff;
 #ifdef DRC_SH2
+  int id = sh2->is_slave;
   int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
   if (t)
     sh2_drc_wcheck_da(a, t, id);
 #endif
-  ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
-  return 0;
+  ((u16 *)sh2->data_array)[a1 / 2] = d;
 }
 
 
-typedef u32 (sh2_read_handler)(u32 a, int id);
-typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
+typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
+typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
 
 #define SH2MAP_ADDR2OFFS_R(a) \
-  ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
+  ((u32)(a) >> SH2_READ_SHIFT)
 
 #define SH2MAP_ADDR2OFFS_W(a) \
   ((u32)(a) >> SH2_WRITE_SHIFT)
@@ -1472,7 +1165,7 @@ u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
   sh2_map += SH2MAP_ADDR2OFFS_R(a);
   p = sh2_map->addr;
   if (map_flag_set(p))
-    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+    return ((sh2_read_handler *)(p << 1))(a, sh2);
   else
     return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
 }
@@ -1485,7 +1178,7 @@ u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
   sh2_map += SH2MAP_ADDR2OFFS_R(a);
   p = sh2_map->addr;
   if (map_flag_set(p))
-    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+    return ((sh2_read_handler *)(p << 1))(a, sh2);
   else
     return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
 }
@@ -1507,48 +1200,46 @@ u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
   }
 
   if (offs == 0x1f)
-    return sh2_peripheral_read32(a, sh2->is_slave);
+    return sh2_peripheral_read32(a, sh2);
 
   handler = (sh2_read_handler *)(p << 1);
-  return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
+  return (handler(a, sh2) << 16) | handler(a + 2, sh2);
 }
 
-// return nonzero if write potentially causes an interrupt (used by drc)
-int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write8_tab;
   sh2_write_handler *wh;
 
   wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
-  return wh(a, d, sh2->is_slave);
+  wh(a, d, sh2);
 }
 
-int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write16_tab;
   sh2_write_handler *wh;
 
   wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
-  return wh(a, d, sh2->is_slave);
+  wh(a, d, sh2);
 }
 
-int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
 {
   const void **sh2_wmap = sh2->write16_tab;
-  sh2_write_handler *handler;
+  sh2_write_handler *wh;
   u32 offs;
 
   offs = SH2MAP_ADDR2OFFS_W(a);
 
   if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
-    sh2_peripheral_write32(a, d, sh2->is_slave);
-    return 0;
+    sh2_peripheral_write32(a, d, sh2);
+    return;
   }
 
-  handler = sh2_wmap[offs];
-  handler(a, d >> 16, sh2->is_slave);
-  handler(a + 2, d, sh2->is_slave);
-  return 0;
+  wh = sh2_wmap[offs];
+  wh(a, d >> 16, sh2);
+  wh(a + 2, d, sh2);
 }
 
 // -----------------------------------------------------------------
@@ -1675,7 +1366,7 @@ static void get_bios(void)
 #define MAP_MEMORY(m) ((uptr)(m) >> 1)
 #define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
 
-static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
+static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
 // for writes we are using handlers only
 static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
 
@@ -1683,12 +1374,16 @@ void Pico32xSwapDRAM(int b)
 {
   cpu68k_map_set(m68k_read8_map,   0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
   cpu68k_map_set(m68k_read16_map,  0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-  cpu68k_map_set(m68k_write8_map,  0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-  cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_read8_map,   0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_read16_map,  0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_write8_map,  0x840000, 0x87ffff,
+                 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
+  cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
+                 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
 
   // SH2
-  sh2_read8_map[2].addr   = sh2_read8_map[6].addr   =
-  sh2_read16_map[2].addr  = sh2_read16_map[6].addr  = MAP_MEMORY(Pico32xMem->dram[b]);
+  sh2_read8_map[0x04/2].addr  = sh2_read8_map[0x24/2].addr  =
+  sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
 
   sh2_write8_map[0x04/2]  = sh2_write8_map[0x24/2]  = b ? sh2_write8_dram1 : sh2_write8_dram0;
   sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
@@ -1760,35 +1455,35 @@ void PicoMemSetup32x(void)
   }
 
   // CS0
-  sh2_read8_map[0].addr   = sh2_read8_map[4].addr   = MAP_HANDLER(sh2_read8_cs0);
-  sh2_read16_map[0].addr  = sh2_read16_map[4].addr  = MAP_HANDLER(sh2_read16_cs0);
+  sh2_read8_map[0x00/2].addr  = sh2_read8_map[0x20/2].addr  = MAP_HANDLER(sh2_read8_cs0);
+  sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
   sh2_write8_map[0x00/2]  = sh2_write8_map[0x20/2]  = sh2_write8_cs0;
   sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
   // CS1 - ROM
-  sh2_read8_map[1].addr   = sh2_read8_map[5].addr   =
-  sh2_read16_map[1].addr  = sh2_read16_map[5].addr  = MAP_MEMORY(Pico.rom);
-  sh2_read8_map[1].mask   = sh2_read8_map[5].mask   =
-  sh2_read16_map[1].mask  = sh2_read16_map[5].mask  = 0x3fffff; // FIXME
+  sh2_read8_map[0x02/2].addr  = sh2_read8_map[0x22/2].addr  =
+  sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
+  sh2_read8_map[0x02/2].mask  = sh2_read8_map[0x22/2].mask  =
+  sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
   // CS2 - DRAM - done by Pico32xSwapDRAM()
-  sh2_read8_map[2].mask   = sh2_read8_map[6].mask   =
-  sh2_read16_map[2].mask  = sh2_read16_map[6].mask  = 0x01ffff;
+  sh2_read8_map[0x04/2].mask  = sh2_read8_map[0x24/2].mask  =
+  sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
   // CS3 - SDRAM
-  sh2_read8_map[3].addr   = sh2_read8_map[7].addr   =
-  sh2_read16_map[3].addr  = sh2_read16_map[7].addr  = MAP_MEMORY(Pico32xMem->sdram);
-  sh2_write8_map[0x06/2]  = sh2_write8_map[0x26/2]  = sh2_write8_sdram;
-  sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
-  sh2_read8_map[3].mask   = sh2_read8_map[7].mask   =
-  sh2_read16_map[3].mask  = sh2_read16_map[7].mask  = 0x03ffff;
+  sh2_read8_map[0x06/2].addr   = sh2_read8_map[0x26/2].addr   =
+  sh2_read16_map[0x06/2].addr  = sh2_read16_map[0x26/2].addr  = MAP_MEMORY(Pico32xMem->sdram);
+  sh2_write8_map[0x06/2]       = sh2_write8_map[0x26/2]       = sh2_write8_sdram;
+  sh2_write16_map[0x06/2]      = sh2_write16_map[0x26/2]      = sh2_write16_sdram;
+  sh2_read8_map[0x06/2].mask   = sh2_read8_map[0x26/2].mask   =
+  sh2_read16_map[0x06/2].mask  = sh2_read16_map[0x26/2].mask  = 0x03ffff;
   // SH2 data array
-  sh2_read8_map[0x18].addr   = MAP_HANDLER(sh2_read8_da);
-  sh2_read16_map[0x18].addr  = MAP_HANDLER(sh2_read16_da);
-  sh2_write8_map[0xc0/2]     = sh2_write8_da;
-  sh2_write16_map[0xc0/2]    = sh2_write16_da;
+  sh2_read8_map[0xc0/2].addr  = MAP_HANDLER(sh2_read8_da);
+  sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
+  sh2_write8_map[0xc0/2]      = sh2_write8_da;
+  sh2_write16_map[0xc0/2]     = sh2_write16_da;
   // SH2 IO
-  sh2_read8_map[0x1f].addr   = MAP_HANDLER(sh2_peripheral_read8);
-  sh2_read16_map[0x1f].addr  = MAP_HANDLER(sh2_peripheral_read16);
-  sh2_write8_map[0xff/2]     = sh2_peripheral_write8;
-  sh2_write16_map[0xff/2]    = sh2_peripheral_write16;
+  sh2_read8_map[0xff/2].addr  = MAP_HANDLER(sh2_peripheral_read8);
+  sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
+  sh2_write8_map[0xff/2]      = sh2_peripheral_write8;
+  sh2_write16_map[0xff/2]     = sh2_peripheral_write16;
 
   // map DRAM area, both 68k and SH2
   Pico32xSwapDRAM(1);