X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2Fmemory.c;h=45c192d588f36d6d8d505ac21d83a7899d00eefe;hb=c1931173ab49838b8e6f934b11de8ff0b8fbbcf3;hp=324c78908dc244a4e70c2ffe8b75694bdd3d668d;hpb=be2c420828ab3c36ef652584fbdef0e0597c7028;p=picodrive.git diff --git a/pico/32x/memory.c b/pico/32x/memory.c index 324c789..45c192d 100644 --- a/pico/32x/memory.c +++ b/pico/32x/memory.c @@ -1,45 +1,365 @@ +/* + * PicoDrive + * (C) notaz, 2009,2010,2013 + * + * This work is licensed under the terms of MAME license. + * See COPYING file in the top-level directory. + * + * Register map: + * a15100 F....... R.....EA F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm + * a15102 ........ ......SM ? 4002 // intS intM + * a15104 ........ ......10 ........ hhhhhhhh 4004 // bk1 bk0 Hint + * a15106 F....... .....SDR UE...... .....SDR 4006 // Full 68S Dma Rv fUll[fb] Empt[fb] + * a15108 (32bit DREQ src) 4008 + * a1510c (32bit DREQ dst) 400c + * a15110 llllllll llllll00 4010 // DREQ Len + * a15112 (16bit FIFO reg) 4012 + * a15114 ? (16bit VRES clr) 4014 + * a15116 ? (16bit Vint clr) 4016 + * a15118 ? (16bit Hint clr) 4018 + * a1511a ........ .......C (16bit CMD clr) 401a // Cm + * a1511c ? (16bit PWM clr) 401c + * a1511e ? ? 401e + * a15120 (16 bytes comm) 2020 + * a15130 (PWM) 2030 + * + * SH2 addr lines: + * iii. .cc. ..xx * // Internal, Cs, x + * + * sh2 map, wait/bus cycles (from docs): + * r w + * rom 0000000-0003fff 1 - + * sys reg 0004000-00040ff 1 1 + * vdp reg 0004100-00041ff 5 5 + * vdp pal 0004200-00043ff 5 5 + * rom 2000000-23fffff 6-15 + * dram/fb 4000000-401ffff 5-12 1-3 + * fb ovr 4020000-403ffff + * sdram 6000000-603ffff 12 2 (cycles) + * d.a. c0000000-? + */ #include "../pico_int.h" #include "../memory.h" +#include "../../cpu/sh2/compiler.h" static const char str_mars[] = "MARS"; -struct Pico32xMem { - u8 sdram[0x40000]; - u8 dram[0x40000]; // AKA fb - u8 m68k_rom[M68K_BANK_SIZE]; // 0x100 +void *p32x_bios_g, *p32x_bios_m, *p32x_bios_s; +struct Pico32xMem *Pico32xMem; + +static void bank_switch(int b); + +// poll detection +#define POLL_THRESHOLD 3 + +static struct { + u32 addr, cycles; + int cnt; +} m68k_poll; + +static int m68k_poll_detect(u32 a, u32 cycles, u32 flags) +{ + int ret = 0; + + if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2 + && cycles - m68k_poll.cycles <= 64) + { + if (m68k_poll.cnt++ > POLL_THRESHOLD) { + if (!(Pico32x.emu_flags & flags)) { + elprintf(EL_32X, "m68k poll addr %08x, cyc %u", + a, cycles - m68k_poll.cycles); + ret = 1; + } + Pico32x.emu_flags |= flags; + } + } + else { + m68k_poll.cnt = 0; + m68k_poll.addr = a; + } + m68k_poll.cycles = cycles; + + return ret; +} + +void p32x_m68k_poll_event(u32 flags) +{ + if (Pico32x.emu_flags & flags) { + elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags, + Pico32x.emu_flags & ~flags); + Pico32x.emu_flags &= ~flags; + SekSetStop(0); + } + m68k_poll.addr = m68k_poll.cnt = 0; +} + +static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags) +{ + int cycles_left = sh2_cycles_left(sh2); + + if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) { + if (sh2->poll_cnt++ > 3) { + if (!(sh2->state & flags)) + elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m', + sh2->state, sh2->state | flags); + + sh2->state |= flags; + sh2_end_run(sh2, 1); + pevt_log_sh2(sh2, EVT_POLL_START); + return; + } + } + else + sh2->poll_cnt = 0; + sh2->poll_addr = a; + sh2->poll_cycles = cycles_left; +} + +void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles) +{ + if (sh2->state & flags) { + elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m', + sh2->state, sh2->state & ~flags); + + if (sh2->m68krcycles_done < m68k_cycles) + sh2->m68krcycles_done = m68k_cycles; + + pevt_log_sh2_o(sh2, EVT_POLL_END); + } + + sh2->state &= ~flags; + sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0; +} + +static void sh2s_sync_on_read(SH2 *sh2) +{ + int cycles; + if (sh2->poll_cnt != 0) + return; + + cycles = sh2_cycles_done(sh2); + if (cycles > 600) + p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3); +} + +// SH2 faking +//#define FAKE_SH2 +#ifdef FAKE_SH2 +static int p32x_csum_faked; +static const u16 comm_fakevals[] = { + 0x4d5f, 0x4f4b, // M_OK + 0x535f, 0x4f4b, // S_OK + 0x4D41, 0x5346, // MASF - Brutal Unleashed + 0x5331, 0x4d31, // Darxide + 0x5332, 0x4d32, + 0x5333, 0x4d33, + 0x0000, 0x0000, // eq for doom + 0x0002, // Mortal Kombat +// 0, // pad }; -static struct Pico32xMem *Pico32xMem; +static u32 sh2_comm_faker(u32 a) +{ + static int f = 0; + if (a == 0x28 && !p32x_csum_faked) { + p32x_csum_faked = 1; + return *(unsigned short *)(Pico.rom + 0x18e); + } + if (f >= sizeof(comm_fakevals) / sizeof(comm_fakevals[0])) + f = 0; + return comm_fakevals[f++]; +} +#endif + +// ------------------------------------------------------------------ +// 68k regs static u32 p32x_reg_read16(u32 a) { a &= 0x3e; +#if 0 + if ((a & 0x30) == 0x20) + return sh2_comm_faker(a); +#else + if ((a & 0x30) == 0x20) { + static u32 dr2 = 0; + unsigned int cycles = SekCyclesDoneT(); + int comreg = 1 << (a & 0x0f) / 2; + + // evil X-Men proto polls in a dbra loop and expects it to expire.. + if (SekDar(2) != dr2) + m68k_poll.cnt = 0; + dr2 = SekDar(2); + + if (cycles - msh2.m68krcycles_done > 500) + p32x_sync_sh2s(cycles); + if (Pico32x.comm_dirty_sh2 & comreg) + Pico32x.comm_dirty_sh2 &= ~comreg; + else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) { + SekSetStop(1); + SekEndTimeslice(16); + } + dr2 = SekDar(2); + goto out; + } +#endif + + if (a == 2) { // INTM, INTS + unsigned int cycles = SekCyclesDoneT(); + if (cycles - msh2.m68krcycles_done > 64) + p32x_sync_sh2s(cycles); + return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3); + } + + if ((a & 0x30) == 0x30) + return p32x_pwm_read16(a, NULL, SekCyclesDoneT()); + +out: return Pico32x.regs[a / 2]; } -static void p32x_reg_write16(u32 a, u32 d) +static void p32x_reg_write8(u32 a, u32 d) { - a &= 0x3e; + u16 *r = Pico32x.regs; + a &= 0x3f; + + // for things like bset on comm port + m68k_poll.cnt = 0; - if (a == 0 && !(Pico32x.regs[0] & 1)) { - Pico32x.regs[0] |= 1; - Pico32xStartup(); + switch (a) { + case 0: // adapter ctl + r[0] = (r[0] & ~P32XS_FM) | ((d << 8) & P32XS_FM); + return; + case 1: // adapter ctl, RES bit writeable + if ((d ^ r[0]) & d & P32XS_nRES) + p32x_reset_sh2s(); + r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES); + return; + case 3: // irq ctl + if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) { + p32x_sync_sh2s(SekCyclesDoneT()); + if (d & 1) + Pico32x.sh2irqi[0] |= P32XI_CMD; + else + Pico32x.sh2irqi[0] &= ~P32XI_CMD; + p32x_update_irls(NULL, SekCyclesDoneT2()); + } + if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) { + p32x_sync_sh2s(SekCyclesDoneT()); + if (d & 2) + Pico32x.sh2irqi[1] |= P32XI_CMD; + else + Pico32x.sh2irqi[1] &= ~P32XI_CMD; + p32x_update_irls(NULL, SekCyclesDoneT2()); + } + return; + case 5: // bank + d &= 7; + if (r[4 / 2] != d) { + r[4 / 2] = d; + bank_switch(d); + } + return; + case 7: // DREQ ctl + r[6 / 2] = (r[6 / 2] & P32XS_FULL) | (d & (P32XS_68S|P32XS_DMA|P32XS_RV)); + return; + case 0x1b: // TV + r[0x1a / 2] = d; + return; + } + + if ((a & 0x30) == 0x20) { + u8 *r8 = (u8 *)r; + int cycles = SekCyclesDoneT(); + int comreg; + + if (r8[a ^ 1] == d) + return; + + comreg = 1 << (a & 0x0f) / 2; + if (Pico32x.comm_dirty_68k & comreg) + p32x_sync_sh2s(cycles); + + r8[a ^ 1] = d; + p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); + p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); + Pico32x.comm_dirty_68k |= comreg; + + if (cycles - (int)msh2.m68krcycles_done > 120) + p32x_sync_sh2s(cycles); return; } } -static void p32x_reg_write8(u32 a, u32 d) +static void p32x_reg_write16(u32 a, u32 d) { - a &= 0x3f; + u16 *r = Pico32x.regs; + a &= 0x3e; + + // for things like bset on comm port + m68k_poll.cnt = 0; + + switch (a) { + case 0x00: // adapter ctl + if ((d ^ r[0]) & d & P32XS_nRES) + p32x_reset_sh2s(); + r[0] = (r[0] & ~(P32XS_FM|P32XS_nRES)) | (d & (P32XS_FM|P32XS_nRES)); + return; + case 0x10: // DREQ len + r[a / 2] = d & ~3; + return; + case 0x12: // FIFO reg + if (!(r[6 / 2] & P32XS_68S)) { + elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?"); + return; + } + if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) { + Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d; + if ((Pico32x.dmac0_fifo_ptr & 3) == 0) + p32x_dreq0_trigger(); + if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN) + r[6 / 2] |= P32XS_FULL; + } + break; + } + + // DREQ src, dst + if ((a & 0x38) == 0x08) { + r[a / 2] = d; + return; + } + // comm port + else if ((a & 0x30) == 0x20) { + int cycles = SekCyclesDoneT(); + int comreg; + + if (r[a / 2] == d) + return; + + comreg = 1 << (a & 0x0f) / 2; + if (Pico32x.comm_dirty_68k & comreg) + p32x_sync_sh2s(cycles); - if (a == 1 && !(Pico32x.regs[0] & 1)) { - Pico32x.regs[0] |= 1; - Pico32xStartup(); + r[a / 2] = d; + p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles); + p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles); + Pico32x.comm_dirty_68k |= comreg; + + if (cycles - (int)msh2.m68krcycles_done > 120) + p32x_sync_sh2s(cycles); + return; + } + // PWM + else if ((a & 0x30) == 0x30) { + p32x_pwm_write16(a, d, NULL, SekCyclesDoneT()); return; } + + p32x_reg_write8(a + 1, d); } +// ------------------------------------------------------------------ // VDP regs static u32 p32x_vdp_read16(u32 a) { @@ -48,38 +368,207 @@ static u32 p32x_vdp_read16(u32 a) return Pico32x.vdp_regs[a / 2]; } -static void p32x_vdp_write16(u32 a, u32 d) +static void p32x_vdp_write8(u32 a, u32 d) { - a &= 0x0e; + u16 *r = Pico32x.vdp_regs; + a &= 0x0f; + // TODO: verify what's writeable switch (a) { - case 0x0a: - Pico32x.pending_fb = d & 1; - if (Pico.video.status & 8) { - Pico32x.vdp_regs[0x0a/2] &= ~1; - Pico32x.vdp_regs[0x0a/2] |= d & 1; + case 0x01: + // priority inversion is handled in palette + if ((r[0] ^ d) & P32XV_PRI) + Pico32x.dirty_pal = 1; + r[0] = (r[0] & P32XV_nPAL) | (d & 0xff); + break; + case 0x03: // shift (for pp mode) + r[2 / 2] = d & 1; + break; + case 0x05: // fill len + r[4 / 2] = d & 0xff; + break; + case 0x0b: + d &= 1; + Pico32x.pending_fb = d; + // if we are blanking and FS bit is changing + if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) { + r[0x0a/2] ^= P32XV_FS; + Pico32xSwapDRAM(d ^ 1); + elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS); } break; } } -static void p32x_vdp_write8(u32 a, u32 d) +static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2) { - a &= 0x0f; + a &= 0x0e; + if (a == 6) { // fill start + Pico32x.vdp_regs[6 / 2] = d; + return; + } + if (a == 8) { // fill data + u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1]; + int len = Pico32x.vdp_regs[4 / 2] + 1; + int len1 = len; + a = Pico32x.vdp_regs[6 / 2]; + while (len1--) { + dram[a] = d; + a = (a & 0xff00) | ((a + 1) & 0xff); + } + Pico32x.vdp_regs[0x06 / 2] = a; + Pico32x.vdp_regs[0x08 / 2] = d; + if (sh2 != NULL && len > 4) { + Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN; + // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles? + p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len); + } + return; + } + + p32x_vdp_write8(a | 1, d); +} + +// ------------------------------------------------------------------ +// SH2 regs + +static u32 p32x_sh2reg_read16(u32 a, int cpuid) +{ + u16 *r = Pico32x.regs; + a &= 0xfe; // ? switch (a) { - case 0x0b: - Pico32x.pending_fb = d & 1; - if (Pico.video.status & 8) { - Pico32x.vdp_regs[0x0a/2] &= ~1; - Pico32x.vdp_regs[0x0a/2] |= d & 1; + case 0x00: // adapter/irq ctl + return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid]; + case 0x04: // H count (often as comm too) + sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL); + sh2s_sync_on_read(&sh2s[cpuid]); + return Pico32x.sh2_regs[4 / 2]; + case 0x10: // DREQ len + return r[a / 2]; + } + + // DREQ src, dst + if ((a & 0x38) == 0x08) + return r[a / 2]; + // comm port + if ((a & 0x30) == 0x20) { + int comreg = 1 << (a & 0x0f) / 2; + if (Pico32x.comm_dirty_68k & comreg) + Pico32x.comm_dirty_68k &= ~comreg; + else + sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL); + sh2s_sync_on_read(&sh2s[cpuid]); + return r[a / 2]; + } + if ((a & 0x30) == 0x30) { + return p32x_pwm_read16(a, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid])); + } + + return 0; +} + +static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid) +{ + a &= 0xff; + + sh2s[cpuid].poll_addr = 0; + + switch (a) { + case 0: // FM + Pico32x.regs[0] &= ~P32XS_FM; + Pico32x.regs[0] |= (d << 8) & P32XS_FM; + return; + case 1: // HEN/irq masks + if ((d ^ Pico32x.sh2_regs[0]) & 0x80) + elprintf(EL_ANOMALY|EL_32X, "HEN"); + Pico32x.sh2irq_mask[cpuid] = d & 0x8f; + Pico32x.sh2_regs[0] &= ~0x80; + Pico32x.sh2_regs[0] |= d & 0x80; + if (d & 1) + p32x_pwm_schedule_sh2(&sh2s[cpuid]); + p32x_update_irls(&sh2s[cpuid], 0); + return; + case 5: // H count + d &= 0xff; + if (Pico32x.sh2_regs[4 / 2] != d) { + Pico32x.sh2_regs[4 / 2] = d; + p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, + sh2_cycles_done_m68k(&sh2s[cpuid])); + sh2_end_run(&sh2s[cpuid], 4); } + return; + } + + if ((a & 0x30) == 0x20) { + u8 *r8 = (u8 *)Pico32x.regs; + int comreg; + if (r8[a ^ 1] == d) + return; + + r8[a ^ 1] = d; + p32x_m68k_poll_event(P32XF_68KCPOLL); + p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, + sh2_cycles_done_m68k(&sh2s[cpuid])); + comreg = 1 << (a & 0x0f) / 2; + Pico32x.comm_dirty_sh2 |= comreg; + return; + } +} + +static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid) +{ + a &= 0xfe; + + sh2s[cpuid].poll_addr = 0; + + // comm + if ((a & 0x30) == 0x20) { + int comreg; + if (Pico32x.regs[a / 2] == d) + return; + + Pico32x.regs[a / 2] = d; + p32x_m68k_poll_event(P32XF_68KCPOLL); + p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL, + sh2_cycles_done_m68k(&sh2s[cpuid])); + comreg = 1 << (a & 0x0f) / 2; + Pico32x.comm_dirty_sh2 |= comreg; + return; + } + // PWM + else if ((a & 0x30) == 0x30) { + p32x_pwm_write16(a, d, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid])); + return; + } + + switch (a) { + case 0: // FM + Pico32x.regs[0] &= ~P32XS_FM; + Pico32x.regs[0] |= d & P32XS_FM; break; + case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls; + case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls; + case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls; + case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls; + case 0x1c: + Pico32x.sh2irqs &= ~P32XI_PWM; + p32x_pwm_schedule_sh2(&sh2s[cpuid]); + goto irls; } + + p32x_sh2reg_write8(a | 1, d, cpuid); + return; + +irls: + p32x_update_irls(&sh2s[cpuid], 0); } -// default 32x handlers -u32 PicoRead8_32x(u32 a) +// ------------------------------------------------------------------ +// 32x 68k handlers + +// after ADEN +static u32 PicoRead8_32x_on(u32 a) { u32 d = 0; if ((a & 0xffc0) == 0x5100) { // a15100 @@ -87,11 +576,19 @@ u32 PicoRead8_32x(u32 a) goto out_16to8; } - if ((a & 0xfff0) == 0x5180 && (Pico32x.regs[0] & 1)) { + if ((a & 0xfc00) != 0x5000) + return PicoRead8_io(a); + + if ((a & 0xfff0) == 0x5180) { // a15180 d = p32x_vdp_read16(a); goto out_16to8; } + if ((a & 0xfe00) == 0x5200) { // a15200 + d = Pico32xMem->pal[(a & 0x1ff) / 2]; + goto out_16to8; + } + if ((a & 0xfffc) == 0x30ec) { // a130ec d = str_mars[a & 3]; goto out; @@ -111,7 +608,7 @@ out: return d; } -u32 PicoRead16_32x(u32 a) +static u32 PicoRead16_32x_on(u32 a) { u32 d = 0; if ((a & 0xffc0) == 0x5100) { // a15100 @@ -119,11 +616,19 @@ u32 PicoRead16_32x(u32 a) goto out; } - if ((a & 0xfff0) == 0x5180 && (Pico32x.regs[0] & 1)) { // a15180 + if ((a & 0xfc00) != 0x5000) + return PicoRead16_io(a); + + if ((a & 0xfff0) == 0x5180) { // a15180 d = p32x_vdp_read16(a); goto out; } + if ((a & 0xfe00) == 0x5200) { // a15200 + d = Pico32xMem->pal[(a & 0x1ff) / 2]; + goto out; + } + if ((a & 0xfffc) == 0x30ec) { // a130ec d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; goto out; @@ -137,7 +642,7 @@ out: return d; } -void PicoWrite8_32x(u32 a, u32 d) +static void PicoWrite8_32x_on(u32 a, u32 d) { if ((a & 0xfc00) == 0x5000) elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); @@ -147,32 +652,199 @@ void PicoWrite8_32x(u32 a, u32 d) return; } - if ((a & 0xfff0) == 0x5180 && (Pico32x.regs[0] & 1)) { // a15180 - p32x_vdp_write8(a, d); + if ((a & 0xfc00) != 0x5000) { + PicoWrite8_io(a, d); return; } + if (!(Pico32x.regs[0] & P32XS_FM)) { + if ((a & 0xfff0) == 0x5180) { // a15180 + p32x_vdp_write8(a, d); + return; + } + + // TODO: verify + if ((a & 0xfe00) == 0x5200) { // a15200 + elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); + ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d; + Pico32x.dirty_pal = 1; + return; + } + } + elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); } -void PicoWrite16_32x(u32 a, u32 d) +static void PicoWrite16_32x_on(u32 a, u32 d) { if ((a & 0xfc00) == 0x5000) - elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); + elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); if ((a & 0xffc0) == 0x5100) { // a15100 p32x_reg_write16(a, d); return; } - if ((a & 0xfff0) == 0x5180 && (Pico32x.regs[0] & 1)) { // a15180 - p32x_vdp_write16(a, d); + if ((a & 0xfc00) != 0x5000) { + PicoWrite16_io(a, d); + return; + } + + if (!(Pico32x.regs[0] & P32XS_FM)) { + if ((a & 0xfff0) == 0x5180) { // a15180 + p32x_vdp_write16(a, d, NULL); // FIXME? + return; + } + + if ((a & 0xfe00) == 0x5200) { // a15200 + Pico32xMem->pal[(a & 0x1ff) / 2] = d; + Pico32x.dirty_pal = 1; + return; + } + } + + elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); +} + +// before ADEN +u32 PicoRead8_32x(u32 a) +{ + u32 d = 0; + if ((a & 0xffc0) == 0x5100) { // a15100 + // regs are always readable + d = ((u8 *)Pico32x.regs)[(a & 0x3f) ^ 1]; + goto out; + } + + if ((a & 0xfffc) == 0x30ec) { // a130ec + d = str_mars[a & 3]; + goto out; + } + + elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc); + return d; + +out: + elprintf(EL_32X, "m68k 32x r8 [%06x] %02x @%06x", a, d, SekPc); + return d; +} + +u32 PicoRead16_32x(u32 a) +{ + u32 d = 0; + if ((a & 0xffc0) == 0x5100) { // a15100 + d = Pico32x.regs[(a & 0x3f) / 2]; + goto out; + } + + if ((a & 0xfffc) == 0x30ec) { // a130ec + d = !(a & 2) ? ('M'<<8)|'A' : ('R'<<8)|'S'; + goto out; + } + + elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc); + return d; + +out: + elprintf(EL_32X, "m68k 32x r16 [%06x] %04x @%06x", a, d, SekPc); + return d; +} + +void PicoWrite8_32x(u32 a, u32 d) +{ + if ((a & 0xffc0) == 0x5100) { // a15100 + u16 *r = Pico32x.regs; + + elprintf(EL_32X, "m68k 32x w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); + a &= 0x3f; + if (a == 1) { + if ((d ^ r[0]) & d & P32XS_ADEN) { + Pico32xStartup(); + r[0] &= ~P32XS_nRES; // causes reset if specified by this write + r[0] |= P32XS_ADEN; + p32x_reg_write8(a, d); // forward for reset processing + } + return; + } + + // allow only COMM for now + if ((a & 0x30) == 0x20) { + u8 *r8 = (u8 *)r; + r8[a ^ 1] = d; + } + return; + } + + elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc); +} + +void PicoWrite16_32x(u32 a, u32 d) +{ + if ((a & 0xffc0) == 0x5100) { // a15100 + u16 *r = Pico32x.regs; + + elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); + a &= 0x3e; + if (a == 0) { + if ((d ^ r[0]) & d & P32XS_ADEN) { + Pico32xStartup(); + r[0] &= ~P32XS_nRES; // causes reset if specified by this write + r[0] |= P32XS_ADEN; + p32x_reg_write16(a, d); // forward for reset processing + } + return; + } + + // allow only COMM for now + if ((a & 0x30) == 0x20) + r[a / 2] = d; return; } elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); } +/* quirk: in both normal and overwrite areas only nonzero values go through */ +#define sh2_write8_dramN(n) \ + if ((d & 0xff) != 0) { \ + u8 *dram = (u8 *)Pico32xMem->dram[n]; \ + dram[(a & 0x1ffff) ^ 1] = d; \ + } + +static void m68k_write8_dram0_ow(u32 a, u32 d) +{ + sh2_write8_dramN(0); +} + +static void m68k_write8_dram1_ow(u32 a, u32 d) +{ + sh2_write8_dramN(1); +} + +#define sh2_write16_dramN(n, ret) \ + u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \ + if (!(a & 0x20000)) { \ + *pd = d; \ + return ret; \ + } \ + /* overwrite */ \ + if (!(d & 0xff00)) d |= *pd & 0xff00; \ + if (!(d & 0x00ff)) d |= *pd & 0x00ff; \ + *pd = d; \ + return ret + +static void m68k_write16_dram0_ow(u32 a, u32 d) +{ + sh2_write16_dramN(0,); +} + +static void m68k_write16_dram1_ow(u32 a, u32 d) +{ + sh2_write16_dramN(1,); +} + +// ----------------------------------------------------------------- + // hint vector is writeable static void PicoWrite8_hint(u32 a, u32 d) { @@ -194,36 +866,534 @@ static void PicoWrite16_hint(u32 a, u32 d) elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc); } -#define HWSWAP(x) (((x) << 16) | ((x) >> 16)) +static void bank_switch(int b) +{ + unsigned int rs, bank; + + bank = b << 20; + if (bank >= Pico.romsize) { + elprintf(EL_32X|EL_ANOMALY, "missing bank @ %06x", bank); + return; + } + + // 32X ROM (unbanked, XXX: consider mirroring?) + rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; + rs -= bank; + if (rs > 0x100000) + rs = 0x100000; + cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); + cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0); + + elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank); + +#ifdef EMU_F68K + // setup FAME fetchmap + for (rs = 0x90; rs < 0xa0; rs++) + PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000; +#endif +} + +// ----------------------------------------------------------------- +// SH2 +// ----------------------------------------------------------------- + +// read8 +static u32 sh2_read8_unmapped(u32 a, int id) +{ + elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x", + id ? 's' : 'm', a, 0, sh2_pc(id)); + return 0; +} + +static u32 sh2_read8_cs0(u32 a, int id) +{ + u32 d = 0; + + // 0x3ff00 is veridied + if ((a & 0x3ff00) == 0x4000) { + d = p32x_sh2reg_read16(a, id); + goto out_16to8; + } + + if ((a & 0x3ff00) == 0x4100) { + d = p32x_vdp_read16(a); + sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL); + goto out_16to8; + } + + // TODO: mirroring? + if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) + return Pico32xMem->sh2_rom_m[a ^ 1]; + if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) + return Pico32xMem->sh2_rom_s[a ^ 1]; + + if ((a & 0x3fe00) == 0x4200) { + d = Pico32xMem->pal[(a & 0x1ff) / 2]; + goto out_16to8; + } + + return sh2_read8_unmapped(a, id); + +out_16to8: + if (a & 1) + d &= 0xff; + else + d >>= 8; + + elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x", + id ? 's' : 'm', a, d, sh2_pc(id)); + return d; +} + +static u32 sh2_read8_da(u32 a, int id) +{ + return Pico32xMem->data_array[id][(a & 0xfff) ^ 1]; +} + +// read16 +static u32 sh2_read16_unmapped(u32 a, int id) +{ + elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x", + id ? 's' : 'm', a, 0, sh2_pc(id)); + return 0; +} + +static u32 sh2_read16_cs0(u32 a, int id) +{ + u32 d = 0; + + if ((a & 0x3ff00) == 0x4000) { + d = p32x_sh2reg_read16(a, id); + if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM + return d; + goto out; + } + + if ((a & 0x3ff00) == 0x4100) { + d = p32x_vdp_read16(a); + sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL); + goto out; + } + + if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m)) + return *(u16 *)(Pico32xMem->sh2_rom_m + a); + if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s)) + return *(u16 *)(Pico32xMem->sh2_rom_s + a); + + if ((a & 0x3fe00) == 0x4200) { + d = Pico32xMem->pal[(a & 0x1ff) / 2]; + goto out; + } + + return sh2_read16_unmapped(a, id); + +out: + elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x", + id ? 's' : 'm', a, d, sh2_pc(id)); + return d; +} + +static u32 sh2_read16_da(u32 a, int id) +{ + return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2]; +} + +static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id) +{ + return 0; +} + +// write8 +static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id) +{ + elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x", + id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); + return 0; +} + +static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id) +{ + elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x", + id ? 's' : 'm', a, d & 0xff, sh2_pc(id)); + + if (Pico32x.regs[0] & P32XS_FM) { + if ((a & 0x3ff00) == 0x4100) { + sh2s[id].poll_addr = 0; + p32x_vdp_write8(a, d); + return 0; + } + } + + if ((a & 0x3ff00) == 0x4000) { + p32x_sh2reg_write8(a, d, id); + return 1; + } + + return sh2_write8_unmapped(a, d, id); +} + +static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id) +{ + sh2_write8_dramN(0); + return 0; +} + +static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id) +{ + sh2_write8_dramN(1); + return 0; +} + +static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id) +{ + u32 a1 = a & 0x3ffff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; + if (t) + sh2_drc_wcheck_ram(a, t, id); +#endif + Pico32xMem->sdram[a1 ^ 1] = d; + return 0; +} + +static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id) +{ + u32 a1 = a & 0xfff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; + if (t) + sh2_drc_wcheck_da(a, t, id); +#endif + Pico32xMem->data_array[id][a1 ^ 1] = d; + return 0; +} + +// write16 +static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id) +{ + elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x", + id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); + return 0; +} + +static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id) +{ + if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM + elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x", + id ? 's' : 'm', a, d & 0xffff, sh2_pc(id)); + + if (Pico32x.regs[0] & P32XS_FM) { + if ((a & 0x3ff00) == 0x4100) { + sh2s[id].poll_addr = 0; + p32x_vdp_write16(a, d, &sh2s[id]); + return 0; + } + + if ((a & 0x3fe00) == 0x4200) { + Pico32xMem->pal[(a & 0x1ff) / 2] = d; + Pico32x.dirty_pal = 1; + return 0; + } + } + + if ((a & 0x3ff00) == 0x4000) { + p32x_sh2reg_write16(a, d, id); + return 1; + } + + return sh2_write16_unmapped(a, d, id); +} + +static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id) +{ + sh2_write16_dramN(0, 0); +} + +static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id) +{ + sh2_write16_dramN(1, 0); +} + +static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id) +{ + u32 a1 = a & 0x3ffff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT]; + if (t) + sh2_drc_wcheck_ram(a, t, id); +#endif + ((u16 *)Pico32xMem->sdram)[a1 / 2] = d; + return 0; +} + +static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id) +{ + u32 a1 = a & 0xfff; +#ifdef DRC_SH2 + int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT]; + if (t) + sh2_drc_wcheck_da(a, t, id); +#endif + ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d; + return 0; +} + + +typedef u32 (sh2_read_handler)(u32 a, int id); +typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id); + +#define SH2MAP_ADDR2OFFS_R(a) \ + ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c)) + +#define SH2MAP_ADDR2OFFS_W(a) \ + ((u32)(a) >> SH2_WRITE_SHIFT) + +u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2) +{ + const sh2_memmap *sh2_map = sh2->read8_map; + uptr p; + + sh2_map += SH2MAP_ADDR2OFFS_R(a); + p = sh2_map->addr; + if (map_flag_set(p)) + return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave); + else + return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1)); +} + +u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2) +{ + const sh2_memmap *sh2_map = sh2->read16_map; + uptr p; + + sh2_map += SH2MAP_ADDR2OFFS_R(a); + p = sh2_map->addr; + if (map_flag_set(p)) + return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave); + else + return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); +} + +u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2) +{ + const sh2_memmap *sh2_map = sh2->read16_map; + sh2_read_handler *handler; + u32 offs; + uptr p; + + offs = SH2MAP_ADDR2OFFS_R(a); + sh2_map += offs; + p = sh2_map->addr; + if (!map_flag_set(p)) { + // XXX: maybe 32bit access instead with ror? + u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1)); + return (pd[0] << 16) | pd[1]; + } + + if (offs == 0x1f) + return sh2_peripheral_read32(a, sh2->is_slave); + + handler = (sh2_read_handler *)(p << 1); + return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave); +} + +// return nonzero if write potentially causes an interrupt (used by drc) +int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2) +{ + const void **sh2_wmap = sh2->write8_tab; + sh2_write_handler *wh; + + wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; + return wh(a, d, sh2->is_slave); +} + +int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2) +{ + const void **sh2_wmap = sh2->write16_tab; + sh2_write_handler *wh; + + wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)]; + return wh(a, d, sh2->is_slave); +} + +int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2) +{ + const void **sh2_wmap = sh2->write16_tab; + sh2_write_handler *handler; + u32 offs; + + offs = SH2MAP_ADDR2OFFS_W(a); + + if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) { + sh2_peripheral_write32(a, d, sh2->is_slave); + return 0; + } + + handler = sh2_wmap[offs]; + handler(a, d >> 16, sh2->is_slave); + handler(a + 2, d, sh2->is_slave); + return 0; +} + +// ----------------------------------------------------------------- + +static const u16 msh2_code[] = { + // trap instructions + 0xaffe, // bra + 0x0009, // nop + // have to wait a bit until m68k initial program finishes clearing stuff + // to avoid races with game SH2 code, like in Tempo + 0xd004, // mov.l @(_m_ok,pc), r0 + 0xd105, // mov.l @(_cnt,pc), r1 + 0xd205, // mov.l @(_start,pc), r2 + 0x71ff, // add #-1, r1 + 0x4115, // cmp/pl r1 + 0x89fc, // bt -2 + 0xc208, // mov.l r0, @(h'20,gbr) + 0x6822, // mov.l @r2, r8 + 0x482b, // jmp @r8 + 0x0009, // nop + ('M'<<8)|'_', ('O'<<8)|'K', + 0x0001, 0x0000, + 0x2200, 0x03e0 // master start pointer in ROM +}; + +static const u16 ssh2_code[] = { + 0xaffe, // bra + 0x0009, // nop + // code to wait for master, in case authentic master BIOS is used + 0xd104, // mov.l @(_m_ok,pc), r1 + 0xd206, // mov.l @(_start,pc), r2 + 0xc608, // mov.l @(h'20,gbr), r0 + 0x3100, // cmp/eq r0, r1 + 0x8bfc, // bf #-2 + 0xd003, // mov.l @(_s_ok,pc), r0 + 0xc209, // mov.l r0, @(h'24,gbr) + 0x6822, // mov.l @r2, r8 + 0x482b, // jmp @r8 + 0x0009, // nop + ('M'<<8)|'_', ('O'<<8)|'K', + ('S'<<8)|'_', ('O'<<8)|'K', + 0x2200, 0x03e4 // slave start pointer in ROM +}; + +#define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16)) +static void get_bios(void) +{ + u16 *ps; + u32 *pl; + int i; + + // M68K ROM + if (p32x_bios_g != NULL) { + elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS"); + Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom)); + } + else { + // generate 68k ROM + ps = (u16 *)Pico32xMem->m68k_rom; + pl = (u32 *)ps; + for (i = 1; i < 0xc0/4; i++) + pl[i] = HWSWAP(0x880200 + (i - 1) * 6); + + // fill with nops + for (i = 0xc0/2; i < 0x100/2; i++) + ps[i] = 0x4e71; + +#if 0 + ps[0xc0/2] = 0x46fc; + ps[0xc2/2] = 0x2700; // move #0x2700,sr + ps[0xfe/2] = 0x60fe; // jump to self +#else + ps[0xfe/2] = 0x4e75; // rts +#endif + } + // fill remaining m68k_rom page with game ROM + memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom), + Pico.rom + sizeof(Pico32xMem->m68k_rom), + sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom)); + + // MSH2 + if (p32x_bios_m != NULL) { + elprintf(EL_STATUS|EL_32X, "32x: using supplied master SH2 BIOS"); + Byteswap(Pico32xMem->sh2_rom_m, p32x_bios_m, sizeof(Pico32xMem->sh2_rom_m)); + } + else { + pl = (u32 *)Pico32xMem->sh2_rom_m; + + // fill exception vector table to our trap address + for (i = 0; i < 128; i++) + pl[i] = HWSWAP(0x200); + + // startup code + memcpy(Pico32xMem->sh2_rom_m + 0x200, msh2_code, sizeof(msh2_code)); + + // reset SP + pl[1] = pl[3] = HWSWAP(0x6040000); + // start + pl[0] = pl[2] = HWSWAP(0x204); + } + + // SSH2 + if (p32x_bios_s != NULL) { + elprintf(EL_STATUS|EL_32X, "32x: using supplied slave SH2 BIOS"); + Byteswap(Pico32xMem->sh2_rom_s, p32x_bios_s, sizeof(Pico32xMem->sh2_rom_s)); + } + else { + pl = (u32 *)Pico32xMem->sh2_rom_s; + + // fill exception vector table to our trap address + for (i = 0; i < 128; i++) + pl[i] = HWSWAP(0x200); + + // startup code + memcpy(Pico32xMem->sh2_rom_s + 0x200, ssh2_code, sizeof(ssh2_code)); + + // reset SP + pl[1] = pl[3] = HWSWAP(0x603f800); + // start + pl[0] = pl[2] = HWSWAP(0x204); + } +} + +#define MAP_MEMORY(m) ((uptr)(m) >> 1) +#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) ) + +static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20]; +// for writes we are using handlers only +static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80]; + +void Pico32xSwapDRAM(int b) +{ + cpu68k_map_set(m68k_read8_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); + cpu68k_map_set(m68k_read16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0); + cpu68k_map_set(m68k_read8_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); + cpu68k_map_set(m68k_read16_map, 0x860000, 0x87ffff, Pico32xMem->dram[b], 0); + cpu68k_map_set(m68k_write8_map, 0x840000, 0x87ffff, + b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1); + cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff, + b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1); + + // SH2 + sh2_read8_map[2].addr = sh2_read8_map[6].addr = + sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]); + + sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0; + sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0; +} + void PicoMemSetup32x(void) { - unsigned short *ps; - unsigned int *pl; - unsigned int rs, rs1; + unsigned int rs; int i; - Pico32xMem = calloc(1, sizeof(*Pico32xMem)); + Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0); if (Pico32xMem == NULL) { elprintf(EL_STATUS, "OOM"); return; } - // generate 68k ROM - ps = (unsigned short *)Pico32xMem->m68k_rom; - pl = (unsigned int *)Pico32xMem->m68k_rom; - for (i = 1; i < 0xc0/4; i++) - pl[i] = HWSWAP(0x880200 + i * 6); - - // fill with nops - for (i = 0xc0/2; i < 0x100/2; i++) - ps[i] = 0x4e71; - - ps[0xc0/2] = 0x46fc; - ps[0xc2/2] = 0x2700; // move #0x2700,sr - ps[0xfe/2] = 0x60fe; // jump to self - - // fill remaining mem with ROM - memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, M68K_BANK_SIZE - 0x100); + get_bios(); // cartridge area becomes unmapped // XXX: we take the easy way and don't unmap ROM, @@ -231,22 +1401,110 @@ void PicoMemSetup32x(void) // m68k_map_unmap(0x000000, 0x3fffff); // MD ROM area - cpu68k_map_set(m68k_read8_map, 0x000000, M68K_BANK_SIZE - 1, Pico32xMem->m68k_rom, 0); - cpu68k_map_set(m68k_read16_map, 0x000000, M68K_BANK_SIZE - 1, Pico32xMem->m68k_rom, 0); - cpu68k_map_set(m68k_write8_map, 0x000000, M68K_BANK_SIZE - 1, PicoWrite8_hint, 1); // TODO verify - cpu68k_map_set(m68k_write16_map, 0x000000, M68K_BANK_SIZE - 1, PicoWrite16_hint, 1); + rs = sizeof(Pico32xMem->m68k_rom_bank); + cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); + cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0); + cpu68k_map_set(m68k_write8_map, 0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify + cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1); // 32X ROM (unbanked, XXX: consider mirroring?) - rs1 = rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; - if (rs1 > 0x80000) - rs1 = 0x80000; - cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs1 - 1, Pico.rom, 0); - cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs1 - 1, Pico.rom, 0); + rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK; + if (rs > 0x80000) + rs = 0x80000; + cpu68k_map_set(m68k_read8_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); + cpu68k_map_set(m68k_read16_map, 0x880000, 0x880000 + rs - 1, Pico.rom, 0); +#ifdef EMU_F68K + // setup FAME fetchmap + PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom; + for (rs = 0x88; rs < 0x90; rs++) + PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000; +#endif // 32X ROM (banked) - if (rs > 0x100000) - rs = 0x100000; - cpu68k_map_set(m68k_read8_map, 0x900000, 0x900000 + rs - 1, Pico.rom, 0); - cpu68k_map_set(m68k_read16_map, 0x900000, 0x900000 + rs - 1, Pico.rom, 0); + bank_switch(0); + + // SYS regs + cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_32x_on, 1); + cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_32x_on, 1); + cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1); + cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1); + + // SH2 maps: A31,A30,A29,CS1,CS0 + // all unmapped by default + for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) { + sh2_read8_map[i].addr = MAP_HANDLER(sh2_read8_unmapped); + sh2_read16_map[i].addr = MAP_HANDLER(sh2_read16_unmapped); + } + + for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) { + sh2_write8_map[i] = sh2_write8_unmapped; + sh2_write16_map[i] = sh2_write16_unmapped; + } + + // "purge area" + for (i = 0x40; i <= 0x5f; i++) { + sh2_write8_map[i >> 1] = + sh2_write16_map[i >> 1] = sh2_write_ignore; + } + + // CS0 + sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0); + sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0); + sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0; + sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0; + // CS1 - ROM + sh2_read8_map[1].addr = sh2_read8_map[5].addr = + sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom); + sh2_read8_map[1].mask = sh2_read8_map[5].mask = + sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME + // CS2 - DRAM - done by Pico32xSwapDRAM() + sh2_read8_map[2].mask = sh2_read8_map[6].mask = + sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff; + // CS3 - SDRAM + sh2_read8_map[3].addr = sh2_read8_map[7].addr = + sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram); + sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram; + sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram; + sh2_read8_map[3].mask = sh2_read8_map[7].mask = + sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff; + // SH2 data array + sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da); + sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da); + sh2_write8_map[0xc0/2] = sh2_write8_da; + sh2_write16_map[0xc0/2] = sh2_write16_da; + // SH2 IO + sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8); + sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16); + sh2_write8_map[0xff/2] = sh2_peripheral_write8; + sh2_write16_map[0xff/2] = sh2_peripheral_write16; + + // map DRAM area, both 68k and SH2 + Pico32xSwapDRAM(1); + + msh2.read8_map = ssh2.read8_map = sh2_read8_map; + msh2.read16_map = ssh2.read16_map = sh2_read16_map; + msh2.write8_tab = ssh2.write8_tab = (const void **)(void *)sh2_write8_map; + msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map; + + sh2_drc_mem_setup(&msh2); + sh2_drc_mem_setup(&ssh2); +} + +void Pico32xMemStateLoaded(void) +{ + bank_switch(Pico32x.regs[4 / 2]); + Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS); + memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm)); + Pico32x.dirty_pal = 1; + + Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL); + memset(&m68k_poll, 0, sizeof(m68k_poll)); + msh2.state = 0; + msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0; + ssh2.state = 0; + ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0; + + sh2_drc_flush_all(); } +// vim:shiftwidth=2:ts=2:expandtab