X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2Fmemory.c;h=5ede2ea7dc9c2eeaf686792e4606228283e56a6c;hb=34280f9b424dc3964e3c3e1cfd2cd18c8041b5d8;hp=1b5bdd430b9d68317f44a1053e6107b598e563c6;hpb=83ff19ec52ff47992b5d6ceda3900b914eda2123;p=picodrive.git

diff --git a/pico/32x/memory.c b/pico/32x/memory.c
index 1b5bdd4..5ede2ea 100644
--- a/pico/32x/memory.c
+++ b/pico/32x/memory.c
@@ -1,4 +1,10 @@
 /*
+ * PicoDrive
+ * (C) notaz, 2009,2010,2013
+ *
+ * This work is licensed under the terms of MAME license.
+ * See COPYING file in the top-level directory.
+ *
  * Register map:
  * a15100 F....... R.....EA  F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
  * a15102 ........ ......SM  ?                 4002 // intS intM
@@ -16,16 +22,25 @@
  * a1511e ?                  ?                 401e
  * a15120            (16 bytes comm)           2020
  * a15130                 (PWM)                2030
+ *
+ * SH2 addr lines:
+ * iii. .cc. ..xx *   // Internal, Cs, x
+ *
+ * sh2 map, wait/bus cycles (from docs):
+ *                             r    w
+ * rom      0000000-0003fff    1    -
+ * sys reg  0004000-00040ff    1    1
+ * vdp reg  0004100-00041ff    5    5
+ * vdp pal  0004200-00043ff    5    5
+ * rom      2000000-23fffff     6-15
+ * dram/fb  4000000-401ffff 5-12  1-3
+ * fb ovr   4020000-403ffff
+ * sdram    6000000-603ffff   12    2  (cycles)
+ * d.a.    c0000000-?
  */
 #include "../pico_int.h"
 #include "../memory.h"
-
-#if 0
-#undef ash2_end_run
-#undef SekEndRun
-#define ash2_end_run(x)
-#define SekEndRun(x)
-#endif
+#include "../../cpu/sh2/compiler.h"
 
 static const char str_mars[] = "MARS";
 
@@ -35,70 +50,102 @@ struct Pico32xMem *Pico32xMem;
 static void bank_switch(int b);
 
 // poll detection
-#define POLL_THRESHOLD 6
+#define POLL_THRESHOLD 3
 
-struct poll_det {
-  u32 addr, cycles, cyc_max;
-  int cnt, flag;
-};
-static struct poll_det m68k_poll, sh2_poll[2];
+static struct {
+  u32 addr, cycles;
+  int cnt;
+} m68k_poll;
 
-static int p32x_poll_detect(struct poll_det *pd, u32 a, u32 cycles, int is_vdp)
+static int m68k_poll_detect(u32 a, u32 cycles, u32 flags)
 {
-  int ret = 0, flag = pd->flag;
-
-  if (is_vdp)
-    flag <<= 3;
-
-  if (a - 2 <= pd->addr && pd->addr <= a + 2 && cycles - pd->cycles <= pd->cyc_max) {
-    pd->cnt++;
-    if (pd->cnt > POLL_THRESHOLD) {
-      if (!(Pico32x.emu_flags & flag)) {
-        elprintf(EL_32X, "%s poll addr %08x, cyc %u",
-          flag & (P32XF_68KPOLL|P32XF_68KVPOLL) ? "m68k" :
-          (flag & (P32XF_MSH2POLL|P32XF_MSH2VPOLL) ? "msh2" : "ssh2"), a, cycles - pd->cycles);
+  int ret = 0;
+
+  if (a - 2 <= m68k_poll.addr && m68k_poll.addr <= a + 2
+    && cycles - m68k_poll.cycles <= 64)
+  {
+    if (m68k_poll.cnt++ > POLL_THRESHOLD) {
+      if (!(Pico32x.emu_flags & flags)) {
+        elprintf(EL_32X, "m68k poll addr %08x, cyc %u",
+          a, cycles - m68k_poll.cycles);
         ret = 1;
       }
-      Pico32x.emu_flags |= flag;
+      Pico32x.emu_flags |= flags;
     }
   }
   else {
-    pd->cnt = 0;
-    pd->addr = a;
+    m68k_poll.cnt = 0;
+    m68k_poll.addr = a;
   }
-  pd->cycles = cycles;
+  m68k_poll.cycles = cycles;
 
   return ret;
 }
 
-static int p32x_poll_undetect(struct poll_det *pd, int is_vdp)
+void p32x_m68k_poll_event(u32 flags)
 {
-  int ret = 0, flag = pd->flag;
-  if (is_vdp)
-    flag <<= 3; // VDP only
+  if (Pico32x.emu_flags & flags) {
+    elprintf(EL_32X, "m68k poll %02x -> %02x", Pico32x.emu_flags,
+      Pico32x.emu_flags & ~flags);
+    Pico32x.emu_flags &= ~flags;
+    SekSetStop(0);
+  }
+  m68k_poll.addr = m68k_poll.cnt = 0;
+}
+
+static void sh2_poll_detect(SH2 *sh2, u32 a, u32 flags)
+{
+  int cycles_left = sh2_cycles_left(sh2);
+
+  if (a == sh2->poll_addr && sh2->poll_cycles - cycles_left <= 10) {
+    if (sh2->poll_cnt++ > 3) {
+      if (!(sh2->state & flags))
+        elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
+          sh2->state, sh2->state | flags);
+
+      sh2->state |= flags;
+      sh2_end_run(sh2, 1);
+      pevt_log_sh2(sh2, EVT_POLL_START);
+      return;
+    }
+  }
   else
-    flag |= flag << 3; // both
-  if (Pico32x.emu_flags & flag) {
-    elprintf(EL_32X, "poll %02x -> %02x", Pico32x.emu_flags, Pico32x.emu_flags & ~flag);
-    ret = 1;
+    sh2->poll_cnt = 0;
+  sh2->poll_addr = a;
+  sh2->poll_cycles = cycles_left;
+}
+
+void p32x_sh2_poll_event(SH2 *sh2, u32 flags, u32 m68k_cycles)
+{
+  if (sh2->state & flags) {
+    elprintf(EL_32X, "%csh2 state: %02x->%02x", sh2->is_slave?'s':'m',
+      sh2->state, sh2->state & ~flags);
+
+    if (sh2->m68krcycles_done < m68k_cycles)
+      sh2->m68krcycles_done = m68k_cycles;
+
+    pevt_log_sh2_o(sh2, EVT_POLL_END);
   }
-  Pico32x.emu_flags &= ~flag;
-  pd->addr = pd->cnt = 0;
-  return ret;
+
+  sh2->state &= ~flags;
+  sh2->poll_addr = sh2->poll_cycles = sh2->poll_cnt = 0;
 }
 
-void p32x_poll_event(int cpu_mask, int is_vdp)
+static void sh2s_sync_on_read(SH2 *sh2)
 {
-  if (cpu_mask & 1)
-    p32x_poll_undetect(&sh2_poll[0], is_vdp);
-  if (cpu_mask & 2)
-    p32x_poll_undetect(&sh2_poll[1], is_vdp);
+  int cycles;
+  if (sh2->poll_cnt != 0)
+    return;
+
+  cycles = sh2_cycles_done(sh2);
+  if (cycles > 600)
+    p32x_sync_other_sh2(sh2, sh2->m68krcycles_done + cycles / 3);
 }
 
 // SH2 faking
 //#define FAKE_SH2
-int p32x_csum_faked;
 #ifdef FAKE_SH2
+static int p32x_csum_faked;
 static const u16 comm_fakevals[] = {
   0x4d5f, 0x4f4b, // M_OK
   0x535f, 0x4f4b, // S_OK
@@ -124,47 +171,6 @@ static u32 sh2_comm_faker(u32 a)
 }
 #endif
 
-// DMAC handling
-static struct {
-  unsigned int sar0, dar0, tcr0; // src addr, dst addr, transfer count
-  unsigned int chcr0; // chan ctl
-  unsigned int sar1, dar1, tcr1; // same for chan 1
-  unsigned int chcr1;
-  int pad[4];
-  unsigned int dmaor;
-} * dmac0;
-
-static void dma_68k2sh2_do(void)
-{
-  unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
-  int i;
-
-  if (dmac0->tcr0 != *dreqlen)
-    elprintf(EL_32X|EL_ANOMALY, "tcr0 and dreq len differ: %d != %d", dmac0->tcr0, *dreqlen);
-
-  // HACK: assume bus is busy and SH2 is halted
-  // XXX: use different mechanism for this, not poll det
-  Pico32x.emu_flags |= P32XF_MSH2POLL; // id ? P32XF_SSH2POLL : P32XF_MSH2POLL;
-
-  for (i = 0; i < Pico32x.dmac_ptr && dmac0->tcr0 > 0; i++) {
-    extern void p32x_sh2_write16(u32 a, u32 d, int id);
-      elprintf(EL_32X, "dmaw [%08x] %04x, left %d", dmac0->dar0, Pico32x.dmac_fifo[i], *dreqlen);
-    p32x_sh2_write16(dmac0->dar0, Pico32x.dmac_fifo[i], 0);
-    dmac0->dar0 += 2;
-    dmac0->tcr0--;
-    (*dreqlen)--;
-  }
-
-  Pico32x.dmac_ptr = 0; // HACK
-  Pico32x.regs[6 / 2] &= ~P32XS_FULL;
-  if (*dreqlen == 0)
-    Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
-  if (dmac0->tcr0 == 0) {
-    dmac0->chcr0 |= 2; // DMA has ended normally
-    p32x_poll_undetect(&sh2_poll[0], 0);
-  }
-}
-
 // ------------------------------------------------------------------
 // 68k regs
 
@@ -172,30 +178,44 @@ static u32 p32x_reg_read16(u32 a)
 {
   a &= 0x3e;
 
-  if (a == 2) // INTM, INTS
-    return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
 #if 0
   if ((a & 0x30) == 0x20)
     return sh2_comm_faker(a);
 #else
   if ((a & 0x30) == 0x20) {
-    // evil X-Men proto polls in a dbra loop and expects it to expire..
     static u32 dr2 = 0;
+    unsigned int cycles = SekCyclesDoneT();
+    int comreg = 1 << (a & 0x0f) / 2;
+
+    // evil X-Men proto polls in a dbra loop and expects it to expire..
     if (SekDar(2) != dr2)
       m68k_poll.cnt = 0;
     dr2 = SekDar(2);
 
-    if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
+    if (cycles - msh2.m68krcycles_done > 500)
+      p32x_sync_sh2s(cycles);
+    if (Pico32x.comm_dirty_sh2 & comreg)
+      Pico32x.comm_dirty_sh2 &= ~comreg;
+    else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
       SekSetStop(1);
       SekEndTimeslice(16);
     }
     dr2 = SekDar(2);
+    goto out;
   }
 #endif
 
+  if (a == 2) { // INTM, INTS
+    unsigned int cycles = SekCyclesDoneT();
+    if (cycles - msh2.m68krcycles_done > 64)
+      p32x_sync_sh2s(cycles);
+    return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
+  }
+
   if ((a & 0x30) == 0x30)
-    return p32x_pwm_read16(a);
+    return p32x_pwm_read16(a, SekCyclesDoneT());
 
+out:
   return Pico32x.regs[a / 2];
 }
 
@@ -218,14 +238,14 @@ static void p32x_reg_write8(u32 a, u32 d)
       return;
     case 3: // irq ctl
       if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+        p32x_sync_sh2s(SekCyclesDoneT());
         Pico32x.sh2irqi[0] |= P32XI_CMD;
-        p32x_update_irls();
-        SekEndRun(16);
+        p32x_update_irls(NULL);
       }
       if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+        p32x_sync_sh2s(SekCyclesDoneT());
         Pico32x.sh2irqi[1] |= P32XI_CMD;
-        p32x_update_irls();
-        SekEndRun(16);
+        p32x_update_irls(NULL);
       }
       return;
     case 5: // bank
@@ -245,12 +265,23 @@ static void p32x_reg_write8(u32 a, u32 d)
 
   if ((a & 0x30) == 0x20) {
     u8 *r8 = (u8 *)r;
+    int cycles = SekCyclesDoneT();
+    int comreg;
+    
+    if (r8[a ^ 1] == d)
+      return;
+
+    comreg = 1 << (a & 0x0f) / 2;
+    if (Pico32x.comm_dirty_68k & comreg)
+      p32x_sync_sh2s(cycles);
+
     r8[a ^ 1] = d;
-    p32x_poll_undetect(&sh2_poll[0], 0);
-    p32x_poll_undetect(&sh2_poll[1], 0);
-    // if some SH2 is busy waiting, it needs to see the result ASAP
-    if (SekCyclesLeftNoMCD > 32)
-      SekEndRun(32);
+    p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
+    p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
+    Pico32x.comm_dirty_68k |= comreg;
+
+    if (cycles - (int)msh2.m68krcycles_done > 120)
+      p32x_sync_sh2s(cycles);
     return;
   }
 }
@@ -275,13 +306,13 @@ static void p32x_reg_write16(u32 a, u32 d)
     case 0x12: // FIFO reg
       if (!(r[6 / 2] & P32XS_68S)) {
         elprintf(EL_32X|EL_ANOMALY, "DREQ FIFO w16 without 68S?");
-	return;
+        return;
       }
-      if (Pico32x.dmac_ptr < DMAC_FIFO_LEN) {
-        Pico32x.dmac_fifo[Pico32x.dmac_ptr++] = d;
-        if ((Pico32x.dmac_ptr & 3) == 0 && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1))
-          dma_68k2sh2_do();
-        if (Pico32x.dmac_ptr == DMAC_FIFO_LEN)
+      if (Pico32x.dmac0_fifo_ptr < DMAC_FIFO_LEN) {
+        Pico32x.dmac_fifo[Pico32x.dmac0_fifo_ptr++] = d;
+        if ((Pico32x.dmac0_fifo_ptr & 3) == 0)
+          p32x_dreq0_trigger();
+        if (Pico32x.dmac0_fifo_ptr == DMAC_FIFO_LEN)
           r[6 / 2] |= P32XS_FULL;
       }
       break;
@@ -293,18 +324,29 @@ static void p32x_reg_write16(u32 a, u32 d)
     return;
   }
   // comm port
-  else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
+  else if ((a & 0x30) == 0x20) {
+    int cycles = SekCyclesDoneT();
+    int comreg;
+    
+    if (r[a / 2] == d)
+      return;
+
+    comreg = 1 << (a & 0x0f) / 2;
+    if (Pico32x.comm_dirty_68k & comreg)
+      p32x_sync_sh2s(cycles);
+
     r[a / 2] = d;
-    p32x_poll_undetect(&sh2_poll[0], 0);
-    p32x_poll_undetect(&sh2_poll[1], 0);
-    // same as for w8
-    if (SekCyclesLeftNoMCD > 32)
-      SekEndRun(32);
+    p32x_sh2_poll_event(&sh2s[0], SH2_STATE_CPOLL, cycles);
+    p32x_sh2_poll_event(&sh2s[1], SH2_STATE_CPOLL, cycles);
+    Pico32x.comm_dirty_68k |= comreg;
+
+    if (cycles - (int)msh2.m68krcycles_done > 120)
+      p32x_sync_sh2s(cycles);
     return;
   }
   // PWM
   else if ((a & 0x30) == 0x30) {
-    p32x_pwm_write16(a, d);
+    p32x_pwm_write16(a, d, SekCyclesDoneT());
     return;
   }
 
@@ -325,9 +367,6 @@ static void p32x_vdp_write8(u32 a, u32 d)
   u16 *r = Pico32x.vdp_regs;
   a &= 0x0f;
 
-  // for FEN checks between writes
-  sh2_poll[0].cnt = 0;
-
   // TODO: verify what's writeable
   switch (a) {
     case 0x01:
@@ -336,6 +375,9 @@ static void p32x_vdp_write8(u32 a, u32 d)
         Pico32x.dirty_pal = 1;
       r[0] = (r[0] & P32XV_nPAL) | (d & 0xff);
       break;
+    case 0x03: // shift (for pp mode)
+      r[2 / 2] = d & 1;
+      break;
     case 0x05: // fill len
       r[4 / 2] = d & 0xff;
       break;
@@ -344,15 +386,15 @@ static void p32x_vdp_write8(u32 a, u32 d)
       Pico32x.pending_fb = d;
       // if we are blanking and FS bit is changing
       if (((r[0x0a/2] & P32XV_VBLK) || (r[0] & P32XV_Mx) == 0) && ((r[0x0a/2] ^ d) & P32XV_FS)) {
-        r[0x0a/2] ^= 1;
-	Pico32xSwapDRAM(d ^ 1);
+        r[0x0a/2] ^= P32XV_FS;
+        Pico32xSwapDRAM(d ^ 1);
         elprintf(EL_32X, "VDP FS: %d", r[0x0a/2] & P32XV_FS);
       }
       break;
   }
 }
 
-static void p32x_vdp_write16(u32 a, u32 d)
+static void p32x_vdp_write16(u32 a, u32 d, SH2 *sh2)
 {
   a &= 0x0e;
   if (a == 6) { // fill start
@@ -362,13 +404,19 @@ static void p32x_vdp_write16(u32 a, u32 d)
   if (a == 8) { // fill data
     u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
     int len = Pico32x.vdp_regs[4 / 2] + 1;
+    int len1 = len;
     a = Pico32x.vdp_regs[6 / 2];
-    while (len--) {
+    while (len1--) {
       dram[a] = d;
       a = (a & 0xff00) | ((a + 1) & 0xff);
     }
-    Pico32x.vdp_regs[6 / 2] = a;
-    Pico32x.vdp_regs[8 / 2] = d;
+    Pico32x.vdp_regs[0x06 / 2] = a;
+    Pico32x.vdp_regs[0x08 / 2] = d;
+    if (sh2 != NULL && len > 4) {
+      Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
+      // supposedly takes 3 bus/6 sh2 cycles? or 3 sh2 cycles?
+      p32x_event_schedule_sh2(sh2, P32X_EVENT_FILLEND, 3 + len);
+    }
     return;
   }
 
@@ -387,8 +435,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     case 0x00: // adapter/irq ctl
       return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
     case 0x04: // H count (often as comm too)
-      if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
-        ash2_end_run(8);
+      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
+      sh2s_sync_on_read(&sh2s[cpuid]);
       return Pico32x.sh2_regs[4 / 2];
     case 0x10: // DREQ len
       return r[a / 2];
@@ -399,13 +447,16 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     return r[a / 2];
   // comm port
   if ((a & 0x30) == 0x20) {
-    if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
-      ash2_end_run(8);
+    int comreg = 1 << (a & 0x0f) / 2;
+    if (Pico32x.comm_dirty_68k & comreg)
+      Pico32x.comm_dirty_68k &= ~comreg;
+    else
+      sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
+    sh2s_sync_on_read(&sh2s[cpuid]);
     return r[a / 2];
   }
   if ((a & 0x30) == 0x30) {
-    sh2_poll[cpuid].cnt = 0;
-    return p32x_pwm_read16(a);
+    return p32x_pwm_read16(a, sh2_cycles_done_m68k(&sh2s[cpuid]));
   }
 
   return 0;
@@ -414,29 +465,47 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
 static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
 {
   a &= 0xff;
+
+  sh2s[cpuid].poll_addr = 0;
+
   switch (a) {
     case 0: // FM
       Pico32x.regs[0] &= ~P32XS_FM;
       Pico32x.regs[0] |= (d << 8) & P32XS_FM;
       return;
-    case 1: // 
+    case 1: // HEN/irq masks
+      if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
+        elprintf(EL_ANOMALY|EL_32X, "HEN");
       Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
       Pico32x.sh2_regs[0] &= ~0x80;
       Pico32x.sh2_regs[0] |= d & 0x80;
-      p32x_update_irls();
+      if (d & 1)
+        p32x_pwm_schedule_sh2(&sh2s[cpuid]);
+      p32x_update_irls(&sh2s[cpuid]);
       return;
     case 5: // H count
-      Pico32x.sh2_regs[4 / 2] = d & 0xff;
-      p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+      d &= 0xff;
+      if (Pico32x.sh2_regs[4 / 2] != d) {
+        Pico32x.sh2_regs[4 / 2] = d;
+        p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+          sh2_cycles_done_m68k(&sh2s[cpuid]));
+        sh2_end_run(&sh2s[cpuid], 4);
+      }
       return;
   }
 
   if ((a & 0x30) == 0x20) {
     u8 *r8 = (u8 *)Pico32x.regs;
+    int comreg;
+    if (r8[a ^ 1] == d)
+      return;
+
     r8[a ^ 1] = d;
-    if (p32x_poll_undetect(&m68k_poll, 0))
-      SekSetStop(0);
-    p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+    p32x_m68k_poll_event(P32XF_68KCPOLL);
+    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    comreg = 1 << (a & 0x0f) / 2;
+    Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
 }
@@ -445,17 +514,25 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
 {
   a &= 0xfe;
 
+  sh2s[cpuid].poll_addr = 0;
+
   // comm
-  if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
+  if ((a & 0x30) == 0x20) {
+    int comreg;
+    if (Pico32x.regs[a / 2] == d)
+      return;
+
     Pico32x.regs[a / 2] = d;
-    if (p32x_poll_undetect(&m68k_poll, 0))
-      SekSetStop(0);
-    p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+    p32x_m68k_poll_event(P32XF_68KCPOLL);
+    p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
+      sh2_cycles_done_m68k(&sh2s[cpuid]));
+    comreg = 1 << (a & 0x0f) / 2;
+    Pico32x.comm_dirty_sh2 |= comreg;
     return;
   }
   // PWM
   else if ((a & 0x30) == 0x30) {
-    p32x_pwm_write16(a, d);
+    p32x_pwm_write16(a, d, sh2_cycles_done_m68k(&sh2s[cpuid]));
     return;
   }
 
@@ -470,7 +547,7 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
     case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
     case 0x1c:
       Pico32x.sh2irqs &= ~P32XI_PWM;
-      p32x_timers_do(0);
+      p32x_pwm_schedule_sh2(&sh2s[cpuid]);
       goto irls;
   }
 
@@ -478,138 +555,11 @@ static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
   return;
 
 irls:
-  p32x_update_irls();
-}
-
-// ------------------------------------------------------------------
-// SH2 internal peripherals
-// we keep them in little endian format
-static u32 sh2_peripheral_read8(u32 a, int id)
-{
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  u32 d;
-
-  a &= 0x1ff;
-  d = PREG8(r, a);
-
-  elprintf(EL_32X, "%csh2 peri r8  [%08x]       %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static u32 sh2_peripheral_read16(u32 a, int id)
-{
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  u32 d;
-
-  a &= 0x1ff;
-  d = r[(a / 2) ^ 1];
-
-  elprintf(EL_32X, "%csh2 peri r16 [%08x]     %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static u32 sh2_peripheral_read32(u32 a, int id)
-{
-  u32 d;
-  a &= 0x1fc;
-  d = Pico32xMem->sh2_peri_regs[id][a / 4];
-
-  elprintf(EL_32X, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
-  return d;
-}
-
-static void sh2_peripheral_write8(u32 a, u32 d, int id)
-{
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w8  [%08x]       %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1ff;
-  PREG8(r, a) = d;
-
-  // X-men SCI hack
-  if ((a == 2 &&  (d & 0x20)) || // transmiter enabled
-      (a == 4 && !(d & 0x80))) { // valid data in TDR
-    void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
-    if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
-      int level = PREG8(oregs, 0x60) >> 4;
-      int vector = PREG8(oregs, 0x63) & 0x7f;
-      elprintf(EL_32X, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
-      sh2_internal_irq(&sh2s[id ^ 1], level, vector);
-    }
-  }
-}
-
-static void sh2_peripheral_write16(u32 a, u32 d, int id)
-{
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w16 [%08x]     %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1ff;
-
-  // evil WDT
-  if (a == 0x80) {
-    if ((d & 0xff00) == 0xa500) { // WTCSR
-      PREG8(r, 0x80) = d;
-      p32x_timers_recalc();
-    }
-    if ((d & 0xff00) == 0x5a00) // WTCNT
-      PREG8(r, 0x81) = d;
-    return;
-  }
-
-  r[(a / 2) ^ 1] = d;
-}
-
-static void sh2_peripheral_write32(u32 a, u32 d, int id)
-{
-  u32 *r = Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32X, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
-
-  a &= 0x1fc;
-  r[a / 4] = d;
-
-  switch (a) {
-    // division unit (TODO: verify):
-    case 0x104: // DVDNT: divident L, starts divide
-      elprintf(EL_32X, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
-      if (r[0x100 / 4]) {
-        signed int divisor = r[0x100 / 4];
-                       r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
-        r[0x104 / 4] = r[0x11c / 4] = r[0x114 / 4] = (signed int)d / divisor;
-      }
-      break;
-    case 0x114:
-      elprintf(EL_32X, "%csh2 divide %08x%08x / %08x @%08x",
-        id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
-      if (r[0x100 / 4]) {
-        signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
-        signed int divisor = r[0x100 / 4];
-        // XXX: undocumented mirroring to 0x118,0x11c?
-        r[0x118 / 4] = r[0x110 / 4] = divident % divisor;
-        r[0x11c / 4] = r[0x114 / 4] = divident / divisor;
-      }
-      break;
-  }
-
-  if ((a == 0x1b0 || a == 0x18c) && (dmac0->chcr0 & 3) == 1 && (dmac0->dmaor & 1)) {
-    elprintf(EL_32X, "sh2 DMA %08x -> %08x, cnt %d, chcr %04x @%06x",
-      dmac0->sar0, dmac0->dar0, dmac0->tcr0, dmac0->chcr0, sh2_pc(id));
-    dmac0->tcr0 &= 0xffffff;
-
-    // HACK: assume 68k starts writing soon and end the timeslice
-    ash2_end_run(16);
-
-    // DREQ is only sent after first 4 words are written.
-    // we do multiple of 4 words to avoid messing up alignment
-    if (dmac0->sar0 == 0x20004012 && Pico32x.dmac_ptr && (Pico32x.dmac_ptr & 3) == 0) {
-      elprintf(EL_32X, "68k -> sh2 DMA");
-      dma_68k2sh2_do();
-    }
-  }
+  p32x_update_irls(&sh2s[cpuid]);
 }
 
 // ------------------------------------------------------------------
-// 32x handlers
+// 32x 68k handlers
 
 // after ADEN
 static u32 PicoRead8_32x_on(u32 a)
@@ -701,17 +651,19 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
     return;
   }
 
-  if ((a & 0xfff0) == 0x5180) { // a15180
-    p32x_vdp_write8(a, d);
-    return;
-  }
+  if (!(Pico32x.regs[0] & P32XS_FM)) {
+    if ((a & 0xfff0) == 0x5180) { // a15180
+      p32x_vdp_write8(a, d);
+      return;
+    }
 
-  // TODO: verify
-  if ((a & 0xfe00) == 0x5200) { // a15200
-    elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8  [%06x]   %02x @%06x", a, d & 0xff, SekPc);
-    ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
-    Pico32x.dirty_pal = 1;
-    return;
+    // TODO: verify
+    if ((a & 0xfe00) == 0x5200) { // a15200
+      elprintf(EL_32X|EL_ANOMALY, "m68k 32x PAL w8  [%06x]   %02x @%06x", a, d & 0xff, SekPc);
+      ((u8 *)Pico32xMem->pal)[(a & 0x1ff) ^ 1] = d;
+      Pico32x.dirty_pal = 1;
+      return;
+    }
   }
 
   elprintf(EL_UIO, "m68k unmapped w8  [%06x]   %02x @%06x", a, d & 0xff, SekPc);
@@ -720,7 +672,7 @@ static void PicoWrite8_32x_on(u32 a, u32 d)
 static void PicoWrite16_32x_on(u32 a, u32 d)
 {
   if ((a & 0xfc00) == 0x5000)
-    elprintf(EL_UIO, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
+    elprintf(EL_32X, "m68k 32x w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
 
   if ((a & 0xffc0) == 0x5100) { // a15100
     p32x_reg_write16(a, d);
@@ -732,15 +684,17 @@ static void PicoWrite16_32x_on(u32 a, u32 d)
     return;
   }
 
-  if ((a & 0xfff0) == 0x5180) { // a15180
-    p32x_vdp_write16(a, d);
-    return;
-  }
+  if (!(Pico32x.regs[0] & P32XS_FM)) {
+    if ((a & 0xfff0) == 0x5180) { // a15180
+      p32x_vdp_write16(a, d, NULL); // FIXME?
+      return;
+    }
 
-  if ((a & 0xfe00) == 0x5200) { // a15200
-    Pico32xMem->pal[(a & 0x1ff) / 2] = d;
-    Pico32x.dirty_pal = 1;
-    return;
+    if ((a & 0xfe00) == 0x5200) { // a15200
+      Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+      Pico32x.dirty_pal = 1;
+      return;
+    }
   }
 
   elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
@@ -844,6 +798,45 @@ void PicoWrite16_32x(u32 a, u32 d)
   elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
 }
 
+/* quirk: in both normal and overwrite areas only nonzero values go through */
+#define sh2_write8_dramN(n) \
+  if ((d & 0xff) != 0) { \
+    u8 *dram = (u8 *)Pico32xMem->dram[n]; \
+    dram[(a & 0x1ffff) ^ 1] = d; \
+  }
+
+static void m68k_write8_dram0_ow(u32 a, u32 d)
+{
+  sh2_write8_dramN(0);
+}
+
+static void m68k_write8_dram1_ow(u32 a, u32 d)
+{
+  sh2_write8_dramN(1);
+}
+
+#define sh2_write16_dramN(n, ret) \
+  u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
+  if (!(a & 0x20000)) { \
+    *pd = d; \
+    return ret; \
+  } \
+  /* overwrite */ \
+  if (!(d & 0xff00)) d |= *pd & 0xff00; \
+  if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
+  *pd = d; \
+  return ret
+
+static void m68k_write16_dram0_ow(u32 a, u32 d)
+{
+  sh2_write16_dramN(0,);
+}
+
+static void m68k_write16_dram1_ow(u32 a, u32 d)
+{
+  sh2_write16_dramN(1,);
+}
+
 // -----------------------------------------------------------------
 
 // hint vector is writeable
@@ -867,14 +860,6 @@ static void PicoWrite16_hint(u32 a, u32 d)
   elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
 }
 
-void Pico32xSwapDRAM(int b)
-{
-  cpu68k_map_set(m68k_read8_map,   0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-  cpu68k_map_set(m68k_read16_map,  0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-  cpu68k_map_set(m68k_write8_map,  0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-  cpu68k_map_set(m68k_write16_map, 0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
-}
-
 static void bank_switch(int b)
 {
   unsigned int rs, bank;
@@ -894,60 +879,54 @@ static void bank_switch(int b)
   cpu68k_map_set(m68k_read16_map,  0x900000, 0x900000 + rs - 1, Pico.rom + bank, 0);
 
   elprintf(EL_32X, "bank %06x-%06x -> %06x", 0x900000, 0x900000 + rs - 1, bank);
+
+#ifdef EMU_F68K
+  // setup FAME fetchmap
+  for (rs = 0x90; rs < 0xa0; rs++)
+    PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom + bank - 0x900000;
+#endif
 }
 
 // -----------------------------------------------------------------
 //                              SH2  
 // -----------------------------------------------------------------
 
-u32 p32x_sh2_read8(u32 a, int id)
+// read8
+static u32 sh2_read8_unmapped(u32 a, int id)
 {
-  u32 d = 0;
-
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
-    return Pico32xMem->sh2_rom_m[a ^ 1];
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
-    return Pico32xMem->sh2_rom_s[a ^ 1];
-
-  if ((a & 0xdffc0000) == 0x06000000)
-    return Pico32xMem->sdram[(a & 0x3ffff) ^ 1];
-
-  if ((a & 0xdfc00000) == 0x02000000)
-    if ((a & 0x003fffff) < Pico.romsize)
-      return Pico.rom[(a & 0x3fffff) ^ 1];
-
-  if ((a & ~0xfff) == 0xc0000000)
-    return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+  elprintf(EL_UIO, "%csh2 unmapped r8  [%08x]       %02x @%06x",
+    id ? 's' : 'm', a, 0, sh2_pc(id));
+  return 0;
+}
 
-  if ((a & 0xdffc0000) == 0x04000000) {
-    /* XXX: overwrite readable as normal? */
-    u8 *dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
-    return dram[(a & 0x1ffff) ^ 1];
-  }
+static u32 sh2_read8_cs0(u32 a, int id)
+{
+  u32 d = 0;
 
-  if ((a & 0xdfffff00) == 0x4000) {
+  // 0x3ff00 is veridied
+  if ((a & 0x3ff00) == 0x4000) {
     d = p32x_sh2reg_read16(a, id);
     goto out_16to8;
   }
 
-  if ((a & 0xdfffff00) == 0x4100) {
+  if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
-      ash2_end_run(8);
+    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
     goto out_16to8;
   }
 
-  if ((a & 0xdfffff00) == 0x4200) {
+  // TODO: mirroring?
+  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+    return Pico32xMem->sh2_rom_m[a ^ 1];
+  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+    return Pico32xMem->sh2_rom_s[a ^ 1];
+
+  if ((a & 0x3fe00) == 0x4200) {
     d = Pico32xMem->pal[(a & 0x1ff) / 2];
     goto out_16to8;
   }
 
-  if ((a & 0xfffffe00) == 0xfffffe00)
-    return sh2_peripheral_read8(a, id);
-
-  elprintf(EL_UIO, "%csh2 unmapped r8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
-  return d;
+  return sh2_read8_unmapped(a, id);
 
 out_16to8:
   if (a & 1)
@@ -960,53 +939,47 @@ out_16to8:
   return d;
 }
 
-u32 p32x_sh2_read16(u32 a, int id)
+static u32 sh2_read8_da(u32 a, int id)
 {
-  u32 d = 0;
-
-  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
-    return *(u16 *)(Pico32xMem->sh2_rom_m + a);
-  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
-    return *(u16 *)(Pico32xMem->sh2_rom_s + a);
-
-  if ((a & 0xdffc0000) == 0x06000000)
-    return ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2];
-
-  if ((a & 0xdfc00000) == 0x02000000)
-    if ((a & 0x003fffff) < Pico.romsize)
-      return ((u16 *)Pico.rom)[(a & 0x3fffff) / 2];
+  return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+}
 
-  if ((a & ~0xfff) == 0xc0000000)
-    return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+// read16
+static u32 sh2_read16_unmapped(u32 a, int id)
+{
+  elprintf(EL_UIO, "%csh2 unmapped r16 [%08x]     %04x @%06x",
+    id ? 's' : 'm', a, 0, sh2_pc(id));
+  return 0;
+}
 
-  if ((a & 0xdffe0000) == 0x04000000)
-    return Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
+static u32 sh2_read16_cs0(u32 a, int id)
+{
+  u32 d = 0;
 
-  if ((a & 0xdfffff00) == 0x4000) {
+  if ((a & 0x3ff00) == 0x4000) {
     d = p32x_sh2reg_read16(a, id);
     if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
       return d;
     goto out;
   }
 
-  if ((a & 0xdfffff00) == 0x4100) {
+  if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
-      ash2_end_run(8);
+    sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
     goto out;
   }
 
-  if ((a & 0xdfffff00) == 0x4200) {
+  if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+    return *(u16 *)(Pico32xMem->sh2_rom_m + a);
+  if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+    return *(u16 *)(Pico32xMem->sh2_rom_s + a);
+
+  if ((a & 0x3fe00) == 0x4200) {
     d = Pico32xMem->pal[(a & 0x1ff) / 2];
     goto out;
   }
 
-  if ((a & 0xfffffe00) == 0xfffffe00)
-    return sh2_peripheral_read16(a, id);
-
-  elprintf(EL_UIO, "%csh2 unmapped r16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d, sh2_pc(id));
-  return d;
+  return sh2_read16_unmapped(a, id);
 
 out:
   elprintf(EL_32X, "%csh2 r16 [%08x]     %04x @%06x",
@@ -1014,129 +987,250 @@ out:
   return d;
 }
 
-u32 p32x_sh2_read32(u32 a, int id)
+static u32 sh2_read16_da(u32 a, int id)
 {
-  if ((a & 0xfffffe00) == 0xfffffe00)
-    return sh2_peripheral_read32(a, id);
+  return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+}
 
-//  elprintf(EL_UIO, "sh2 r32 [%08x] %08x @%06x", a, d, ash2_pc());
-  return (p32x_sh2_read16(a, id) << 16) | p32x_sh2_read16(a + 2, id);
+static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+{
+  return 0;
 }
 
-void p32x_sh2_write8(u32 a, u32 d, int id)
+// write8
+static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
 {
-  if ((a & 0xdffffc00) == 0x4000)
-    elprintf(EL_32X, "%csh2 w8  [%08x]       %02x @%06x",
-      id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+  elprintf(EL_UIO, "%csh2 unmapped w8  [%08x]       %02x @%06x",
+    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+  return 0;
+}
 
-  if ((a & 0xdffc0000) == 0x06000000) {
-    Pico32xMem->sdram[(a & 0x3ffff) ^ 1] = d;
-    return;
-  }
+static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
+{
+  elprintf(EL_32X, "%csh2 w8  [%08x]       %02x @%06x",
+    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
 
-  if ((a & 0xdffc0000) == 0x04000000) {
-    u8 *dram;
-    if (!(a & 0x20000) || d) {
-      dram = (u8 *)Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
-      dram[(a & 0x1ffff) ^ 1] = d;
+  if (Pico32x.regs[0] & P32XS_FM) {
+    if ((a & 0x3ff00) == 0x4100) {
+      sh2s[id].poll_addr = 0;
+      p32x_vdp_write8(a, d);
+      return 0;
     }
-    return;
   }
 
-  if ((a & ~0xfff) == 0xc0000000) {
-    Pico32xMem->data_array[id][(a & 0xfff) ^ 1] = d;
-    return;
+  if ((a & 0x3ff00) == 0x4000) {
+    p32x_sh2reg_write8(a, d, id);
+    return 1;
   }
 
-  if ((a & 0xdfffff00) == 0x4100) {
-    p32x_vdp_write8(a, d);
-    return;
-  }
+  return sh2_write8_unmapped(a, d, id);
+}
 
-  if ((a & 0xdfffff00) == 0x4000) {
-    p32x_sh2reg_write8(a, d, id);
-    return;
-  }
+static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
+{
+  sh2_write8_dramN(0);
+  return 0;
+}
 
-  if ((a & 0xfffffe00) == 0xfffffe00) {
-    sh2_peripheral_write8(a, d, id);
-    return;
-  }
+static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
+{
+  sh2_write8_dramN(1);
+  return 0;
+}
 
-  elprintf(EL_UIO, "%csh2 unmapped w8  [%08x]       %02x @%06x",
-    id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
+{
+  u32 a1 = a & 0x3ffff;
+#ifdef DRC_SH2
+  int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
+  if (t)
+    sh2_drc_wcheck_ram(a, t, id);
+#endif
+  Pico32xMem->sdram[a1 ^ 1] = d;
+  return 0;
+}
+
+static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
+{
+  u32 a1 = a & 0xfff;
+#ifdef DRC_SH2
+  int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
+  if (t)
+    sh2_drc_wcheck_da(a, t, id);
+#endif
+  Pico32xMem->data_array[id][a1 ^ 1] = d;
+  return 0;
+}
+
+// write16
+static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
+{
+  elprintf(EL_UIO, "%csh2 unmapped w16 [%08x]     %04x @%06x",
+    id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+  return 0;
 }
 
-void p32x_sh2_write16(u32 a, u32 d, int id)
+static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
 {
-  if ((a & 0xdffffc00) == 0x4000 && ((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
+  if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
     elprintf(EL_32X, "%csh2 w16 [%08x]     %04x @%06x",
       id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
 
-  // ignore "Associative purge space"
-  if ((a & 0xf8000000) == 0x40000000)
-    return;
+  if (Pico32x.regs[0] & P32XS_FM) {
+    if ((a & 0x3ff00) == 0x4100) {
+      sh2s[id].poll_addr = 0;
+      p32x_vdp_write16(a, d, &sh2s[id]);
+      return 0;
+    }
 
-  if ((a & 0xdffc0000) == 0x06000000) {
-    ((u16 *)Pico32xMem->sdram)[(a & 0x3ffff) / 2] = d;
-    return;
+    if ((a & 0x3fe00) == 0x4200) {
+      Pico32xMem->pal[(a & 0x1ff) / 2] = d;
+      Pico32x.dirty_pal = 1;
+      return 0;
+    }
   }
 
-  if ((a & ~0xfff) == 0xc0000000) {
-    ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2] = d;
-    return;
+  if ((a & 0x3ff00) == 0x4000) {
+    p32x_sh2reg_write16(a, d, id);
+    return 1;
   }
 
-  if ((a & 0xdffc0000) == 0x04000000) {
-    u16 *pd = &Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1][(a & 0x1ffff) / 2];
-    if (!(a & 0x20000)) {
-      *pd = d;
-      return;
-    }
-    // overwrite
-    if (!(d & 0xff00)) d |= *pd & 0xff00;
-    if (!(d & 0x00ff)) d |= *pd & 0x00ff;
-    *pd = d;
-    return;
-  }
+  return sh2_write16_unmapped(a, d, id);
+}
 
-  if ((a & 0xdfffff00) == 0x4100) {
-    sh2_poll[id].cnt = 0; // for poll before VDP accesses
-    p32x_vdp_write16(a, d);
-    return;
-  }
+static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
+{
+  sh2_write16_dramN(0, 0);
+}
 
-  if ((a & 0xdffffe00) == 0x4200) {
-    Pico32xMem->pal[(a & 0x1ff) / 2] = d;
-    Pico32x.dirty_pal = 1;
-    return;
-  }
+static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
+{
+  sh2_write16_dramN(1, 0);
+}
 
-  if ((a & 0xdfffff00) == 0x4000) {
-    p32x_sh2reg_write16(a, d, id);
-    return;
-  }
+static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
+{
+  u32 a1 = a & 0x3ffff;
+#ifdef DRC_SH2
+  int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
+  if (t)
+    sh2_drc_wcheck_ram(a, t, id);
+#endif
+  ((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
+  return 0;
+}
 
-  if ((a & 0xfffffe00) == 0xfffffe00) {
-    sh2_peripheral_write16(a, d, id);
-    return;
+static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
+{
+  u32 a1 = a & 0xfff;
+#ifdef DRC_SH2
+  int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
+  if (t)
+    sh2_drc_wcheck_da(a, t, id);
+#endif
+  ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
+  return 0;
+}
+
+
+typedef u32 (sh2_read_handler)(u32 a, int id);
+typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
+
+#define SH2MAP_ADDR2OFFS_R(a) \
+  ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
+
+#define SH2MAP_ADDR2OFFS_W(a) \
+  ((u32)(a) >> SH2_WRITE_SHIFT)
+
+u32 REGPARM(2) p32x_sh2_read8(u32 a, SH2 *sh2)
+{
+  const sh2_memmap *sh2_map = sh2->read8_map;
+  uptr p;
+
+  sh2_map += SH2MAP_ADDR2OFFS_R(a);
+  p = sh2_map->addr;
+  if (map_flag_set(p))
+    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+  else
+    return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
+}
+
+u32 REGPARM(2) p32x_sh2_read16(u32 a, SH2 *sh2)
+{
+  const sh2_memmap *sh2_map = sh2->read16_map;
+  uptr p;
+
+  sh2_map += SH2MAP_ADDR2OFFS_R(a);
+  p = sh2_map->addr;
+  if (map_flag_set(p))
+    return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+  else
+    return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+}
+
+u32 REGPARM(2) p32x_sh2_read32(u32 a, SH2 *sh2)
+{
+  const sh2_memmap *sh2_map = sh2->read16_map;
+  sh2_read_handler *handler;
+  u32 offs;
+  uptr p;
+
+  offs = SH2MAP_ADDR2OFFS_R(a);
+  sh2_map += offs;
+  p = sh2_map->addr;
+  if (!map_flag_set(p)) {
+    // XXX: maybe 32bit access instead with ror?
+    u16 *pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
+    return (pd[0] << 16) | pd[1];
   }
 
-  elprintf(EL_UIO, "%csh2 unmapped w16 [%08x]     %04x @%06x",
-    id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+  if (offs == 0x1f)
+    return sh2_peripheral_read32(a, sh2->is_slave);
+
+  handler = (sh2_read_handler *)(p << 1);
+  return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
 }
 
-void p32x_sh2_write32(u32 a, u32 d, int id)
+// return nonzero if write potentially causes an interrupt (used by drc)
+int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
 {
-  if ((a & 0xfffffe00) == 0xfffffe00) {
-    sh2_peripheral_write32(a, d, id);
-    return;
+  const void **sh2_wmap = sh2->write8_tab;
+  sh2_write_handler *wh;
+
+  wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+  return wh(a, d, sh2->is_slave);
+}
+
+int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+{
+  const void **sh2_wmap = sh2->write16_tab;
+  sh2_write_handler *wh;
+
+  wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
+  return wh(a, d, sh2->is_slave);
+}
+
+int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+{
+  const void **sh2_wmap = sh2->write16_tab;
+  sh2_write_handler *handler;
+  u32 offs;
+
+  offs = SH2MAP_ADDR2OFFS_W(a);
+
+  if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
+    sh2_peripheral_write32(a, d, sh2->is_slave);
+    return 0;
   }
 
-  p32x_sh2_write16(a, d >> 16, id);
-  p32x_sh2_write16(a + 2, d, id);
+  handler = sh2_wmap[offs];
+  handler(a, d >> 16, sh2->is_slave);
+  handler(a + 2, d, sh2->is_slave);
+  return 0;
 }
 
+// -----------------------------------------------------------------
+
 static const u16 msh2_code[] = {
   // trap instructions
   0xaffe, // bra <self>
@@ -1177,7 +1271,7 @@ static const u16 ssh2_code[] = {
   0x2200, 0x03e4  // slave start pointer in ROM
 };
 
-#define HWSWAP(x) (((x) << 16) | ((x) >> 16))
+#define HWSWAP(x) (((u16)(x) << 16) | ((x) >> 16))
 static void get_bios(void)
 {
   u16 *ps;
@@ -1187,7 +1281,7 @@ static void get_bios(void)
   // M68K ROM
   if (p32x_bios_g != NULL) {
     elprintf(EL_STATUS|EL_32X, "32x: using supplied 68k BIOS");
-    Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, 0x100);
+    Byteswap(Pico32xMem->m68k_rom, p32x_bios_g, sizeof(Pico32xMem->m68k_rom));
   }
   else {
     // generate 68k ROM
@@ -1209,7 +1303,9 @@ static void get_bios(void)
 #endif
   }
   // fill remaining m68k_rom page with game ROM
-  memcpy(Pico32xMem->m68k_rom + 0x100, Pico.rom + 0x100, sizeof(Pico32xMem->m68k_rom) - 0x100);
+  memcpy(Pico32xMem->m68k_rom_bank + sizeof(Pico32xMem->m68k_rom),
+    Pico.rom + sizeof(Pico32xMem->m68k_rom),
+    sizeof(Pico32xMem->m68k_rom_bank) - sizeof(Pico32xMem->m68k_rom));
 
   // MSH2
   if (p32x_bios_m != NULL) {
@@ -1254,18 +1350,43 @@ static void get_bios(void)
   }
 }
 
+#define MAP_MEMORY(m) ((uptr)(m) >> 1)
+#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
+
+static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
+// for writes we are using handlers only
+static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
+
+void Pico32xSwapDRAM(int b)
+{
+  cpu68k_map_set(m68k_read8_map,   0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_read16_map,  0x840000, 0x85ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_read8_map,   0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_read16_map,  0x860000, 0x87ffff, Pico32xMem->dram[b], 0);
+  cpu68k_map_set(m68k_write8_map,  0x840000, 0x87ffff,
+                 b ? m68k_write8_dram1_ow : m68k_write8_dram0_ow, 1);
+  cpu68k_map_set(m68k_write16_map, 0x840000, 0x87ffff,
+                 b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
+
+  // SH2
+  sh2_read8_map[2].addr   = sh2_read8_map[6].addr   =
+  sh2_read16_map[2].addr  = sh2_read16_map[6].addr  = MAP_MEMORY(Pico32xMem->dram[b]);
+
+  sh2_write8_map[0x04/2]  = sh2_write8_map[0x24/2]  = b ? sh2_write8_dram1 : sh2_write8_dram0;
+  sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
+}
+
 void PicoMemSetup32x(void)
 {
   unsigned int rs;
+  int i;
 
-  Pico32xMem = calloc(1, sizeof(*Pico32xMem));
+  Pico32xMem = plat_mmap(0x06000000, sizeof(*Pico32xMem), 0, 0);
   if (Pico32xMem == NULL) {
     elprintf(EL_STATUS, "OOM");
     return;
   }
 
-  dmac0 = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-
   get_bios();
 
   // cartridge area becomes unmapped
@@ -1274,21 +1395,24 @@ void PicoMemSetup32x(void)
   // m68k_map_unmap(0x000000, 0x3fffff);
 
   // MD ROM area
-  rs = sizeof(Pico32xMem->m68k_rom);
-  cpu68k_map_set(m68k_read8_map,   0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
-  cpu68k_map_set(m68k_read16_map,  0x000000, rs - 1, Pico32xMem->m68k_rom, 0);
+  rs = sizeof(Pico32xMem->m68k_rom_bank);
+  cpu68k_map_set(m68k_read8_map,   0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
+  cpu68k_map_set(m68k_read16_map,  0x000000, rs - 1, Pico32xMem->m68k_rom_bank, 0);
   cpu68k_map_set(m68k_write8_map,  0x000000, rs - 1, PicoWrite8_hint, 1); // TODO verify
   cpu68k_map_set(m68k_write16_map, 0x000000, rs - 1, PicoWrite16_hint, 1);
 
-  // DRAM area
-  Pico32xSwapDRAM(1);
-
   // 32X ROM (unbanked, XXX: consider mirroring?)
   rs = (Pico.romsize + M68K_BANK_MASK) & ~M68K_BANK_MASK;
   if (rs > 0x80000)
     rs = 0x80000;
   cpu68k_map_set(m68k_read8_map,   0x880000, 0x880000 + rs - 1, Pico.rom, 0);
   cpu68k_map_set(m68k_read16_map,  0x880000, 0x880000 + rs - 1, Pico.rom, 0);
+#ifdef EMU_F68K
+  // setup FAME fetchmap
+  PicoCpuFM68k.Fetch[0] = (unsigned long)Pico32xMem->m68k_rom;
+  for (rs = 0x88; rs < 0x90; rs++)
+    PicoCpuFM68k.Fetch[rs] = (unsigned long)Pico.rom - 0x880000;
+#endif
 
   // 32X ROM (banked)
   bank_switch(0);
@@ -1299,12 +1423,82 @@ void PicoMemSetup32x(void)
   cpu68k_map_set(m68k_write8_map,  0xa10000, 0xa1ffff, PicoWrite8_32x_on, 1);
   cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_32x_on, 1);
 
-  // setup poll detector
-  m68k_poll.flag = P32XF_68KPOLL;
-  m68k_poll.cyc_max = 64;
-  sh2_poll[0].flag = P32XF_MSH2POLL;
-  sh2_poll[0].cyc_max = 21;
-  sh2_poll[1].flag = P32XF_SSH2POLL;
-  sh2_poll[1].cyc_max = 16;
+  // SH2 maps: A31,A30,A29,CS1,CS0
+  // all unmapped by default
+  for (i = 0; i < ARRAY_SIZE(sh2_read8_map); i++) {
+    sh2_read8_map[i].addr   = MAP_HANDLER(sh2_read8_unmapped);
+    sh2_read16_map[i].addr  = MAP_HANDLER(sh2_read16_unmapped);
+  }
+
+  for (i = 0; i < ARRAY_SIZE(sh2_write8_map); i++) {
+    sh2_write8_map[i]       = sh2_write8_unmapped;
+    sh2_write16_map[i]      = sh2_write16_unmapped;
+  }
+
+  // "purge area"
+  for (i = 0x40; i <= 0x5f; i++) {
+    sh2_write8_map[i >> 1]  =
+    sh2_write16_map[i >> 1] = sh2_write_ignore;
+  }
+
+  // CS0
+  sh2_read8_map[0].addr   = sh2_read8_map[4].addr   = MAP_HANDLER(sh2_read8_cs0);
+  sh2_read16_map[0].addr  = sh2_read16_map[4].addr  = MAP_HANDLER(sh2_read16_cs0);
+  sh2_write8_map[0x00/2]  = sh2_write8_map[0x20/2]  = sh2_write8_cs0;
+  sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
+  // CS1 - ROM
+  sh2_read8_map[1].addr   = sh2_read8_map[5].addr   =
+  sh2_read16_map[1].addr  = sh2_read16_map[5].addr  = MAP_MEMORY(Pico.rom);
+  sh2_read8_map[1].mask   = sh2_read8_map[5].mask   =
+  sh2_read16_map[1].mask  = sh2_read16_map[5].mask  = 0x3fffff; // FIXME
+  // CS2 - DRAM - done by Pico32xSwapDRAM()
+  sh2_read8_map[2].mask   = sh2_read8_map[6].mask   =
+  sh2_read16_map[2].mask  = sh2_read16_map[6].mask  = 0x01ffff;
+  // CS3 - SDRAM
+  sh2_read8_map[3].addr   = sh2_read8_map[7].addr   =
+  sh2_read16_map[3].addr  = sh2_read16_map[7].addr  = MAP_MEMORY(Pico32xMem->sdram);
+  sh2_write8_map[0x06/2]  = sh2_write8_map[0x26/2]  = sh2_write8_sdram;
+  sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
+  sh2_read8_map[3].mask   = sh2_read8_map[7].mask   =
+  sh2_read16_map[3].mask  = sh2_read16_map[7].mask  = 0x03ffff;
+  // SH2 data array
+  sh2_read8_map[0x18].addr   = MAP_HANDLER(sh2_read8_da);
+  sh2_read16_map[0x18].addr  = MAP_HANDLER(sh2_read16_da);
+  sh2_write8_map[0xc0/2]     = sh2_write8_da;
+  sh2_write16_map[0xc0/2]    = sh2_write16_da;
+  // SH2 IO
+  sh2_read8_map[0x1f].addr   = MAP_HANDLER(sh2_peripheral_read8);
+  sh2_read16_map[0x1f].addr  = MAP_HANDLER(sh2_peripheral_read16);
+  sh2_write8_map[0xff/2]     = sh2_peripheral_write8;
+  sh2_write16_map[0xff/2]    = sh2_peripheral_write16;
+
+  // map DRAM area, both 68k and SH2
+  Pico32xSwapDRAM(1);
+
+  msh2.read8_map   = ssh2.read8_map   = sh2_read8_map;
+  msh2.read16_map  = ssh2.read16_map  = sh2_read16_map;
+  msh2.write8_tab  = ssh2.write8_tab  = (const void **)(void *)sh2_write8_map;
+  msh2.write16_tab = ssh2.write16_tab = (const void **)(void *)sh2_write16_map;
+
+  sh2_drc_mem_setup(&msh2);
+  sh2_drc_mem_setup(&ssh2);
+}
+
+void Pico32xMemStateLoaded(void)
+{
+  bank_switch(Pico32x.regs[4 / 2]);
+  Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
+  memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
+  Pico32x.dirty_pal = 1;
+
+  Pico32x.emu_flags &= ~(P32XF_68KCPOLL | P32XF_68KVPOLL);
+  memset(&m68k_poll, 0, sizeof(m68k_poll));
+  msh2.state = 0;
+  msh2.poll_addr = msh2.poll_cycles = msh2.poll_cnt = 0;
+  ssh2.state = 0;
+  ssh2.poll_addr = ssh2.poll_cycles = ssh2.poll_cnt = 0;
+
+  sh2_drc_flush_all();
 }
 
+// vim:shiftwidth=2:ts=2:expandtab