X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2Fmemory.c;h=b0f70070e18e1e208fe94bb8f91e3ed7d6d9bad1;hb=4943816bcded6f39324d6a832e6d0e687d74b8b0;hp=531a286aa1cb0cd28f52cd6144a2fee6f5379008;hpb=a8fd6e376175c06e2423d0914359c761829d6e93;p=picodrive.git

diff --git a/pico/32x/memory.c b/pico/32x/memory.c
index 531a286..b0f7007 100644
--- a/pico/32x/memory.c
+++ b/pico/32x/memory.c
@@ -1,13 +1,10 @@
 /*
  * PicoDrive
- * (C) notaz, 2009,2010
+ * (C) notaz, 2009,2010,2013
  *
  * This work is licensed under the terms of MAME license.
  * See COPYING file in the top-level directory.
  *
- * SH2 addr lines:
- * iii. .cc. ..xx *   // Internal, Cs, x
- *
  * Register map:
  * a15100 F....... R.....EA  F.....AC N...VHMP 4000 // Fm Ren nrEs Aden Cart heN V H cMd Pwm
  * a15102 ........ ......SM  ?                 4002 // intS intM
@@ -25,6 +22,21 @@
  * a1511e ?                  ?                 401e
  * a15120            (16 bytes comm)           2020
  * a15130                 (PWM)                2030
+ *
+ * SH2 addr lines:
+ * iii. .cc. ..xx *   // Internal, Cs, x
+ *
+ * sh2 map, wait/bus cycles (from docs):
+ *                             r    w
+ * rom      0000000-0003fff    1    -
+ * sys reg  0004000-00040ff    1    1
+ * vdp reg  0004100-00041ff    5    5
+ * vdp pal  0004200-00043ff    5    5
+ * rom      2000000-23fffff     6-15
+ * dram/fb  4000000-401ffff 5-12  1-3
+ * fb ovr   4020000-403ffff
+ * sdram    6000000-603ffff   12    2  (cycles)
+ * d.a.    c0000000-?
  */
 #include "../pico_int.h"
 #include "../memory.h"
@@ -109,8 +121,8 @@ void p32x_poll_event(int cpu_mask, int is_vdp)
 
 // SH2 faking
 //#define FAKE_SH2
-int p32x_csum_faked;
 #ifdef FAKE_SH2
+static int p32x_csum_faked;
 static const u16 comm_fakevals[] = {
   0x4d5f, 0x4f4b, // M_OK
   0x535f, 0x4f4b, // S_OK
@@ -442,8 +454,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     case 0x00: // adapter/irq ctl
       return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
     case 0x04: // H count (often as comm too)
-      if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
-        ash2_end_run(8);
+      if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
+        ash2_end_run(&sh2s[cpuid], 8);
       return Pico32x.sh2_regs[4 / 2];
     case 0x10: // DREQ len
       return r[a / 2];
@@ -457,8 +469,8 @@ static u32 p32x_sh2reg_read16(u32 a, int cpuid)
     int comreg = 1 << (a & 0x0f) / 2;
     if (Pico32x.comm_dirty_68k & comreg)
       Pico32x.comm_dirty_68k &= ~comreg;
-    else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
-      ash2_end_run(8);
+    else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(&sh2s[cpuid]), 0))
+      ash2_end_run(&sh2s[cpuid], 8);
     return r[a / 2];
   }
   if ((a & 0x30) == 0x30) {
@@ -683,7 +695,7 @@ static void sh2_peripheral_write32(u32 a, u32 d, int id)
     dmac0->tcr0 &= 0xffffff;
 
     // HACK: assume 68k starts writing soon and end the timeslice
-    ash2_end_run(16);
+    ash2_end_run(&sh2s[id], 16);
 
     // DREQ is only sent after first 4 words are written.
     // we do multiple of 4 words to avoid messing up alignment
@@ -1004,8 +1016,8 @@ static u32 sh2_read8_cs0(u32 a, int id)
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
-      ash2_end_run(8);
+    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
+      ash2_end_run(&sh2s[id], 8);
     goto out_16to8;
   }
 
@@ -1059,8 +1071,8 @@ static u32 sh2_read16_cs0(u32 a, int id)
 
   if ((a & 0x3ff00) == 0x4100) {
     d = p32x_vdp_read16(a);
-    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(), 1))
-      ash2_end_run(8);
+    if (p32x_poll_detect(&sh2_poll[id], a, ash2_cycles_done(&sh2s[id]), 1))
+      ash2_end_run(&sh2s[id], 8);
     goto out;
   }
 
@@ -1241,11 +1253,6 @@ static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
 }
 
 
-typedef struct {
-  uptr addr; // stores (membase >> 1) or ((handler >> 1) | (1<<31))
-  u32 mask;
-} sh2_memmap;
-
 typedef u32 (sh2_read_handler)(u32 a, int id);
 typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
 
@@ -1605,14 +1612,12 @@ void PicoMemSetup32x(void)
 #endif
 }
 
-void Pico32xStateLoaded(void)
+void Pico32xMemStateLoaded(void)
 {
   bank_switch(Pico32x.regs[4 / 2]);
   Pico32xSwapDRAM((Pico32x.vdp_regs[0x0a / 2] & P32XV_FS) ^ P32XV_FS);
-  p32x_poll_event(3, 0);
-  Pico32x.dirty_pal = 1;
   memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
-  p32x_timers_recalc();
+  Pico32x.dirty_pal = 1;
 #ifdef DRC_SH2
   sh2_drc_flush_all();
 #endif