X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2F32x%2Fsh2soc.c;h=04d33748185bd83c7a043a1075758ef506491921;hb=ae214f1c37e5b02b6413040649a40f8ba3874e1b;hp=ab4ac529bb9b0406f894ccb4a3c1439df61e0f07;hpb=045a4c528a71e5513acc2cfb8a77e31efcad5d87;p=picodrive.git

diff --git a/pico/32x/sh2soc.c b/pico/32x/sh2soc.c
index ab4ac52..04d3374 100644
--- a/pico/32x/sh2soc.c
+++ b/pico/32x/sh2soc.c
@@ -59,7 +59,7 @@ struct dmac {
 
 static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
 {
-  char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
+  char *regs = (void *)sh2->peri_regs;
   struct dmac *dmac = (void *)(regs + 0x180);
   int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
   int vector = (chan == &dmac->chan[0]) ?
@@ -73,7 +73,7 @@ static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
 {
   chan->chcr |= DMA_TE; // DMA has ended normally
 
-  p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
+  p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDone());
   if (chan->chcr & DMA_IE)
     dmac_te_irq(sh2, chan);
 }
@@ -128,7 +128,7 @@ static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
 // DMA trigger by SH2 register write
 static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
 {
-  elprintf(EL_32XP, "sh2 DMA %08x->%08x, cnt %d, chcr %04x @%06x",
+  elprintf_sh2(sh2, EL_32XP, "DMA %08x->%08x, cnt %d, chcr %04x @%06x",
     chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
   chan->tcr &= 0xffffff;
 
@@ -142,7 +142,7 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
 
   // DREQ0 is only sent after first 4 words are written.
   // we do multiple of 4 words to avoid messing up alignment
-  if (chan->sar == 0x20004012) {
+  if ((chan->sar & ~0x20000000) == 0x00004012) {
     if (Pico32x.dmac0_fifo_ptr && (Pico32x.dmac0_fifo_ptr & 3) == 0) {
       elprintf(EL_32XP, "68k -> sh2 DMA");
       p32x_dreq0_trigger();
@@ -150,6 +150,10 @@ static void dmac_trigger(SH2 *sh2, struct dma_chan *chan)
     return;
   }
 
+  // DREQ1
+  if ((chan->dar & 0xc7fffff0) == 0x00004030)
+    return;
+
   elprintf(EL_32XP|EL_ANOMALY, "unhandled DMA: "
     "%08x->%08x, cnt %d, chcr %04x @%06x",
     chan->sar, chan->dar, chan->tcr, chan->chcr, sh2->pc);
@@ -167,7 +171,7 @@ void p32x_timers_recalc(void)
 
   // SH2 timer step
   for (i = 0; i < 2; i++) {
-    tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7;
+    tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
     // Sclk cycles per timer tick
     if (tmp)
       cycles = 0x20 << tmp;
@@ -186,7 +190,7 @@ void p32x_timers_do(unsigned int m68k_slice)
 
   // WDT timers
   for (i = 0; i < 2; i++) {
-    void *pregs = Pico32xMem->sh2_peri_regs[i];
+    void *pregs = sh2s[i].peri_regs;
     if (PREG8(pregs, 0x80) & 0x20) { // TME
       timer_cycles[i] += cycles;
       cnt = PREG8(pregs, 0x81);
@@ -207,71 +211,136 @@ void p32x_timers_do(unsigned int m68k_slice)
   }
 }
 
+void sh2_peripheral_reset(SH2 *sh2)
+{
+  memset(sh2->peri_regs, 0, sizeof(sh2->peri_regs)); // ?
+  PREG8(sh2->peri_regs, 0x001) = 0xff; // SCI BRR
+  PREG8(sh2->peri_regs, 0x003) = 0xff; // SCI TDR
+  PREG8(sh2->peri_regs, 0x004) = 0x84; // SCI SSR
+  PREG8(sh2->peri_regs, 0x011) = 0x01; // TIER
+  PREG8(sh2->peri_regs, 0x017) = 0xe0; // TOCR
+}
+
 // ------------------------------------------------------------------
 // SH2 internal peripheral memhandlers
 // we keep them in little endian format
 
-u32 sh2_peripheral_read8(u32 a, int id)
+u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
 {
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+  u8 *r = (void *)sh2->peri_regs;
   u32 d;
 
   a &= 0x1ff;
   d = PREG8(r, a);
 
-  elprintf(EL_32XP, "%csh2 peri r8  [%08x]       %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf_sh2(sh2, EL_32XP, "peri r8  [%08x]       %02x @%06x",
+    a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-u32 sh2_peripheral_read16(u32 a, int id)
+u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
 {
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+  u16 *r = (void *)sh2->peri_regs;
   u32 d;
 
   a &= 0x1ff;
   d = r[(a / 2) ^ 1];
 
-  elprintf(EL_32XP, "%csh2 peri r16 [%08x]     %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf_sh2(sh2, EL_32XP, "peri r16 [%08x]     %04x @%06x",
+    a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-u32 sh2_peripheral_read32(u32 a, int id)
+u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
 {
   u32 d;
   a &= 0x1fc;
-  d = Pico32xMem->sh2_peri_regs[id][a / 4];
+  d = sh2->peri_regs[a / 4];
 
-  elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+  elprintf_sh2(sh2, EL_32XP, "peri r32 [%08x] %08x @%06x",
+    a | ~0x1ff, d, sh2_pc(sh2));
   return d;
 }
 
-int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
+static void sci_trigger(SH2 *sh2, u8 *r)
 {
-  u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w8  [%08x]       %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u8 *oregs;
+
+  if (!(PREG8(r, 2) & 0x20))
+    return; // transmitter not enabled
+  if ((PREG8(r, 4) & 0x80)) // TDRE - TransmitDataR Empty
+    return;
+
+  oregs = (u8 *)sh2->other_sh2->peri_regs;
+  if (!(PREG8(oregs, 2) & 0x10))
+    return; // receiver not enabled
+
+  PREG8(oregs, 5) = PREG8(r, 3); // other.RDR = this.TDR
+  PREG8(r, 4) |= 0x80;     // TDRE - TDR empty
+  PREG8(oregs, 4) |= 0x40; // RDRF - RDR Full
+
+  // might need to delay these a bit..
+  if (PREG8(r, 2) & 0x80) { // TIE - tx irq enabled
+    int level = PREG8(oregs, 0x60) >> 4;
+    int vector = PREG8(oregs, 0x64) & 0x7f;
+    elprintf_sh2(sh2, EL_32XP, "SCI tx irq (%d, %d)",
+      level, vector);
+    sh2_internal_irq(sh2, level, vector);
+  }
+  // TODO: TEIE
+  if (PREG8(oregs, 2) & 0x40) { // RIE - rx irq enabled
+    int level = PREG8(oregs, 0x60) >> 4;
+    int vector = PREG8(oregs, 0x63) & 0x7f;
+    elprintf_sh2(sh2->other_sh2, EL_32XP, "SCI rx irq (%d, %d)",
+      level, vector);
+    sh2_internal_irq(sh2->other_sh2, level, vector);
+  }
+}
+
+void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
+{
+  u8 *r = (void *)sh2->peri_regs;
+  u8 old;
+
+  elprintf_sh2(sh2, EL_32XP, "peri w8  [%08x]       %02x @%06x",
+    a, d, sh2_pc(sh2));
 
   a &= 0x1ff;
-  PREG8(r, a) = d;
+  old = PREG8(r, a);
 
-  // X-men SCI hack
-  if ((a == 2 &&  (d & 0x20)) || // transmiter enabled
-      (a == 4 && !(d & 0x80))) { // valid data in TDR
-    void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
-    if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
-      int level = PREG8(oregs, 0x60) >> 4;
-      int vector = PREG8(oregs, 0x63) & 0x7f;
-      elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
-      sh2_internal_irq(&sh2s[id ^ 1], level, vector);
-      return 1;
+  switch (a) {
+  case 0x002: // SCR - serial control
+    if (!(PREG8(r, a) & 0x20) && (d & 0x20)) { // TE being set
+      PREG8(r, a) = d;
+      sci_trigger(sh2, r);
     }
+    break;
+  case 0x003: // TDR - transmit data
+    break;
+  case 0x004: // SSR - serial status
+    d = (old & (d | 0x06)) | (d & 1);
+    PREG8(r, a) = d;
+    sci_trigger(sh2, r);
+    return;
+  case 0x005: // RDR - receive data
+    break;
+  case 0x010: // TIER
+    if (d & 0x8e)
+      elprintf(EL_32XP|EL_ANOMALY, "TIER: %02x", d);
+    d = (d & 0x8e) | 1;
+    break;
+  case 0x017: // TOCR
+    d |= 0xe0;
+    break;
   }
-  return 0;
+  PREG8(r, a) = d;
 }
 
-int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
+void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
 {
-  u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w16 [%08x]     %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u16 *r = (void *)sh2->peri_regs;
+  elprintf_sh2(sh2, EL_32XP, "peri w16 [%08x]     %04x @%06x",
+    a, d, sh2_pc(sh2));
 
   a &= 0x1ff;
 
@@ -283,25 +352,29 @@ int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
     }
     if ((d & 0xff00) == 0x5a00) // WTCNT
       PREG8(r, 0x81) = d;
-    return 0;
+    return;
   }
 
   r[(a / 2) ^ 1] = d;
-  return 0;
 }
 
-void sh2_peripheral_write32(u32 a, u32 d, int id)
+void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
 {
-  u32 *r = Pico32xMem->sh2_peri_regs[id];
-  elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+  u32 *r = sh2->peri_regs;
+  u32 old;
+
+  elprintf_sh2(sh2, EL_32XP, "peri w32 [%08x] %08x @%06x",
+    a, d, sh2_pc(sh2));
 
   a &= 0x1fc;
+  old = r[a / 4];
   r[a / 4] = d;
 
   switch (a) {
     // division unit (TODO: verify):
     case 0x104: // DVDNT: divident L, starts divide
-      elprintf(EL_32XP, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
+      elprintf_sh2(sh2, EL_32XP, "divide %08x / %08x",
+        d, r[0x100 / 4]);
       if (r[0x100 / 4]) {
         signed int divisor = r[0x100 / 4];
                        r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
@@ -311,8 +384,8 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
         r[0x110 / 4] = r[0x114 / 4] = r[0x118 / 4] = r[0x11c / 4] = 0; // ?
       break;
     case 0x114:
-      elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
-        id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
+      elprintf_sh2(sh2, EL_32XP, "divide %08x%08x / %08x @%08x",
+        r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
       if (r[0x100 / 4]) {
         signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
         signed int divisor = r[0x100 / 4];
@@ -322,7 +395,7 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
         r[0x11c / 4] = r[0x114 / 4] = divident;
         divident >>= 31;
         if ((unsigned long long)divident + 1 > 1) {
-          //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
+          //elprintf_sh2(sh2, EL_32XP, "divide overflow! @%08x", sh2_pc(sh2));
           r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
         }
       }
@@ -333,43 +406,44 @@ void sh2_peripheral_write32(u32 a, u32 d, int id)
 
   // perhaps starting a DMA?
   if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
-    struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
+    struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
+    if (a == 0x1b0 && !((old ^ d) & d & DMA_DME))
+      return;
     if (!(dmac->dmaor & DMA_DME))
       return;
 
     if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[0]);
+      dmac_trigger(sh2, &dmac->chan[0]);
     if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
-      dmac_trigger(&sh2s[id], &dmac->chan[1]);
+      dmac_trigger(sh2, &dmac->chan[1]);
   }
 }
 
 /* 32X specific */
 static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
 {
-  unsigned short *dreqlen = &Pico32x.regs[0x10 / 2];
+  unsigned short dreqlen = Pico32x.regs[0x10 / 2];
   int i;
 
   // debug/sanity checks
-  if (chan->tcr != *dreqlen)
-    elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0 and len differ: %d != %d",
-      chan->tcr, *dreqlen);
+  if (chan->tcr < dreqlen || chan->tcr > dreqlen + 4)
+    elprintf(EL_32XP|EL_ANOMALY, "dreq0: tcr0/len inconsistent: %d/%d",
+      chan->tcr, dreqlen);
   // note: DACK is not connected, single addr mode should not be used
   if ((chan->chcr & 0x3f08) != 0x0400)
     elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad control: %04x", chan->chcr);
-  if (chan->sar != 0x20004012)
-    elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x\n", chan->sar);
+  if ((chan->sar & ~0x20000000) != 0x00004012)
+    elprintf(EL_32XP|EL_ANOMALY, "dreq0: bad sar?: %08x", chan->sar);
 
   // HACK: assume bus is busy and SH2 is halted
   sh2->state |= SH2_STATE_SLEEP;
 
   for (i = 0; i < Pico32x.dmac0_fifo_ptr && chan->tcr > 0; i++) {
-    elprintf(EL_32XP, "dmaw [%08x] %04x, left %d",
-      chan->dar, Pico32x.dmac_fifo[i], *dreqlen);
+    elprintf_sh2(sh2, EL_32XP, "dreq0 [%08x] %04x, dreq_len %d",
+      chan->dar, Pico32x.dmac_fifo[i], dreqlen);
     p32x_sh2_write16(chan->dar, Pico32x.dmac_fifo[i], sh2);
     chan->dar += 2;
     chan->tcr--;
-    (*dreqlen)--;
   }
 
   if (Pico32x.dmac0_fifo_ptr != i)
@@ -378,8 +452,6 @@ static void dreq0_do(SH2 *sh2, struct dma_chan *chan)
   Pico32x.dmac0_fifo_ptr -= i;
 
   Pico32x.regs[6 / 2] &= ~P32XS_FULL;
-  if (*dreqlen == 0)
-    Pico32x.regs[6 / 2] &= ~P32XS_68S; // transfer complete
   if (chan->tcr == 0)
     dmac_transfer_complete(sh2, chan);
   else
@@ -401,8 +473,8 @@ static void dreq1_do(SH2 *sh2, struct dma_chan *chan)
 
 void p32x_dreq0_trigger(void)
 {
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+  struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+  struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
 
   elprintf(EL_32XP, "dreq0_trigger");
   if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
@@ -415,8 +487,8 @@ void p32x_dreq0_trigger(void)
 
 void p32x_dreq1_trigger(void)
 {
-  struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
-  struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+  struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+  struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
   int hit = 0;
 
   elprintf(EL_32XP, "dreq1_trigger");
@@ -429,8 +501,19 @@ void p32x_dreq1_trigger(void)
     hit = 1;
   }
 
-  if (!hit)
-    elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
+  // debug
+#if (EL_LOGMASK & (EL_32XP|EL_ANOMALY))
+  {
+    static int miss_count;
+    if (!hit) {
+      if (++miss_count == 4)
+        elprintf(EL_32XP|EL_ANOMALY, "dreq1: nobody cared");
+    }
+    else
+      miss_count = 0;
+  }
+#endif
+  (void)hit;
 }
 
 // vim:shiftwidth=2:ts=2:expandtab