X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2Fmemory_arm.S;fp=pico%2Fmemory_arm.s;h=87846d6cebd52c4911bc665b493b1b57836b2d55;hb=88fd63ad10faa746ef9d7ad7d98a72e51fe2aa86;hp=f6d7f79d04d2fcb9ccfcffc861ee7c18289b6d72;hpb=e64886365da9e882b54e06ab683ee4db60171e32;p=picodrive.git diff --git a/pico/memory_arm.s b/pico/memory_arm.S similarity index 73% rename from pico/memory_arm.s rename to pico/memory_arm.S index f6d7f79..87846d6 100644 --- a/pico/memory_arm.s +++ b/pico/memory_arm.S @@ -6,6 +6,8 @@ * See COPYING file in the top-level directory. */ +#include "pico_int_o32.h" + .equ SRR_MAPPED, (1 << 0) .equ SRR_READONLY, (1 << 1) .equ SRF_EEPROM, (1 << 1) @@ -21,35 +23,32 @@ .global PicoWrite8_io .global PicoWrite16_io -PicoRead8_sram: @ u32 a, u32 d - ldr r2, =(SRam) - ldr r3, =(Pico+0x22200) - ldr r1, [r2, #8] @ SRam.end +PicoRead8_sram: @ u32 a + ldr r3, =Pico + ldr r1, [r3, #OFS_Pico_sv_end] cmp r0, r1 bgt m_read8_nosram - ldr r1, [r2, #4] @ SRam.start - cmp r0, r1 + ldr r2, [r3, #OFS_Pico_sv_start] + cmp r0, r2 blt m_read8_nosram - ldrb r1, [r3, #0x11] @ Pico.m.sram_reg + ldrb r1, [r3, #OFS_Pico_m_sram_reg] tst r1, #SRR_MAPPED beq m_read8_nosram - ldr r1, [r2, #0x0c] + ldr r1, [r3, #OFS_Pico_sv_flags] tst r1, #SRF_EEPROM bne m_read8_eeprom - ldr r1, [r2, #4] @ SRam.start - ldr r2, [r2] @ SRam.data - sub r0, r0, r1 - add r0, r0, r2 - ldrb r0, [r0] + ldr r1, [r3, #OFS_Pico_sv_data] + sub r0, r0, r2 + ldrb r0, [r0, r1] bx lr m_read8_nosram: - ldr r1, [r3, #4] @ romsize + ldr r1, [r3, #OFS_Pico_romsize] cmp r0, r1 movgt r0, #0 bxgt lr @ bad location @ XXX: banking unfriendly - ldr r1, [r3] + ldr r1, [r3, #OFS_Pico_rom] eor r0, r0, #1 ldrb r0, [r1, r0] bx lr @@ -63,7 +62,7 @@ m_read8_eeprom: bx lr -PicoRead8_io: @ u32 a, u32 d +PicoRead8_io: @ u32 a bic r2, r0, #0x001f @ most commonly we get i/o port read, cmp r2, #0xa10000 @ so check for it first beq io_ports_read @@ -73,11 +72,11 @@ m_read8_not_io: cmp r2, #0x1000 bne m_read8_not_brq - ldr r3, =(Pico+0x22200) + ldr r3, =Pico mov r1, r0 - ldr r0, [r3, #8] @ Pico.m.rotate + ldr r0, [r3, #OFS_Pico_m_rotate] add r0, r0, #1 - strb r0, [r3, #8] + strb r0, [r3, #OFS_Pico_m_rotate] eor r0, r0, r0, lsl #6 tst r1, #1 @@ -87,8 +86,8 @@ m_read8_not_io: cmp r2, #0x1100 bxne lr @ not busreq - ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run - ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset + ldrb r1, [r3, #OFS_Pico_m_z80Run] + ldrb r2, [r3, #OFS_Pico_m_z80_reset] orr r0, r0, r1 orr r0, r0, r2 bx lr @@ -104,36 +103,33 @@ m_read8_not_brq: @ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ PicoRead16_sram: @ u32 a, u32 d - ldr r2, =(SRam) - ldr r3, =(Pico+0x22200) - ldr r1, [r2, #8] @ SRam.end + ldr r3, =Pico + ldr r1, [r3, #OFS_Pico_sv_end] cmp r0, r1 bgt m_read16_nosram - ldr r1, [r2, #4] @ SRam.start - cmp r0, r1 + ldr r2, [r3, #OFS_Pico_sv_start] + cmp r0, r2 blt m_read16_nosram - ldrb r1, [r3, #0x11] @ Pico.m.sram_reg + ldrb r1, [r3, #OFS_Pico_m_sram_reg] tst r1, #SRR_MAPPED beq m_read16_nosram - ldr r1, [r2, #0x0c] + ldr r1, [r3, #OFS_Pico_sv_flags] tst r1, #SRF_EEPROM bne EEPROM_read - ldr r1, [r2, #4] @ SRam.start - ldr r2, [r2] @ SRam.data - sub r0, r0, r1 - add r0, r0, r2 - ldrb r1, [r0], #1 - ldrb r0, [r0] + ldr r1, [r3, #OFS_Pico_sv_data] + sub r0, r0, r2 + ldrb r1, [r0, r1]! + ldrb r0, [r0, #1] orr r0, r0, r1, lsl #8 bx lr m_read16_nosram: - ldr r1, [r3, #4] @ romsize + ldr r1, [r3, #OFS_Pico_romsize] cmp r0, r1 movgt r0, #0 bxgt lr @ bad location @ XXX: banking unfriendly - ldr r1, [r3] + ldr r1, [r3, #OFS_Pico_rom] ldrh r0, [r1, r0] bx lr @@ -152,19 +148,19 @@ m_read16_not_io: cmp r2, #0x1000 bne m_read16_not_brq - ldr r3, =(Pico+0x22200) + ldr r3, =Pico and r2, r0, #0xff00 - ldr r0, [r3, #8] @ Pico.m.rotate + ldr r0, [r3, #OFS_Pico_m_rotate] add r0, r0, #1 - strb r0, [r3, #8] + strb r0, [r3, #OFS_Pico_m_rotate] eor r0, r0, r0, lsl #5 eor r0, r0, r0, lsl #8 bic r0, r0, #0x100 @ bit8 defined in this area cmp r2, #0x1100 bxne lr @ not busreq - ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run - ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset + ldrb r1, [r3, #OFS_Pico_m_z80Run] + ldrb r2, [r3, #OFS_Pico_m_z80_reset] orr r0, r0, r1, lsl #8 orr r0, r0, r2, lsl #8 bx lr @@ -202,12 +198,12 @@ m_write8_not_z80ctl: eor r2, r2, #0x003000 eors r2, r2, #0x0000f1 bne m_write8_not_sreg - ldr r3, =(Pico+0x22200) - ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg + ldr r3, =Pico + ldrb r2, [r3, #OFS_Pico_m_sram_reg] and r1, r1, #(SRR_MAPPED|SRR_READONLY) bic r2, r2, #(SRR_MAPPED|SRR_READONLY) orr r2, r2, r1 - strb r2, [r3, #(8+9)] + strb r2, [r3, #OFS_Pico_m_sram_reg] bx lr m_write8_not_sreg: @@ -239,12 +235,12 @@ m_write16_not_z80ctl: eor r2, r2, #0x003000 eors r2, r2, #0x0000f0 bne m_write16_not_sreg - ldr r3, =(Pico+0x22200) - ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg + ldr r3, =Pico + ldrb r2, [r3, #OFS_Pico_m_sram_reg] and r1, r1, #(SRR_MAPPED|SRR_READONLY) bic r2, r2, #(SRR_MAPPED|SRR_READONLY) orr r2, r2, r1 - strb r2, [r3, #(8+9)] + strb r2, [r3, #OFS_Pico_m_sram_reg] bx lr m_write16_not_sreg: