X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=pico%2Fpico_int.h;h=cb6ae7c9a1dc5648afcdfbcccda00faea4184623;hb=f4bb5d6b2c96a94317c4edb7805eb6d6ed8589ef;hp=cb12bc10c1fdbf84cf9eaf8560735aa15532e45b;hpb=45f2f245f51ef0c0d37df3c998595c132bfcaffa;p=picodrive.git

diff --git a/pico/pico_int.h b/pico/pico_int.h
index cb12bc1..cb6ae7c 100644
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -1,7 +1,7 @@
 // Pico Library - Internal Header File
 
 // (c) Copyright 2004 Dave, All rights reserved.
-// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.
+// (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.
 // Free for non-commercial use.
 
 // For commercial use, separate licencing terms must be obtained.
@@ -45,12 +45,15 @@ extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
 #define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after
 #define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)
 #define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)
+#define SekDar(x) PicoCpuCM68k.d[x]
+#define SekSr     CycloneGetSr(&PicoCpuCM68k)
 #define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }
 #define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }
 #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)
 #define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))
 
 #define SekInterrupt(i) PicoCpuCM68k.irq=i
+#define SekIrqLevel     PicoCpuCM68k.irq
 
 #ifdef EMU_M68K
 #define EMU_CORE_DEBUG
@@ -69,6 +72,8 @@ extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
 #define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after
 #define SekPc     fm68k_get_pc(&PicoCpuFM68k)
 #define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)
+#define SekDar(x) PicoCpuFM68k.dreg[x].D
+#define SekSr     PicoCpuFM68k.sr
 #define SekSetStop(x) { \
 	PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \
 	if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \
@@ -81,6 +86,7 @@ extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
 #define SekShouldInterrupt fm68k_would_interrupt()
 
 #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq
+#define SekIrqLevel       PicoCpuFM68k.interrupts[0]
 
 #ifdef EMU_M68K
 #define EMU_CORE_DEBUG
@@ -100,6 +106,8 @@ extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
 #define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after
 #define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)
 #define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)
+#define SekDar(x) PicoCpuMM68k.dar[x]
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)
 #define SekSetStop(x) { \
 	if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \
 	else PicoCpuMM68k.stopped=0; \
@@ -117,6 +125,7 @@ extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
 	m68k_set_irq(irq); \
 	m68k_set_context(oldcontext); \
 }
+#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)
 
 #endif
 #endif // EMU_M68K
@@ -226,6 +235,37 @@ extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];
 typedef unsigned char (z80_read_f)(unsigned short a);
 typedef void (z80_write_f)(unsigned int a, unsigned char data);
 
+// ----------------------- SH2 CPU -----------------------
+
+#include "cpu/sh2/sh2.h"
+
+extern SH2 sh2s[2];
+#define msh2 sh2s[0]
+#define ssh2 sh2s[1]
+
+#ifndef DRC_SH2
+# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after
+# define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)
+#else
+# define ash2_end_run(after) { \
+   if ((sh2->sr >> 12) > (after)) \
+     { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \
+}
+# define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))
+#endif
+
+//#define sh2_pc(c)     (c) ? ssh2.ppc : msh2.ppc
+#define sh2_pc(c)     (c) ? ssh2.pc : msh2.pc
+#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]
+#define sh2_gbr(c)    (c) ? ssh2.gbr : msh2.gbr
+#define sh2_vbr(c)    (c) ? ssh2.vbr : msh2.vbr
+#define sh2_sr(c)   (((c) ? ssh2.sr : msh2.sr) & 0xfff)
+
+#define sh2_set_gbr(c, v) \
+  { if (c) ssh2.gbr = v; else msh2.gbr = v; }
+#define sh2_set_vbr(c, v) \
+  { if (c) ssh2.vbr = v; else msh2.vbr = v; }
+
 // ---------------------------------------------------------
 
 // main oscillator clock which controls timing
@@ -257,15 +297,15 @@ struct PicoMisc
   unsigned char pal;           // 08 1=PAL 0=NTSC
   unsigned char sram_reg;      // 09 SRAM reg. See SRR_* below
   unsigned short z80_bank68k;  // 0a
-  unsigned short z80_lastaddr; // this is for Z80 faking
-  unsigned char  pad0;
-  unsigned char  z80_reset;    // z80 reset held
+  unsigned short pad0;
+  unsigned char  pad1;
+  unsigned char  z80_reset;    // 0f z80 reset held
   unsigned char  padDelay[2];  // 10 gamepad phase time outs, so we count a delay
   unsigned short eeprom_addr;  // EEPROM address register
   unsigned char  eeprom_cycle; // EEPROM cycle number
   unsigned char  eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
   unsigned char  eeprom_status;
-  unsigned char  pad1;
+  unsigned char  pad2;
   unsigned short dma_xfers;    // 18
   unsigned char  eeprom_wb[2]; // EEPROM latch/write buffer
   unsigned int  frame_count;   // 1c for movies and idle det
@@ -385,8 +425,91 @@ typedef struct
 	Rot_Comp rot_comp;
 } mcd_state;
 
+// XXX: this will need to be reworked for cart+cd support.
 #define Pico_mcd ((mcd_state *)Pico.rom)
 
+// 32X
+#define P32XS_FM    (1<<15)
+#define P32XS_REN   (1<< 7)
+#define P32XS_nRES  (1<< 1)
+#define P32XS_ADEN  (1<< 0)
+#define P32XS2_ADEN (1<< 9)
+#define P32XS_FULL  (1<< 7) // DREQ FIFO full
+#define P32XS_68S   (1<< 2)
+#define P32XS_DMA   (1<< 1)
+#define P32XS_RV    (1<< 0)
+
+#define P32XV_nPAL  (1<<15) // VDP
+#define P32XV_PRI   (1<< 7)
+#define P32XV_Mx    (3<< 0) // display mode mask
+
+#define P32XV_VBLK  (1<<15)
+#define P32XV_HBLK  (1<<14)
+#define P32XV_PEN   (1<<13)
+#define P32XV_nFEN  (1<< 1)
+#define P32XV_FS    (1<< 0)
+
+#define P32XP_FULL  (1<<15) // PWM
+#define P32XP_EMPTY (1<<14)
+
+#define P32XF_68KPOLL   (1 << 0)
+#define P32XF_MSH2POLL  (1 << 1)
+#define P32XF_SSH2POLL  (1 << 2)
+#define P32XF_68KVPOLL  (1 << 3)
+#define P32XF_MSH2VPOLL (1 << 4)
+#define P32XF_SSH2VPOLL (1 << 5)
+
+#define P32XI_VRES (1 << 14/2) // IRL/2
+#define P32XI_VINT (1 << 12/2)
+#define P32XI_HINT (1 << 10/2)
+#define P32XI_CMD  (1 <<  8/2)
+#define P32XI_PWM  (1 <<  6/2)
+
+// peripheral reg access
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]
+
+// real one is 4*2, but we use more because we don't lockstep
+#define DMAC_FIFO_LEN (4*4)
+#define PWM_BUFF_LEN 1024 // in one channel samples
+
+#define SH2_DRCBLK_RAM_SHIFT 1
+#define SH2_DRCBLK_DA_SHIFT  1
+
+struct Pico32x
+{
+  unsigned short regs[0x20];
+  unsigned short vdp_regs[0x10];
+  unsigned short sh2_regs[3];
+  unsigned char pending_fb;
+  unsigned char dirty_pal;
+  unsigned int emu_flags;
+  unsigned char sh2irq_mask[2];
+  unsigned char sh2irqi[2];      // individual
+  unsigned int sh2irqs;          // common irqs
+  unsigned short dmac_fifo[DMAC_FIFO_LEN];
+  unsigned int dmac_ptr;
+  unsigned int pwm_irq_sample_cnt;
+};
+
+struct Pico32xMem
+{
+  unsigned char  sdram[0x40000];
+#ifdef DRC_SH2
+  unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];
+#endif
+  unsigned short dram[2][0x20000/2];    // AKA fb
+  unsigned char  m68k_rom[0x10000];     // 0x100; using M68K_BANK_SIZE
+  unsigned char  data_array[2][0x1000]; // cache in SH2s (can be used as RAM)
+#ifdef DRC_SH2
+  unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];
+#endif
+  unsigned char  sh2_rom_m[0x800];
+  unsigned char  sh2_rom_s[0x400];
+  unsigned short pal[0x100];
+  unsigned short pal_native[0x100];     // converted to native (for renderer)
+  unsigned int   sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s
+  signed short   pwm[2*PWM_BUFF_LEN];   // PWM buffer for current frame
+};
 
 // area.c
 PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);
@@ -417,6 +540,7 @@ extern areaseek *areaSeek;
 extern areaclose *areaClose;
 
 // cart.c
+void Byteswap(void *dst, const void *src, int len);
 extern void (*PicoCartMemSetup)(void);
 extern void (*PicoCartUnloadHook)(void);
 
@@ -427,7 +551,7 @@ int CM_compareRun(int cyc, int is_sub);
 PICO_INTERNAL void PicoFrameStart(void);
 void PicoDrawSync(int to, int blank_last_line);
 void BackFill(int reg7, int sh);
-void FinalizeLineRGB555(int sh);
+void FinalizeLineRGB555(int sh, int line);
 extern int DrawScanline;
 #define MAX_LINE_SPRITES 29
 extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];
@@ -442,8 +566,6 @@ void PicoDoHighPal555M4(void);
 void PicoDrawSetColorFormatMode4(int which);
 
 // memory.c
-PICO_INTERNAL void PicoInitPc(unsigned int pc);
-PICO_INTERNAL unsigned int PicoCheckPc(unsigned int pc);
 PICO_INTERNAL void PicoMemSetup(void);
 unsigned int PicoRead8_io(unsigned int a);
 unsigned int PicoRead16_io(unsigned int a);
@@ -455,14 +577,14 @@ PICO_INTERNAL void PicoMemSetupPico(void);
 
 // cd/memory.c
 PICO_INTERNAL void PicoMemSetupCD(void);
-PICO_INTERNAL_ASM void PicoMemRemapCD(int r3);
-PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);
+void PicoMemStateLoaded(void);
 
 // pico.c
 extern struct Pico Pico;
 extern struct PicoSRAM SRam;
 extern int PicoPadInt[2];
 extern int emustatus;
+extern int scanlines_total;
 extern void (*PicoResetHook)(void);
 extern void (*PicoLineHook)(void);
 PICO_INTERNAL int  CheckDMA(void);
@@ -576,12 +698,48 @@ void PicoMemSetupMS(void);
 void PicoFrameMS(void);
 void PicoFrameDrawOnlyMS(void);
 
+// 32x/32x.c
+extern struct Pico32x Pico32x;
+void Pico32xInit(void);
+void PicoPower32x(void);
+void PicoReset32x(void);
+void Pico32xStartup(void);
+void PicoUnload32x(void);
+void PicoFrame32x(void);
+void p32x_update_irls(void);
+void p32x_reset_sh2s(void);
+
+// 32x/memory.c
+struct Pico32xMem *Pico32xMem;
+unsigned int PicoRead8_32x(unsigned int a);
+unsigned int PicoRead16_32x(unsigned int a);
+void PicoWrite8_32x(unsigned int a, unsigned int d);
+void PicoWrite16_32x(unsigned int a, unsigned int d);
+void PicoMemSetup32x(void);
+void Pico32xSwapDRAM(int b);
+void p32x_poll_event(int cpu_mask, int is_vdp);
+
+// 32x/draw.c
+void FinalizeLine32xRGB555(int sh, int line);
+
+// 32x/pwm.c
+unsigned int p32x_pwm_read16(unsigned int a);
+void p32x_pwm_write16(unsigned int a, unsigned int d);
+void p32x_pwm_update(int *buf32, int length, int stereo);
+void p32x_timers_do(int new_line);
+void p32x_timers_recalc(void);
+extern int pwm_frame_smp_cnt;
+
 /* avoid dependency on newer glibc */
 static __inline int isspace_(int c)
 {
 	return (0x09 <= c && c <= 0x0d) || c == ' ';
 }
 
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
+#endif
+
 // emulation event logging
 #ifndef EL_LOGMASK
 #define EL_LOGMASK 0
@@ -606,6 +764,8 @@ static __inline int isspace_(int c)
 #define EL_IDLE    0x00010000 /* idle loop det. */
 #define EL_CDREGS  0x00020000 /* MCD: register access */
 #define EL_CDREG3  0x00040000 /* MCD: register 3 only */
+#define EL_32X     0x00080000
+#define EL_PWM     0x00100000 /* 32X PWM stuff (LOTS of output) */
 
 #define EL_STATUS  0x40000000 /* status messages */
 #define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
@@ -635,6 +795,12 @@ extern void lprintf(const char *fmt, ...);
 #define MEMH_FUNC
 #endif
 
+#ifdef __GNUC__
+#define NOINLINE __attribute__((noinline))
+#else
+#define NOINLINE
+#endif
+
 #ifdef __cplusplus
 } // End of extern "C"
 #endif