X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=plugins%2Fgpulib%2Fgpu.c;h=b23f8a88f6decfa2e63e7c11f3ee9bc1bd3dad25;hb=0b4038f8edd327a3a9a2fbdefbc25ece921bc2ab;hp=d67df03c39a4e5d89d74f34f99b4e5b445ae6004;hpb=31d997216cc3ed116125a344a44d2c813d322fc1;p=pcsx_rearmed.git

diff --git a/plugins/gpulib/gpu.c b/plugins/gpulib/gpu.c
index d67df03c..b23f8a88 100644
--- a/plugins/gpulib/gpu.c
+++ b/plugins/gpulib/gpu.c
@@ -9,6 +9,7 @@
  */
 
 #include <stdio.h>
+#include <stdlib.h>
 #include <string.h>
 #include "gpu.h"
 
@@ -23,13 +24,8 @@
 #define noinline
 #endif
 
-#define gpu_log(fmt, ...) \
-  printf("%d:%03d: " fmt, *gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__)
-
 //#define log_io gpu_log
 #define log_io(...)
-//#define log_anomaly gpu_log
-#define log_anomaly(...)
 
 struct psx_gpu gpu;
 
@@ -56,33 +52,96 @@ static noinline void do_reset(void)
   memset(gpu.regs, 0, sizeof(gpu.regs));
   for (i = 0; i < sizeof(gpu.ex_regs) / sizeof(gpu.ex_regs[0]); i++)
     gpu.ex_regs[i] = (0xe0 + i) << 24;
-  gpu.status.reg = 0x14802000;
+  gpu.status = 0x14802000;
   gpu.gp0 = 0;
   gpu.regs[3] = 1;
   gpu.screen.hres = gpu.screen.w = 256;
   gpu.screen.vres = gpu.screen.h = 240;
+  gpu.screen.x = gpu.screen.y = 0;
+  renderer_notify_res_change();
 }
 
 static noinline void update_width(void)
 {
+  static const short hres_all[8] = { 256, 368, 320, 368, 512, 368, 640, 368 };
+  static const uint8_t hdivs[8] = { 10, 7, 8, 7, 5, 7, 4, 7 };
+  uint8_t hdiv = hdivs[(gpu.status >> 16) & 7];
+  int hres = hres_all[(gpu.status >> 16) & 7];
+  int pal = gpu.status & PSX_GPU_STATUS_PAL;
   int sw = gpu.screen.x2 - gpu.screen.x1;
-  if (sw <= 0 || sw >= 2560)
-    // full width
-    gpu.screen.w = gpu.screen.hres;
-  else
-    gpu.screen.w = sw * gpu.screen.hres / 2560;
+  int x = 0, x_auto;
+  if (sw <= 0)
+    /* nothing displayed? */;
+  else {
+    int s = pal ? 656 : 608; // or 600? pal is just a guess
+    x = (gpu.screen.x1 - s) / hdiv;
+    x = (x + 1) & ~1;   // blitter limitation
+    sw /= hdiv;
+    sw = (sw + 2) & ~3; // according to nocash
+    switch (gpu.state.screen_centering_type) {
+    case 1:
+      break;
+    case 2:
+      x = gpu.state.screen_centering_x;
+      break;
+    default:
+      // correct if slightly miscentered
+      x_auto = (hres - sw) / 2 & ~3;
+      if ((uint32_t)x_auto <= 8u && abs(x) < 24)
+        x = x_auto;
+    }
+    if (x + sw > hres)
+      sw = hres - x;
+    // .x range check is done in vout_update()
+  }
+  // reduce the unpleasant right border that a few games have
+  if (gpu.state.screen_centering_type == 0
+      && x <= 4 && hres - (x + sw) >= 4)
+    hres -= 4;
+  gpu.screen.x = x;
+  gpu.screen.w = sw;
+  gpu.screen.hres = hres;
+  gpu.state.dims_changed = 1;
+  //printf("xx %d %d -> %2d, %d / %d\n",
+  //  gpu.screen.x1, gpu.screen.x2, x, sw, hres);
 }
 
 static noinline void update_height(void)
 {
-  // TODO: emulate this properly..
+  int pal = gpu.status & PSX_GPU_STATUS_PAL;
+  int dheight = gpu.status & PSX_GPU_STATUS_DHEIGHT;
+  int y = gpu.screen.y1 - (pal ? 39 : 16); // 39 for spyro
   int sh = gpu.screen.y2 - gpu.screen.y1;
-  if (gpu.status.dheight)
-    sh *= 2;
-  if (sh <= 0 || sh > gpu.screen.vres)
-    sh = gpu.screen.vres;
-
+  int center_tol = 16;
+  int vres = 240;
+
+  if (pal && (sh > 240 || gpu.screen.vres == 256))
+    vres = 256;
+  if (dheight)
+    y *= 2, sh *= 2, vres *= 2, center_tol *= 2;
+  if (sh <= 0)
+    /* nothing displayed? */;
+  else {
+    switch (gpu.state.screen_centering_type) {
+    case 1:
+      break;
+    case 2:
+      y = gpu.state.screen_centering_y;
+      break;
+    default:
+      // correct if slightly miscentered
+      if ((uint32_t)(vres - sh) <= 1 && abs(y) <= center_tol)
+        y = 0;
+    }
+    if (y + sh > vres)
+      sh = vres - y;
+  }
+  gpu.screen.y = y;
   gpu.screen.h = sh;
+  gpu.screen.vres = vres;
+  gpu.state.dims_changed = 1;
+  //printf("yy %d %d -> %d, %d / %d\n",
+  //  gpu.screen.y1, gpu.screen.y2, y, sh, vres);
 }
 
 static noinline void decide_frameskip(void)
@@ -114,9 +173,9 @@ static noinline int decide_frameskip_allow(uint32_t cmd_e3)
   // but not for interlace since it'll most likely always do that
   uint32_t x = cmd_e3 & 0x3ff;
   uint32_t y = (cmd_e3 >> 10) & 0x3ff;
-  gpu.frameskip.allow = gpu.status.interlace ||
-    (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w ||
-    (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h;
+  gpu.frameskip.allow = (gpu.status & PSX_GPU_STATUS_INTERLACE) ||
+    (uint32_t)(x - gpu.screen.src_x) >= (uint32_t)gpu.screen.w ||
+    (uint32_t)(y - gpu.screen.src_y) >= (uint32_t)gpu.screen.h;
   return gpu.frameskip.allow;
 }
 
@@ -126,17 +185,16 @@ static noinline void get_gpu_info(uint32_t data)
     case 0x02:
     case 0x03:
     case 0x04:
-    case 0x05:
       gpu.gp0 = gpu.ex_regs[data & 7] & 0xfffff;
       break;
-    case 0x06:
-      gpu.gp0 = gpu.ex_regs[5] & 0xfffff;
+    case 0x05:
+      gpu.gp0 = gpu.ex_regs[5] & 0x3fffff;
       break;
     case 0x07:
       gpu.gp0 = 2;
       break;
     default:
-      gpu.gp0 = 0;
+      // gpu.gp0 unchanged
       break;
   }
 }
@@ -163,9 +221,11 @@ long GPUinit(void)
   ret  = vout_init();
   ret |= renderer_init();
 
+  memset(&gpu.state, 0, sizeof(gpu.state));
+  memset(&gpu.frameskip, 0, sizeof(gpu.frameskip));
+  gpu.zero = 0;
   gpu.state.frame_count = &gpu.zero;
   gpu.state.hcnt = &gpu.zero;
-  gpu.frameskip.active = 0;
   gpu.cmd_len = 0;
   do_reset();
 
@@ -193,8 +253,6 @@ long GPUshutdown(void)
 
 void GPUwriteStatus(uint32_t data)
 {
-  static const short hres[8] = { 256, 368, 320, 384, 512, 512, 640, 640 };
-  static const short vres[4] = { 240, 480, 256, 480 };
   uint32_t cmd = data >> 24;
 
   if (cmd < ARRAY_SIZE(gpu.regs)) {
@@ -213,14 +271,21 @@ void GPUwriteStatus(uint32_t data)
       do_cmd_reset();
       break;
     case 0x03:
-      gpu.status.blanking = data & 1;
+      if (data & 1) {
+        gpu.status |= PSX_GPU_STATUS_BLANKING;
+        gpu.state.dims_changed = 1; // for hud clearing
+      }
+      else
+        gpu.status &= ~PSX_GPU_STATUS_BLANKING;
       break;
     case 0x04:
-      gpu.status.dma = data & 3;
+      gpu.status &= ~PSX_GPU_STATUS_DMA_MASK;
+      gpu.status |= PSX_GPU_STATUS_DMA(data & 3);
       break;
     case 0x05:
-      gpu.screen.x = data & 0x3ff;
-      gpu.screen.y = (data >> 10) & 0x1ff;
+      gpu.screen.src_x = data & 0x3ff;
+      gpu.screen.src_y = (data >> 10) & 0x1ff;
+      renderer_notify_scanout_x_change(gpu.screen.src_x, gpu.screen.hres);
       if (gpu.frameskip.set) {
         decide_frameskip_allow(gpu.ex_regs[3]);
         if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) {
@@ -240,9 +305,7 @@ void GPUwriteStatus(uint32_t data)
       update_height();
       break;
     case 0x08:
-      gpu.status.reg = (gpu.status.reg & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10);
-      gpu.screen.hres = hres[(gpu.status.reg >> 16) & 7];
-      gpu.screen.vres = vres[(gpu.status.reg >> 19) & 3];
+      gpu.status = (gpu.status & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10);
       update_width();
       update_height();
       renderer_notify_res_change();
@@ -354,9 +417,9 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
 
   renderer_flush_queues();
   if (is_read) {
-    gpu.status.img = 1;
+    gpu.status |= PSX_GPU_STATUS_IMG;
     // XXX: wrong for width 1
-    memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4);
+    gpu.gp0 = LE32TOH(*(uint32_t *) VRAM_MEM_XY(gpu.dma.x, gpu.dma.y));
     gpu.state.last_vram_read_frame = *gpu.state.frame_count;
   }
 
@@ -367,10 +430,10 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re
 static void finish_vram_transfer(int is_read)
 {
   if (is_read)
-    gpu.status.img = 0;
+    gpu.status &= ~PSX_GPU_STATUS_IMG;
   else
     renderer_update_caches(gpu.dma_start.x, gpu.dma_start.y,
-                           gpu.dma_start.w, gpu.dma_start.h);
+                           gpu.dma_start.w, gpu.dma_start.h, 0);
 }
 
 static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd)
@@ -382,12 +445,12 @@ static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd)
 
   while (pos < count && skip) {
     uint32_t *list = data + pos;
-    cmd = list[0] >> 24;
+    cmd = LE32TOH(list[0]) >> 24;
     len = 1 + cmd_lengths[cmd];
 
     switch (cmd) {
       case 0x02:
-        if ((list[2] & 0x3ff) > gpu.screen.w || ((list[2] >> 16) & 0x1ff) > gpu.screen.h)
+        if ((LE32TOH(list[2]) & 0x3ff) > gpu.screen.w || ((LE32TOH(list[2]) >> 16) & 0x1ff) > gpu.screen.h)
           // clearing something large, don't skip
           do_cmd_list(list, 3, &dummy);
         else
@@ -398,12 +461,12 @@ static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd)
       case 0x34 ... 0x37:
       case 0x3c ... 0x3f:
         gpu.ex_regs[1] &= ~0x1ff;
-        gpu.ex_regs[1] |= list[4 + ((cmd >> 4) & 1)] & 0x1ff;
+        gpu.ex_regs[1] |= LE32TOH(list[4 + ((cmd >> 4) & 1)]) & 0x1ff;
         break;
       case 0x48 ... 0x4F:
         for (v = 3; pos + v < count; v++)
         {
-          if ((list[v] & 0xf000f000) == 0x50005000)
+          if ((list[v] & HTOLE32(0xf000f000)) == HTOLE32(0x50005000))
             break;
         }
         len += v - 3;
@@ -411,16 +474,16 @@ static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd)
       case 0x58 ... 0x5F:
         for (v = 4; pos + v < count; v += 2)
         {
-          if ((list[v] & 0xf000f000) == 0x50005000)
+          if ((list[v] & HTOLE32(0xf000f000)) == HTOLE32(0x50005000))
             break;
         }
         len += v - 4;
         break;
       default:
         if (cmd == 0xe3)
-          skip = decide_frameskip_allow(list[0]);
+          skip = decide_frameskip_allow(LE32TOH(list[0]));
         if ((cmd & 0xf8) == 0xe0)
-          gpu.ex_regs[cmd & 7] = list[0];
+          gpu.ex_regs[cmd & 7] = LE32TOH(list[0]);
         break;
     }
 
@@ -455,7 +518,7 @@ static noinline int do_cmd_buffer(uint32_t *data, int count)
         break;
     }
 
-    cmd = data[pos] >> 24;
+    cmd = LE32TOH(data[pos]) >> 24;
     if (0xa0 <= cmd && cmd <= 0xdf) {
       if (unlikely((pos+2) >= count)) {
         // incomplete vram write/read cmd, can't consume yet
@@ -464,13 +527,13 @@ static noinline int do_cmd_buffer(uint32_t *data, int count)
       }
 
       // consume vram write/read cmd
-      start_vram_transfer(data[pos + 1], data[pos + 2], (cmd & 0xe0) == 0xc0);
+      start_vram_transfer(LE32TOH(data[pos + 1]), LE32TOH(data[pos + 2]), (cmd & 0xe0) == 0xc0);
       pos += 3;
       continue;
     }
 
     // 0xex cmds might affect frameskip.allow, so pass to do_cmd_list_skip
-    if (gpu.frameskip.active && (gpu.frameskip.allow || ((data[pos] >> 24) & 0xf0) == 0xe0))
+    if (gpu.frameskip.active && (gpu.frameskip.allow || ((LE32TOH(data[pos]) >> 24) & 0xf0) == 0xe0))
       pos += do_cmd_list_skip(data + pos, count - pos, &cmd);
     else {
       pos += do_cmd_list(data + pos, count - pos, &cmd);
@@ -482,9 +545,9 @@ static noinline int do_cmd_buffer(uint32_t *data, int count)
       break;
   }
 
-  gpu.status.reg &= ~0x1fff;
-  gpu.status.reg |= gpu.ex_regs[1] & 0x7ff;
-  gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11;
+  gpu.status &= ~0x1fff;
+  gpu.status |= gpu.ex_regs[1] & 0x7ff;
+  gpu.status |= (gpu.ex_regs[6] & 3) << 11;
 
   gpu.state.fb_dirty |= vram_dirty;
 
@@ -519,12 +582,12 @@ void GPUwriteDataMem(uint32_t *mem, int count)
 void GPUwriteData(uint32_t data)
 {
   log_io("gpu_write %08x\n", data);
-  gpu.cmd_buffer[gpu.cmd_len++] = data;
+  gpu.cmd_buffer[gpu.cmd_len++] = HTOLE32(data);
   if (gpu.cmd_len >= CMD_BUFFER_LEN)
     flush_cmd_buffer();
 }
 
-long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
+long GPUdmaChain(uint32_t *rambase, uint32_t start_addr, uint32_t *progress_addr)
 {
   uint32_t addr, *list, ld_addr = 0;
   int len, left, count;
@@ -540,22 +603,36 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
   for (count = 0; (addr & 0x800000) == 0; count++)
   {
     list = rambase + (addr & 0x1fffff) / 4;
-    len = list[0] >> 24;
-    addr = list[0] & 0xffffff;
+    len = LE32TOH(list[0]) >> 24;
+    addr = LE32TOH(list[0]) & 0xffffff;
     preload(rambase + (addr & 0x1fffff) / 4);
 
     cpu_cycles += 10;
     if (len > 0)
       cpu_cycles += 5 + len;
 
-    log_io(".chain %08x #%d\n", (list - rambase) * 4, len);
+    log_io(".chain %08lx #%d+%d\n",
+      (long)(list - rambase) * 4, len, gpu.cmd_len);
+    if (unlikely(gpu.cmd_len > 0)) {
+      memcpy(gpu.cmd_buffer + gpu.cmd_len, list + 1, len * 4);
+      gpu.cmd_len += len;
+      flush_cmd_buffer();
+      continue;
+    }
 
     if (len) {
       left = do_cmd_buffer(list + 1, len);
-      if (left)
-        log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len);
+      if (left) {
+        memcpy(gpu.cmd_buffer, list + 1 + len - left, left * 4);
+        gpu.cmd_len = left;
+        log_anomaly("GPUdmaChain: %d/%d words left\n", left, len);
+      }
     }
 
+    if (progress_addr) {
+      *progress_addr = addr;
+      break;
+    }
     #define LD_THRESHOLD (8*1024)
     if (count >= LD_THRESHOLD) {
       if (count == LD_THRESHOLD) {
@@ -566,7 +643,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
       // loop detection marker
       // (bit23 set causes DMA error on real machine, so
       //  unlikely to be ever set by the game)
-      list[0] |= 0x800000;
+      list[0] |= HTOLE32(0x800000);
     }
   }
 
@@ -576,8 +653,8 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr)
     addr = ld_addr & 0x1fffff;
     while (count-- > 0) {
       list = rambase + addr / 4;
-      addr = list[0] & 0x1fffff;
-      list[0] &= ~0x800000;
+      addr = LE32TOH(list[0]) & 0x1fffff;
+      list[0] &= HTOLE32(~0x800000);
     }
   }
 
@@ -608,8 +685,11 @@ uint32_t GPUreadData(void)
     flush_cmd_buffer();
 
   ret = gpu.gp0;
-  if (gpu.dma.h)
+  if (gpu.dma.h) {
+    ret = HTOLE32(ret);
     do_vram_io(&ret, 1, 1);
+    ret = LE32TOH(ret);
+  }
 
   log_io("gpu_read %08x\n", ret);
   return ret;
@@ -622,7 +702,7 @@ uint32_t GPUreadStatus(void)
   if (unlikely(gpu.cmd_len > 0))
     flush_cmd_buffer();
 
-  ret = gpu.status.reg;
+  ret = gpu.status;
   log_io("gpu_read_status %08x\n", ret);
   return ret;
 }
@@ -646,20 +726,20 @@ long GPUfreeze(uint32_t type, struct GPUFreeze *freeze)
       memcpy(freeze->psxVRam, gpu.vram, 1024 * 512 * 2);
       memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs));
       memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs));
-      freeze->ulStatus = gpu.status.reg;
+      freeze->ulStatus = gpu.status;
       break;
     case 0: // load
       memcpy(gpu.vram, freeze->psxVRam, 1024 * 512 * 2);
       memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs));
       memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs));
-      gpu.status.reg = freeze->ulStatus;
+      gpu.status = freeze->ulStatus;
       gpu.cmd_len = 0;
       for (i = 8; i > 0; i--) {
         gpu.regs[i] ^= 1; // avoid reg change detection
         GPUwriteStatus((i << 24) | (gpu.regs[i] ^ 1));
       }
       renderer_sync_ecmds(gpu.ex_regs);
-      renderer_update_caches(0, 0, 1024, 512);
+      renderer_update_caches(0, 0, 1024, 512, 1);
       break;
   }
 
@@ -672,7 +752,7 @@ void GPUupdateLace(void)
     flush_cmd_buffer();
   renderer_flush_queues();
 
-  if (gpu.status.blanking) {
+  if (gpu.status & PSX_GPU_STATUS_BLANKING) {
     if (!gpu.state.blanked) {
       vout_blank();
       gpu.state.blanked = 1;
@@ -694,6 +774,9 @@ void GPUupdateLace(void)
   }
 
   vout_update();
+  if (gpu.state.enhancement_active && !gpu.state.enhancement_was_active)
+    renderer_update_caches(0, 0, 1024, 512, 1);
+  gpu.state.enhancement_was_active = gpu.state.enhancement_active;
   gpu.state.fb_dirty = 0;
   gpu.state.blanked = 0;
 }
@@ -701,7 +784,8 @@ void GPUupdateLace(void)
 void GPUvBlank(int is_vblank, int lcf)
 {
   int interlace = gpu.state.allow_interlace
-    && gpu.status.interlace && gpu.status.dheight;
+    && (gpu.status & PSX_GPU_STATUS_INTERLACE)
+    && (gpu.status & PSX_GPU_STATUS_DHEIGHT);
   // interlace doesn't look nice on progressive displays,
   // so we have this "auto" mode here for games that don't read vram
   if (gpu.state.allow_interlace == 2
@@ -731,6 +815,15 @@ void GPUrearmedCallbacks(const struct rearmed_cbs *cbs)
   gpu.state.frame_count = cbs->gpu_frame_count;
   gpu.state.allow_interlace = cbs->gpu_neon.allow_interlace;
   gpu.state.enhancement_enable = cbs->gpu_neon.enhancement_enable;
+  if (gpu.state.screen_centering_type != cbs->screen_centering_type
+      || gpu.state.screen_centering_x != cbs->screen_centering_x
+      || gpu.state.screen_centering_y != cbs->screen_centering_y) {
+    gpu.state.screen_centering_type = cbs->screen_centering_type;
+    gpu.state.screen_centering_x = cbs->screen_centering_x;
+    gpu.state.screen_centering_y = cbs->screen_centering_y;
+    update_width();
+    update_height();
+  }
 
   gpu.mmap = cbs->mmap;
   gpu.munmap = cbs->munmap;