X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=plugins%2Fgpulib%2Fgpu.c;h=bef297fb5eb34dfa6447cce3a959fe7363cd8573;hb=ae097dfb64926c50902b08b681cbf805b98e3751;hp=46e92d1b1dcf0fc15191e8309260e4beb50a8626;hpb=fbb4bfffdca204ecb0f228ad13e0b16fd5e5f77e;p=pcsx_rearmed.git diff --git a/plugins/gpulib/gpu.c b/plugins/gpulib/gpu.c index 46e92d1b..bef297fb 100644 --- a/plugins/gpulib/gpu.c +++ b/plugins/gpulib/gpu.c @@ -13,8 +13,15 @@ #include "gpu.h" #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#ifdef __GNUC__ #define unlikely(x) __builtin_expect((x), 0) +#define preload __builtin_prefetch #define noinline __attribute__((noinline)) +#else +#define unlikely(x) +#define preload(...) +#define noinline +#endif #define gpu_log(fmt, ...) \ printf("%d:%03d: " fmt, *gpu.state.frame_count, *gpu.state.hcnt, ##__VA_ARGS__) @@ -24,7 +31,7 @@ //#define log_anomaly gpu_log #define log_anomaly(...) -struct psx_gpu gpu __attribute__((aligned(2048))); +struct psx_gpu gpu; static noinline int do_cmd_buffer(uint32_t *data, int count); static void finish_vram_transfer(int is_read); @@ -49,7 +56,7 @@ static noinline void do_reset(void) memset(gpu.regs, 0, sizeof(gpu.regs)); for (i = 0; i < sizeof(gpu.ex_regs) / sizeof(gpu.ex_regs[0]); i++) gpu.ex_regs[i] = (0xe0 + i) << 24; - gpu.status.reg = 0x14802000; + gpu.status = 0x14802000; gpu.gp0 = 0; gpu.regs[3] = 1; gpu.screen.hres = gpu.screen.w = 256; @@ -68,10 +75,11 @@ static noinline void update_width(void) static noinline void update_height(void) { + // TODO: emulate this properly.. int sh = gpu.screen.y2 - gpu.screen.y1; - if (gpu.status.dheight) + if (gpu.status & PSX_GPU_STATUS_DHEIGHT) sh *= 2; - if (sh <= 0) + if (sh <= 0 || sh > gpu.screen.vres) sh = gpu.screen.vres; gpu.screen.h = sh; @@ -106,7 +114,7 @@ static noinline int decide_frameskip_allow(uint32_t cmd_e3) // but not for interlace since it'll most likely always do that uint32_t x = cmd_e3 & 0x3ff; uint32_t y = (cmd_e3 >> 10) & 0x3ff; - gpu.frameskip.allow = gpu.status.interlace || + gpu.frameskip.allow = (gpu.status & PSX_GPU_STATUS_INTERLACE) || (uint32_t)(x - gpu.screen.x) >= (uint32_t)gpu.screen.w || (uint32_t)(y - gpu.screen.y) >= (uint32_t)gpu.screen.h; return gpu.frameskip.allow; @@ -133,6 +141,22 @@ static noinline void get_gpu_info(uint32_t data) } } +// double, for overdraw guard +#define VRAM_SIZE (1024 * 512 * 2 * 2) + +static int map_vram(void) +{ + gpu.vram = gpu.mmap(VRAM_SIZE); + if (gpu.vram != NULL) { + gpu.vram += 4096 / 2; + return 0; + } + else { + fprintf(stderr, "could not map vram, expect crashes\n"); + return -1; + } +} + long GPUinit(void) { int ret; @@ -145,12 +169,26 @@ long GPUinit(void) gpu.cmd_len = 0; do_reset(); + if (gpu.mmap != NULL) { + if (map_vram() != 0) + ret = -1; + } return ret; } long GPUshutdown(void) { - return vout_finish(); + long ret; + + renderer_finish(); + ret = vout_finish(); + if (gpu.vram != NULL) { + gpu.vram -= 4096 / 2; + gpu.munmap(gpu.vram, VRAM_SIZE); + } + gpu.vram = NULL; + + return ret; } void GPUwriteStatus(uint32_t data) @@ -175,14 +213,18 @@ void GPUwriteStatus(uint32_t data) do_cmd_reset(); break; case 0x03: - gpu.status.blanking = data & 1; + if (data & 1) + gpu.status |= PSX_GPU_STATUS_BLANKING; + else + gpu.status &= ~PSX_GPU_STATUS_BLANKING; break; case 0x04: - gpu.status.dma = data & 3; + gpu.status &= ~PSX_GPU_STATUS_DMA_MASK; + gpu.status |= PSX_GPU_STATUS_DMA(data & 3); break; case 0x05: gpu.screen.x = data & 0x3ff; - gpu.screen.y = (data >> 10) & 0x3ff; + gpu.screen.y = (data >> 10) & 0x1ff; if (gpu.frameskip.set) { decide_frameskip_allow(gpu.ex_regs[3]); if (gpu.frameskip.last_flip_frame != *gpu.state.frame_count) { @@ -202,11 +244,12 @@ void GPUwriteStatus(uint32_t data) update_height(); break; case 0x08: - gpu.status.reg = (gpu.status.reg & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10); - gpu.screen.hres = hres[(gpu.status.reg >> 16) & 7]; - gpu.screen.vres = vres[(gpu.status.reg >> 19) & 3]; + gpu.status = (gpu.status & ~0x7f0000) | ((data & 0x3F) << 17) | ((data & 0x40) << 10); + gpu.screen.hres = hres[(gpu.status >> 16) & 7]; + gpu.screen.vres = vres[(gpu.status >> 19) & 3]; update_width(); update_height(); + renderer_notify_res_change(); break; default: if ((cmd & 0xf0) == 0x10) @@ -315,9 +358,9 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re renderer_flush_queues(); if (is_read) { - gpu.status.img = 1; + gpu.status |= PSX_GPU_STATUS_IMG; // XXX: wrong for width 1 - memcpy(&gpu.gp0, VRAM_MEM_XY(gpu.dma.x, gpu.dma.y), 4); + gpu.gp0 = LE32TOH(*(uint32_t *) VRAM_MEM_XY(gpu.dma.x, gpu.dma.y)); gpu.state.last_vram_read_frame = *gpu.state.frame_count; } @@ -328,7 +371,7 @@ static void start_vram_transfer(uint32_t pos_word, uint32_t size_word, int is_re static void finish_vram_transfer(int is_read) { if (is_read) - gpu.status.img = 0; + gpu.status &= ~PSX_GPU_STATUS_IMG; else renderer_update_caches(gpu.dma_start.x, gpu.dma_start.y, gpu.dma_start.w, gpu.dma_start.h); @@ -336,46 +379,62 @@ static void finish_vram_transfer(int is_read) static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd) { - int cmd = 0, pos = 0, len, dummy; + int cmd = 0, pos = 0, len, dummy, v; int skip = 1; gpu.frameskip.pending_fill[0] = 0; - // XXX: polylines are not properly handled while (pos < count && skip) { uint32_t *list = data + pos; - cmd = list[0] >> 24; + cmd = LE32TOH(list[0]) >> 24; len = 1 + cmd_lengths[cmd]; - if (cmd == 0x02) { - if ((list[2] & 0x3ff) > gpu.screen.w || ((list[2] >> 16) & 0x1ff) > gpu.screen.h) - // clearing something large, don't skip - do_cmd_list(list, 3, &dummy); - else - memcpy(gpu.frameskip.pending_fill, list, 3 * 4); - } - else if ((cmd & 0xf4) == 0x24) { - // flat textured prim - gpu.ex_regs[1] &= ~0x1ff; - gpu.ex_regs[1] |= list[4] & 0x1ff; - } - else if ((cmd & 0xf4) == 0x34) { - // shaded textured prim - gpu.ex_regs[1] &= ~0x1ff; - gpu.ex_regs[1] |= list[5] & 0x1ff; + switch (cmd) { + case 0x02: + if ((LE32TOH(list[2]) & 0x3ff) > gpu.screen.w || ((LE32TOH(list[2]) >> 16) & 0x1ff) > gpu.screen.h) + // clearing something large, don't skip + do_cmd_list(list, 3, &dummy); + else + memcpy(gpu.frameskip.pending_fill, list, 3 * 4); + break; + case 0x24 ... 0x27: + case 0x2c ... 0x2f: + case 0x34 ... 0x37: + case 0x3c ... 0x3f: + gpu.ex_regs[1] &= ~0x1ff; + gpu.ex_regs[1] |= LE32TOH(list[4 + ((cmd >> 4) & 1)]) & 0x1ff; + break; + case 0x48 ... 0x4F: + for (v = 3; pos + v < count; v++) + { + if ((list[v] & HTOLE32(0xf000f000)) == HTOLE32(0x50005000)) + break; + } + len += v - 3; + break; + case 0x58 ... 0x5F: + for (v = 4; pos + v < count; v += 2) + { + if ((list[v] & HTOLE32(0xf000f000)) == HTOLE32(0x50005000)) + break; + } + len += v - 4; + break; + default: + if (cmd == 0xe3) + skip = decide_frameskip_allow(LE32TOH(list[0])); + if ((cmd & 0xf8) == 0xe0) + gpu.ex_regs[cmd & 7] = LE32TOH(list[0]); + break; } - else if (cmd == 0xe3) - skip = decide_frameskip_allow(list[0]); - - if ((cmd & 0xf8) == 0xe0) - gpu.ex_regs[cmd & 7] = list[0]; if (pos + len > count) { cmd = -1; break; // incomplete cmd } - if (cmd == 0xa0 || cmd == 0xc0) + if (0xa0 <= cmd && cmd <= 0xdf) break; // image i/o + pos += len; } @@ -400,16 +459,22 @@ static noinline int do_cmd_buffer(uint32_t *data, int count) break; } - cmd = data[pos] >> 24; - if (cmd == 0xa0 || cmd == 0xc0) { + cmd = LE32TOH(data[pos]) >> 24; + if (0xa0 <= cmd && cmd <= 0xdf) { + if (unlikely((pos+2) >= count)) { + // incomplete vram write/read cmd, can't consume yet + cmd = -1; + break; + } + // consume vram write/read cmd - start_vram_transfer(data[pos + 1], data[pos + 2], cmd == 0xc0); + start_vram_transfer(LE32TOH(data[pos + 1]), LE32TOH(data[pos + 2]), (cmd & 0xe0) == 0xc0); pos += 3; continue; } // 0xex cmds might affect frameskip.allow, so pass to do_cmd_list_skip - if (gpu.frameskip.active && (gpu.frameskip.allow || ((data[pos] >> 24) & 0xf0) == 0xe0)) + if (gpu.frameskip.active && (gpu.frameskip.allow || ((LE32TOH(data[pos]) >> 24) & 0xf0) == 0xe0)) pos += do_cmd_list_skip(data + pos, count - pos, &cmd); else { pos += do_cmd_list(data + pos, count - pos, &cmd); @@ -421,9 +486,9 @@ static noinline int do_cmd_buffer(uint32_t *data, int count) break; } - gpu.status.reg &= ~0x1fff; - gpu.status.reg |= gpu.ex_regs[1] & 0x7ff; - gpu.status.reg |= (gpu.ex_regs[6] & 3) << 11; + gpu.status &= ~0x1fff; + gpu.status |= gpu.ex_regs[1] & 0x7ff; + gpu.status |= (gpu.ex_regs[6] & 3) << 11; gpu.state.fb_dirty |= vram_dirty; @@ -458,67 +523,67 @@ void GPUwriteDataMem(uint32_t *mem, int count) void GPUwriteData(uint32_t data) { log_io("gpu_write %08x\n", data); - gpu.cmd_buffer[gpu.cmd_len++] = data; + gpu.cmd_buffer[gpu.cmd_len++] = HTOLE32(data); if (gpu.cmd_len >= CMD_BUFFER_LEN) flush_cmd_buffer(); } long GPUdmaChain(uint32_t *rambase, uint32_t start_addr) { - uint32_t addr, *list; - uint32_t *llist_entry = NULL; + uint32_t addr, *list, ld_addr = 0; int len, left, count; long cpu_cycles = 0; + preload(rambase + (start_addr & 0x1fffff) / 4); + if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); - // ff7 sends it's main list twice, detect this - if (*gpu.state.frame_count == gpu.state.last_list.frame && - *gpu.state.hcnt - gpu.state.last_list.hcnt <= 1 && - gpu.state.last_list.cycles > 2048) - { - llist_entry = rambase + (gpu.state.last_list.addr & 0x1fffff) / 4; - *llist_entry |= 0x800000; - } - log_io("gpu_dma_chain\n"); addr = start_addr & 0xffffff; - for (count = 0; addr != 0xffffff; count++) + for (count = 0; (addr & 0x800000) == 0; count++) { list = rambase + (addr & 0x1fffff) / 4; - len = list[0] >> 24; - addr = list[0] & 0xffffff; + len = LE32TOH(list[0]) >> 24; + addr = LE32TOH(list[0]) & 0xffffff; + preload(rambase + (addr & 0x1fffff) / 4); + cpu_cycles += 10; if (len > 0) cpu_cycles += 5 + len; log_io(".chain %08x #%d\n", (list - rambase) * 4, len); - // loop detection marker - // (bit23 set causes DMA error on real machine, so - // unlikely to be ever set by the game) - list[0] |= 0x800000; - if (len) { left = do_cmd_buffer(list + 1, len); if (left) log_anomaly("GPUdmaChain: discarded %d/%d words\n", left, len); } - if (addr & 0x800000) - break; + #define LD_THRESHOLD (8*1024) + if (count >= LD_THRESHOLD) { + if (count == LD_THRESHOLD) { + ld_addr = addr; + continue; + } + + // loop detection marker + // (bit23 set causes DMA error on real machine, so + // unlikely to be ever set by the game) + list[0] |= HTOLE32(0x800000); + } } - // remove loop detection markers - addr = start_addr & 0x1fffff; - while (count-- > 0) { - list = rambase + addr / 4; - addr = list[0] & 0x1fffff; - list[0] &= ~0x800000; + if (ld_addr != 0) { + // remove loop detection markers + count -= LD_THRESHOLD + 2; + addr = ld_addr & 0x1fffff; + while (count-- > 0) { + list = rambase + addr / 4; + addr = LE32TOH(list[0]) & 0x1fffff; + list[0] &= HTOLE32(~0x800000); + } } - if (llist_entry) - *llist_entry &= ~0x800000; gpu.state.last_list.frame = *gpu.state.frame_count; gpu.state.last_list.hcnt = *gpu.state.hcnt; @@ -547,8 +612,11 @@ uint32_t GPUreadData(void) flush_cmd_buffer(); ret = gpu.gp0; - if (gpu.dma.h) + if (gpu.dma.h) { + ret = HTOLE32(ret); do_vram_io(&ret, 1, 1); + ret = LE32TOH(ret); + } log_io("gpu_read %08x\n", ret); return ret; @@ -561,7 +629,7 @@ uint32_t GPUreadStatus(void) if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); - ret = gpu.status.reg; + ret = gpu.status; log_io("gpu_read_status %08x\n", ret); return ret; } @@ -582,16 +650,16 @@ long GPUfreeze(uint32_t type, struct GPUFreeze *freeze) case 1: // save if (gpu.cmd_len > 0) flush_cmd_buffer(); - memcpy(freeze->psxVRam, gpu.vram, sizeof(gpu.vram)); + memcpy(freeze->psxVRam, gpu.vram, 1024 * 512 * 2); memcpy(freeze->ulControl, gpu.regs, sizeof(gpu.regs)); memcpy(freeze->ulControl + 0xe0, gpu.ex_regs, sizeof(gpu.ex_regs)); - freeze->ulStatus = gpu.status.reg; + freeze->ulStatus = gpu.status; break; case 0: // load - memcpy(gpu.vram, freeze->psxVRam, sizeof(gpu.vram)); + memcpy(gpu.vram, freeze->psxVRam, 1024 * 512 * 2); memcpy(gpu.regs, freeze->ulControl, sizeof(gpu.regs)); memcpy(gpu.ex_regs, freeze->ulControl + 0xe0, sizeof(gpu.ex_regs)); - gpu.status.reg = freeze->ulStatus; + gpu.status = freeze->ulStatus; gpu.cmd_len = 0; for (i = 8; i > 0; i--) { gpu.regs[i] ^= 1; // avoid reg change detection @@ -611,7 +679,7 @@ void GPUupdateLace(void) flush_cmd_buffer(); renderer_flush_queues(); - if (gpu.status.blanking) { + if (gpu.status & PSX_GPU_STATUS_BLANKING) { if (!gpu.state.blanked) { vout_blank(); gpu.state.blanked = 1; @@ -640,7 +708,8 @@ void GPUupdateLace(void) void GPUvBlank(int is_vblank, int lcf) { int interlace = gpu.state.allow_interlace - && gpu.status.interlace && gpu.status.dheight; + && (gpu.status & PSX_GPU_STATUS_INTERLACE) + && (gpu.status & PSX_GPU_STATUS_DHEIGHT); // interlace doesn't look nice on progressive displays, // so we have this "auto" mode here for games that don't read vram if (gpu.state.allow_interlace == 2 @@ -669,6 +738,14 @@ void GPUrearmedCallbacks(const struct rearmed_cbs *cbs) gpu.state.hcnt = cbs->gpu_hcnt; gpu.state.frame_count = cbs->gpu_frame_count; gpu.state.allow_interlace = cbs->gpu_neon.allow_interlace; + gpu.state.enhancement_enable = cbs->gpu_neon.enhancement_enable; + + gpu.mmap = cbs->mmap; + gpu.munmap = cbs->munmap; + + // delayed vram mmap + if (gpu.vram == NULL) + map_vram(); if (cbs->pl_vout_set_raw_vram) cbs->pl_vout_set_raw_vram(gpu.vram);