X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=plugins%2Fgpulib%2Fgpu.c;h=e3943a251660ee9c5d4da62be3f151f87dd31fd5;hb=c296224f47ceebab4d6fbd071959bff294e80293;hp=22571fa2b5f98e0ca6a9abbbac53b0a0fcda7b34;hpb=8f8ade9c6a3da1dd6d254789d50df6b8c2997850;p=pcsx_rearmed.git diff --git a/plugins/gpulib/gpu.c b/plugins/gpulib/gpu.c index 22571fa2..e3943a25 100644 --- a/plugins/gpulib/gpu.c +++ b/plugins/gpulib/gpu.c @@ -14,6 +14,7 @@ #include /* for calloc */ #include "gpu.h" +#include "gpu_timing.h" #include "../../libpcsxcore/gpu.h" // meh #include "../../frontend/plugin_lib.h" @@ -35,15 +36,15 @@ struct psx_gpu gpu; -static noinline int do_cmd_buffer(uint32_t *data, int count); +static noinline int do_cmd_buffer(uint32_t *data, int count, int *cpu_cycles); static void finish_vram_transfer(int is_read); static noinline void do_cmd_reset(void) { + int dummy = 0; renderer_sync(); - if (unlikely(gpu.cmd_len > 0)) - do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len); + do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len, &dummy); gpu.cmd_len = 0; if (unlikely(gpu.dma.h > 0)) @@ -78,7 +79,10 @@ static noinline void update_width(void) int hres = hres_all[(gpu.status >> 16) & 7]; int pal = gpu.status & PSX_GPU_STATUS_PAL; int sw = gpu.screen.x2 - gpu.screen.x1; + int type = gpu.state.screen_centering_type; int x = 0, x_auto; + if (type == C_AUTO) + type = gpu.state.screen_centering_type_default; if (sw <= 0) /* nothing displayed? */; else { @@ -87,7 +91,7 @@ static noinline void update_width(void) x = (x + 1) & ~1; // blitter limitation sw /= hdiv; sw = (sw + 2) & ~3; // according to nocash - switch (gpu.state.screen_centering_type) { + switch (type) { case C_INGAME: break; case C_MANUAL: @@ -177,8 +181,8 @@ static noinline void decide_frameskip(void) gpu.frameskip.active = 0; if (!gpu.frameskip.active && gpu.frameskip.pending_fill[0] != 0) { - int dummy; - do_cmd_list(gpu.frameskip.pending_fill, 3, &dummy); + int dummy = 0; + do_cmd_list(gpu.frameskip.pending_fill, 3, &dummy, &dummy); gpu.frameskip.pending_fill[0] = 0; } } @@ -219,8 +223,9 @@ static noinline void get_gpu_info(uint32_t data) } } -// double, for overdraw guard -#define VRAM_SIZE ((1024 * 512 * 2 * 2) + 4096) +#ifndef max +#define max(a, b) (((a) > (b)) ? (a) : (b)) +#endif // Minimum 16-byte VRAM alignment needed by gpu_unai's pixel-skipping // renderer/downscaler it uses in high res modes: @@ -232,6 +237,9 @@ static noinline void get_gpu_info(uint32_t data) #define VRAM_ALIGN 16 #endif +// double, for overdraw guard + at least 1 page before +#define VRAM_SIZE ((1024 * 512 * 2 * 2) + max(VRAM_ALIGN, 4096)) + // vram ptr received from mmap/malloc/alloc (will deallocate using this) static uint16_t *vram_ptr_orig = NULL; @@ -245,9 +253,9 @@ static uint16_t *vram_ptr_orig = NULL; static int map_vram(void) { #if GPULIB_USE_MMAP - gpu.vram = vram_ptr_orig = gpu.mmap(VRAM_SIZE + (VRAM_ALIGN-1)); + gpu.vram = vram_ptr_orig = gpu.mmap(VRAM_SIZE); #else - gpu.vram = vram_ptr_orig = calloc(VRAM_SIZE + (VRAM_ALIGN-1), 1); + gpu.vram = vram_ptr_orig = calloc(VRAM_SIZE, 1); #endif if (gpu.vram != NULL && gpu.vram != (void *)(intptr_t)-1) { // 4kb guard in front @@ -510,7 +518,7 @@ static void finish_vram_transfer(int is_read) gpu.gpu_state_change(PGS_VRAM_TRANSFER_END); } -static void do_vram_copy(const uint32_t *params) +static void do_vram_copy(const uint32_t *params, int *cpu_cycles) { const uint32_t sx = LE32TOH(params[0]) & 0x3FF; const uint32_t sy = (LE32TOH(params[0]) >> 16) & 0x1FF; @@ -522,6 +530,7 @@ static void do_vram_copy(const uint32_t *params) uint16_t lbuf[128]; uint32_t x, y; + *cpu_cycles += gput_copy(w, h); if (sx == dx && sy == dy && msb == 0) return; @@ -557,7 +566,7 @@ static void do_vram_copy(const uint32_t *params) static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd) { - int cmd = 0, pos = 0, len, dummy, v; + int cmd = 0, pos = 0, len, dummy = 0, v; int skip = 1; gpu.frameskip.pending_fill[0] = 0; @@ -571,7 +580,7 @@ static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd) case 0x02: if ((LE32TOH(list[2]) & 0x3ff) > gpu.screen.w || ((LE32TOH(list[2]) >> 16) & 0x1ff) > gpu.screen.h) // clearing something large, don't skip - do_cmd_list(list, 3, &dummy); + do_cmd_list(list, 3, &dummy, &dummy); else memcpy(gpu.frameskip.pending_fill, list, 3 * 4); break; @@ -621,7 +630,7 @@ static noinline int do_cmd_list_skip(uint32_t *data, int count, int *last_cmd) return pos; } -static noinline int do_cmd_buffer(uint32_t *data, int count) +static noinline int do_cmd_buffer(uint32_t *data, int count, int *cpu_cycles) { int cmd, pos; uint32_t old_e3 = gpu.ex_regs[3]; @@ -655,17 +664,22 @@ static noinline int do_cmd_buffer(uint32_t *data, int count) cmd = -1; // incomplete cmd, can't consume yet break; } - do_vram_copy(data + pos + 1); + do_vram_copy(data + pos + 1, cpu_cycles); vram_dirty = 1; pos += 4; continue; } + else if (cmd == 0x1f) { + log_anomaly("irq1?\n"); + pos++; + continue; + } // 0xex cmds might affect frameskip.allow, so pass to do_cmd_list_skip if (gpu.frameskip.active && (gpu.frameskip.allow || ((LE32TOH(data[pos]) >> 24) & 0xf0) == 0xe0)) pos += do_cmd_list_skip(data + pos, count - pos, &cmd); else { - pos += do_cmd_list(data + pos, count - pos, &cmd); + pos += do_cmd_list(data + pos, count - pos, cpu_cycles, &cmd); vram_dirty = 1; } @@ -688,7 +702,8 @@ static noinline int do_cmd_buffer(uint32_t *data, int count) static noinline void flush_cmd_buffer(void) { - int left = do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len); + int dummy = 0, left; + left = do_cmd_buffer(gpu.cmd_buffer, gpu.cmd_len, &dummy); if (left > 0) memmove(gpu.cmd_buffer, gpu.cmd_buffer + gpu.cmd_len - left, left * 4); if (left != gpu.cmd_len) { @@ -700,14 +715,14 @@ static noinline void flush_cmd_buffer(void) void GPUwriteDataMem(uint32_t *mem, int count) { - int left; + int dummy = 0, left; log_io("gpu_dma_write %p %d\n", mem, count); if (unlikely(gpu.cmd_len > 0)) flush_cmd_buffer(); - left = do_cmd_buffer(mem, count); + left = do_cmd_buffer(mem, count, &dummy); if (left) log_anomaly("GPUwriteDataMem: discarded %d/%d words\n", left, count); } @@ -724,7 +739,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr, uint32_t *progress_addr { uint32_t addr, *list, ld_addr = 0; int len, left, count; - long cpu_cycles = 0; + int cpu_cycles = 0; preload(rambase + (start_addr & 0x1fffff) / 4); @@ -744,8 +759,8 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr, uint32_t *progress_addr if (len > 0) cpu_cycles += 5 + len; - log_io(".chain %08lx #%d+%d\n", - (long)(list - rambase) * 4, len, gpu.cmd_len); + log_io(".chain %08lx #%d+%d %u\n", + (long)(list - rambase) * 4, len, gpu.cmd_len, cpu_cycles); if (unlikely(gpu.cmd_len > 0)) { if (gpu.cmd_len + len > ARRAY_SIZE(gpu.cmd_buffer)) { log_anomaly("cmd_buffer overflow, likely garbage commands\n"); @@ -758,7 +773,7 @@ long GPUdmaChain(uint32_t *rambase, uint32_t start_addr, uint32_t *progress_addr } if (len) { - left = do_cmd_buffer(list + 1, len); + left = do_cmd_buffer(list + 1, len, &cpu_cycles); if (left) { memcpy(gpu.cmd_buffer, list + 1 + len - left, left * 4); gpu.cmd_len = left; @@ -968,6 +983,7 @@ void GPUrearmedCallbacks(const struct rearmed_cbs *cbs) gpu.state.frame_count = cbs->gpu_frame_count; gpu.state.allow_interlace = cbs->gpu_neon.allow_interlace; gpu.state.enhancement_enable = cbs->gpu_neon.enhancement_enable; + gpu.state.screen_centering_type_default = cbs->screen_centering_type_default; if (gpu.state.screen_centering_type != cbs->screen_centering_type || gpu.state.screen_centering_x != cbs->screen_centering_x || gpu.state.screen_centering_y != cbs->screen_centering_y) {