X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=teensy3%2Fmk20dx128.c;h=d9a751fd2646208875a8cad11bc6b65fffe1233a;hb=a773ac06cdc55be51ebc0bc61aa6066b54746c7d;hp=4dc722540f0b041ec42def81a9def948954d65d8;hpb=35f00b6caaac4a8b93247913f0863bcd8f419041;p=megadrive.git diff --git a/teensy3/mk20dx128.c b/teensy3/mk20dx128.c index 4dc7225..d9a751f 100644 --- a/teensy3/mk20dx128.c +++ b/teensy3/mk20dx128.c @@ -28,7 +28,7 @@ * SOFTWARE. */ -#include "mk20dx128.h" +#include "kinetis.h" extern unsigned long _stext; @@ -40,6 +40,9 @@ extern unsigned long _ebss; extern unsigned long _estack; //extern void __init_array_start(void); //extern void __init_array_end(void); + + + extern int main (void); void ResetHandler(void); void _init_Teensyduino_internal_(void); @@ -161,11 +164,15 @@ void portd_isr(void) __attribute__ ((weak, alias("unused_isr"))); void porte_isr(void) __attribute__ ((weak, alias("unused_isr"))); void software_isr(void) __attribute__ ((weak, alias("unused_isr"))); +#if defined(__MK20DX128__) +__attribute__ ((section(".dmabuffers"), used, aligned(256))) +#else +__attribute__ ((section(".dmabuffers"), used, aligned(512))) +#endif +void (* _VectorsRam[NVIC_NUM_INTERRUPTS+16])(void); -// TODO: create AVR-stype ISR() macro, with default linkage to undefined handler -// __attribute__ ((section(".vectors"), used)) -void (* const gVectors[])(void) = +void (* const _VectorsFlash[NVIC_NUM_INTERRUPTS+16])(void) = { (void (*)(void))((unsigned long)&_estack), // 0 ARM: Initial Stack Pointer ResetHandler, // 1 ARM: Initial Program Counter @@ -360,11 +367,14 @@ void ResetHandler(void) uint32_t *src = &_etext; uint32_t *dest = &_sdata; unsigned int i; +#if F_CPU <= 2000000 + volatile int n; +#endif WDOG_UNLOCK = WDOG_UNLOCK_SEQ1; WDOG_UNLOCK = WDOG_UNLOCK_SEQ2; - asm volatile ("nop"); - asm volatile ("nop"); + __asm__ volatile ("nop"); + __asm__ volatile ("nop"); // programs using the watchdog timer or needing to initialize hardware as // early as possible can implement startup_early_hook() startup_early_hook(); @@ -378,7 +388,6 @@ void ResetHandler(void) SIM_SCGC5 = 0x00043F82; // clocks active to all GPIO SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL; #endif - // if the RTC oscillator isn't enabled, get it started early if (!(RTC_CR & RTC_CR_OSCE)) { RTC_SR = 0; @@ -388,16 +397,46 @@ void ResetHandler(void) // release I/O pins hold, if we woke up from VLLS mode if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO; + // since this is a write once register, make it visible to all F_CPU's + // so we can into other sleep modes in the future at any speed + SMC_PMPROT = SMC_PMPROT_AVLP | SMC_PMPROT_ALLS | SMC_PMPROT_AVLLS; + // TODO: do this while the PLL is waiting to lock.... while (dest < &_edata) *dest++ = *src++; dest = &_sbss; while (dest < &_ebss) *dest++ = 0; - SCB_VTOR = 0; // use vector table in flash // default all interrupts to medium priority level + for (i=0; i < NVIC_NUM_INTERRUPTS + 16; i++) _VectorsRam[i] = _VectorsFlash[i]; for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128); - - // start in FEI mode + SCB_VTOR = (uint32_t)_VectorsRam; // use vector table in RAM + + // hardware always starts in FEI mode + // C1[CLKS] bits are written to 00 + // C1[IREFS] bit is written to 1 + // C6[PLLS] bit is written to 0 +// MCG_SC[FCDIV] defaults to divide by two for internal ref clock +// I tried changing MSG_SC to divide by 1, it didn't work for me +#if F_CPU <= 2000000 + // use the internal oscillator + MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_IREFS; + // wait for MCGOUT to use oscillator + while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(1)) ; + for (n=0; n<10; n++) ; // TODO: why do we get 2 mA extra without this delay? + MCG_C2 = MCG_C2_IRCS; + while (!(MCG_S & MCG_S_IRCST)) ; + // now in FBI mode: + // C1[CLKS] bits are written to 01 + // C1[IREFS] bit is written to 1 + // C6[PLLS] is written to 0 + // C2[LP] is written to 0 + MCG_C2 = MCG_C2_IRCS | MCG_C2_LP; + // now in BLPI mode: + // C1[CLKS] bits are written to 01 + // C1[IREFS] bit is written to 1 + // C6[PLLS] bit is written to 0 + // C2[LP] bit is written to 1 +#else // enable capacitors for crystal OSC0_CR = OSC_SC8P | OSC_SC2P; // enable osc, 8-32 MHz range, low power mode @@ -410,37 +449,113 @@ void ResetHandler(void) while ((MCG_S & MCG_S_IREFST) != 0) ; // wait for MCGOUT to use oscillator while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ; - // now we're in FBE mode - // config PLL input for 16 MHz Crystal / 4 = 4 MHz - MCG_C5 = MCG_C5_PRDIV0(3); - // config PLL for 96 MHz output - MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); + // now in FBE mode + // C1[CLKS] bits are written to 10 + // C1[IREFS] bit is written to 0 + // C1[FRDIV] must be written to divide xtal to 31.25-39 kHz + // C6[PLLS] bit is written to 0 + // C2[LP] is written to 0 + #if F_CPU <= 16000000 + // if the crystal is fast enough, use it directly (no FLL or PLL) + MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS | MCG_C2_LP; + // BLPE mode: + // C1[CLKS] bits are written to 10 + // C1[IREFS] bit is written to 0 + // C2[LP] bit is written to 1 + #else + // if we need faster than the crystal, turn on the PLL + #if F_CPU == 72000000 + MCG_C5 = MCG_C5_PRDIV0(5); // config PLL input for 16 MHz Crystal / 6 = 2.667 Hz + #else + MCG_C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz + #endif + #if F_CPU == 168000000 + MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(18); // config PLL for 168 MHz output + #elif F_CPU == 144000000 + MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(12); // config PLL for 144 MHz output + #elif F_CPU == 120000000 + MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(6); // config PLL for 120 MHz output + #elif F_CPU == 72000000 + MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(3); // config PLL for 72 MHz output + #else + MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); // config PLL for 96 MHz output + #endif // wait for PLL to start using xtal as its input while (!(MCG_S & MCG_S_PLLST)) ; // wait for PLL to lock while (!(MCG_S & MCG_S_LOCK0)) ; // now we're in PBE mode -#if F_CPU == 96000000 - // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash + #endif +#endif + + // now program the clock dividers +#if F_CPU == 168000000 + // config divisors: 168 MHz core, 56 MHz bus, 33.6 MHz flash, USB = 168 * 2 / 7 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(4); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(6) | SIM_CLKDIV2_USBFRAC; +#elif F_CPU == 144000000 + // config divisors: 144 MHz core, 48 MHz bus, 28.8 MHz flash, USB = 144 / 3 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(2) | SIM_CLKDIV1_OUTDIV4(4); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2); +#elif F_CPU == 120000000 + // config divisors: 120 MHz core, 60 MHz bus, 24 MHz flash, USB = 128 * 2 / 5 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(4); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC; +#elif F_CPU == 96000000 + // config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2 SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); +#elif F_CPU == 72000000 + // config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash, USB = 72 * 2 / 3 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC; #elif F_CPU == 48000000 - // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash + // config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash, USB = 96 / 2 SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); #elif F_CPU == 24000000 - // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash + // config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash, USB = 96 / 2 + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3); + SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); +#elif F_CPU == 16000000 + // config divisors: 16 MHz core, 16 MHz bus, 16 MHz flash + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(0); +#elif F_CPU == 8000000 + // config divisors: 8 MHz core, 8 MHz bus, 8 MHz flash + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(1); +#elif F_CPU == 4000000 + // config divisors: 4 MHz core, 4 MHz bus, 2 MHz flash + // since we are running from external clock 16MHz + // fix outdiv too -> cpu 16/4, bus 16/4, flash 16/4 + // here we can go into vlpr? + // config divisors: 4 MHz core, 4 MHz bus, 4 MHz flash SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3); +#elif F_CPU == 2000000 + // since we are running from the fast internal reference clock 4MHz + // but is divided down by 2 so we actually have a 2MHz, MCG_SC[FCDIV] default is 2 + // fix outdiv -> cpu 2/1, bus 2/1, flash 2/2 + // config divisors: 2 MHz core, 2 MHz bus, 1 MHz flash + SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1); #else -#error "Error, F_CPU must be 96000000, 48000000, or 24000000" +#error "Error, F_CPU must be 168, 144, 120, 96, 72, 48, 24, 16, 8, 4, or 2 MHz" #endif + +#if F_CPU > 16000000 // switch to PLL as clock source, FLL input = 16 MHz / 512 MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4); // wait for PLL clock to be used while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ; // now we're in PEE mode - // configure USB for 48 MHz clock - SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2 // USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); +#else + SIM_SOPT2 = SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(3); +#endif + +#if F_CPU <= 2000000 + // since we are not going into "stop mode" i removed it + SMC_PMCTRL = SMC_PMCTRL_RUNM(2); // VLPR mode :-) +#endif // initialize the SysTick counter SYST_RVR = (F_CPU / 1000) - 1; @@ -450,35 +565,23 @@ void ResetHandler(void) __enable_irq(); _init_Teensyduino_internal_(); - if (RTC_SR & RTC_SR_TIF) rtc_set(TIME_T); + if (RTC_SR & RTC_SR_TIF) { + // TODO: this should probably set the time more agressively, if + // we could reliably detect the first reboot after programming. + rtc_set(TIME_T); + } __libc_init_array(); -/* - for (ptr = &__init_array_start; ptr < &__init_array_end; ptr++) { - (*ptr)(); - } -*/ startup_late_hook(); main(); while (1) ; } -// TODO: is this needed for c++ and where does it come from? -/* -void _init(void) -{ -} -*/ - char *__brkval = (char *)&_ebss; void * _sbrk(int incr) { - //static char *heap_end = (char *)&_ebss; - //char *prev = heap_end; - //heap_end += incr; - char *prev = __brkval; __brkval += incr; return prev; @@ -490,14 +593,6 @@ int _read(int file, char *ptr, int len) return 0; } -/* moved to Print.cpp, to support Print::printf() -__attribute__((weak)) -int _write(int file, char *ptr, int len) -{ - return 0; -} -*/ - __attribute__((weak)) int _close(int fd) { @@ -556,16 +651,16 @@ int nvic_execution_priority(void) // full algorithm in ARM DDI0403D, page B1-639 // this isn't quite complete, but hopefully good enough - asm volatile("mrs %0, faultmask\n" : "=r" (faultmask)::); + __asm__ volatile("mrs %0, faultmask\n" : "=r" (faultmask)::); if (faultmask) return -1; - asm volatile("mrs %0, primask\n" : "=r" (primask)::); + __asm__ volatile("mrs %0, primask\n" : "=r" (primask)::); if (primask) return 0; - asm volatile("mrs %0, ipsr\n" : "=r" (ipsr)::); + __asm__ volatile("mrs %0, ipsr\n" : "=r" (ipsr)::); if (ipsr) { if (ipsr < 16) priority = 0; // could be non-zero else priority = NVIC_GET_PRIORITY(ipsr - 16); } - asm volatile("mrs %0, basepri\n" : "=r" (basepri)::); + __asm__ volatile("mrs %0, basepri\n" : "=r" (basepri)::); if (basepri > 0 && basepri < priority) priority = basepri; return priority; }