X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=testpico%2Fmain.c;h=0e6c69215eec64537d5af5c5a078de4d1988b31b;hb=4f936a9c6b1180ffe82b618bacade0c746cd3c18;hp=c1b09318001bc1baeb1af067158b3f909c143750;hpb=ffd4b35c4235e0c1a10cb8137c607c4788fd543a;p=megadrive.git diff --git a/testpico/main.c b/testpico/main.c index c1b0931..0e6c692 100644 --- a/testpico/main.c +++ b/testpico/main.c @@ -4,29 +4,17 @@ */ #include #include - -#define u8 unsigned char -#define u16 unsigned short -#define u32 unsigned int - -#define noinline __attribute__((noinline)) -#define unused __attribute__((unused)) -#define _packed __attribute__((packed)) - -#define mem_barrier() \ - asm volatile("":::"memory") - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) - +#include "common.h" #include "asmtools.h" #define VDP_DATA_PORT 0xC00000 #define VDP_CTRL_PORT 0xC00004 +#define VDP_HV_COUNTER 0xC00008 #define TILE_MEM_END 0xB000 #define FONT_LEN 128 -#define TILE_FONT_BASE (TILE_MEM_END / 32 - FONT_LEN) +#define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32) /* note: using ED menu's layout here.. */ #define WPLANE (TILE_MEM_END + 0x0000) @@ -35,19 +23,6 @@ #define APLANE (TILE_MEM_END + 0x1000) #define BPLANE (TILE_MEM_END + 0x3000) -#define read8(a) \ - *((volatile u8 *) (a)) -#define read16(a) \ - *((volatile u16 *) (a)) -#define read32(a) \ - *((volatile u32 *) (a)) -#define write8(a, d) \ - *((volatile u8 *) (a)) = (d) -#define write16(a, d) \ - *((volatile u16 *) (a)) = (d) -#define write32(a, d) \ - *((volatile u32 *) (a)) = (d) - #define write16_z80le(a, d) \ ((volatile u8 *)(a))[0] = (u8)(d), \ ((volatile u8 *)(a))[1] = ((d) >> 8) @@ -103,6 +78,18 @@ enum { #define VDP_MODE2_DMA 0x10 #define VDP_MODE2_IE0 0x20 // v int #define VDP_MODE2_DISP 0x40 +#define VDP_MODE2_128K 0x80 + +#define SR_PAL (1 << 0) +#define SR_DMA (1 << 1) +#define SR_HB (1 << 2) +#define SR_VB (1 << 3) +#define SR_ODD (1 << 4) +#define SR_C (1 << 5) +#define SR_SOVR (1 << 6) +#define SR_F (1 << 7) +#define SR_FULL (1 << 8) +#define SR_EMPT (1 << 9) /* cell counts */ #define LEFT_BORDER 1 /* lame TV */ @@ -323,8 +310,6 @@ struct exc_frame { }; } _packed; -int xtttt(void) { return sizeof(struct exc_frame); } - void exception(const struct exc_frame *f) { int i; @@ -385,6 +370,30 @@ static void do_setup_dma(const void *src_, u16 words) // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA); } +static void vdp_wait_for_fifo_empty(void) +{ + while (!(read16(VDP_CTRL_PORT) & 0x200)) + /* fifo not empty */; +} + +static void vdp_wait_for_dma_idle(void) +{ + while (read16(VDP_CTRL_PORT) & 2) + /* dma busy */; +} + +static void vdp_wait_for_line_0(void) +{ + // in PAL vcounter reports 0 twice in a frame, + // so wait for vblank to clear first + while (!(read16(VDP_CTRL_PORT) & 8)) + /* not blanking */; + while (read16(VDP_CTRL_PORT) & 8) + /* blanking */; + while (read8(VDP_HV_COUNTER) != 0) + ; +} + static void t_dma_zero_wrap_early(void) { const u32 *src = (const u32 *)0x3c0000; @@ -415,8 +424,7 @@ static void t_dma_zero_fill_early(void) write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA); write16(VDP_DATA_PORT, 0x1122); ram[2] = read16(VDP_CTRL_PORT); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_AUTOINC, 2); write32(VDP_CTRL_PORT, CTL_READ_VRAM(0)); @@ -429,6 +437,18 @@ if ((v0_) != (v1_)) { \ ok_ = 0; \ } +#define expect_range(ok_, v0_, vmin_, vmax_) \ +if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \ + printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \ + ok_ = 0; \ +} + +#define expect_bits(ok_, v0_, val_, mask_) \ +if (((v0_) & (mask_)) != (val_)) { \ + printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \ + ok_ = 0; \ +} + static int t_dma_zero_wrap(void) { const u32 *src = (const u32 *)0x3c0000; @@ -557,7 +577,7 @@ static int t_dma_vsram_wrap(void) static int t_dma_and_data(void) { const u32 *src = (const u32 *)0x3c0000; - u32 v0; + u32 v0, v1; int ok = 1; write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); @@ -567,10 +587,42 @@ static int t_dma_and_data(void) write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA); write32(VDP_DATA_PORT, 0x5ec8a248); - write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc)); v0 = read32(VDP_DATA_PORT); + v1 = read32(VDP_DATA_PORT); - expect(ok, v0, 0x5ec8a248); + expect(ok, v0, src[0]); + expect(ok, v1, 0x5ec8a248); + return ok; +} + +static int t_dma_short_cmd(void) +{ + const u32 *src = (const u32 *)0x3c0000; + u32 v0, v1, v2; + int ok = 1; + + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4)); + write32(VDP_DATA_PORT, 0x10111213); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0)); + write32(VDP_DATA_PORT, 0x20212223); + write32(VDP_DATA_PORT, 0x30313233); + vdp_wait_for_fifo_empty(); + + do_setup_dma(src, 2); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA); + write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16); + write32(VDP_DATA_PORT, 0x40414243); + + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4)); + v0 = read32(VDP_DATA_PORT); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0)); + v1 = read32(VDP_DATA_PORT); + v2 = read32(VDP_DATA_PORT); + + expect(ok, v0, 0x10111213); + expect(ok, v1, src[0]); + expect(ok, v2, 0x40414243); return ok; } @@ -583,14 +635,14 @@ static int t_dma_fill3_odd(void) write32(VDP_DATA_PORT, 0); write32(VDP_DATA_PORT, 0); write32(VDP_DATA_PORT, 0); + vdp_wait_for_fifo_empty(); VDP_setReg(VDP_AUTOINC, 3); VDP_setReg(VDP_DMA_LEN0, 3); VDP_setReg(VDP_DMA_SRC2, 0x80); write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA); write16(VDP_DATA_PORT, 0x1122); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_AUTOINC, 2); write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); @@ -613,14 +665,14 @@ static int t_dma_fill3_even(void) write32(VDP_DATA_PORT, 0); write32(VDP_DATA_PORT, 0); write32(VDP_DATA_PORT, 0); + vdp_wait_for_fifo_empty(); VDP_setReg(VDP_AUTOINC, 3); VDP_setReg(VDP_DMA_LEN0, 3); VDP_setReg(VDP_DMA_SRC2, 0x80); write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); write16(VDP_DATA_PORT, 0x1122); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_AUTOINC, 2); write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); @@ -647,14 +699,14 @@ static unused int t_dma_fill3_vsram(void) write16(VDP_DATA_PORT, 0x0111); write16(VDP_DATA_PORT, 0x0222); write16(VDP_DATA_PORT, 0x0333); + vdp_wait_for_fifo_empty(); VDP_setReg(VDP_AUTOINC, 3); VDP_setReg(VDP_DMA_LEN0, 3); VDP_setReg(VDP_DMA_SRC2, 0x80); write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA); write16(VDP_DATA_PORT, 0x0102); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_AUTOINC, 2); write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0)); @@ -685,13 +737,11 @@ static int t_dma_fill_dis(void) write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); VDP_setReg(VDP_MODE2, VDP_MODE2_MD); write16(VDP_DATA_PORT, 0x1122); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); write16(VDP_DATA_PORT, 0x3344); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); v0 = read32(VDP_DATA_PORT); @@ -718,8 +768,7 @@ static int t_dma_fill_src(void) VDP_setReg(VDP_DMA_SRC2, 0x80); write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); write16(VDP_DATA_PORT, 0x1122); - while (read16(VDP_CTRL_PORT) & 2) - ; + vdp_wait_for_dma_idle(); VDP_setReg(VDP_DMA_LEN0, 2); VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17); @@ -734,6 +783,145 @@ static int t_dma_fill_src(void) return ok; } +// (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1) +static int t_dma_128k(void) +{ + u16 *ram = (u16 *)0xff0000; + u32 v0, v1; + int ok = 1; + + ram[0] = 0x5a11; + ram[1] = 0x5a22; + ram[2] = 0x5a33; + + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); + write32(VDP_DATA_PORT, 0x01020304); + write32(VDP_DATA_PORT, 0x05060708); + vdp_wait_for_fifo_empty(); + + mem_barrier(); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); + do_setup_dma(ram, 3); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA); + vdp_wait_for_fifo_empty(); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); + v0 = read32(VDP_DATA_PORT); + v1 = read32(VDP_DATA_PORT); + + expect(ok, v0, 0x22110304); + expect(ok, v1, 0x05330708); + return ok; +} + +static int t_vdp_128k_b16(void) +{ + u32 v0, v1; + int ok = 1; + + VDP_setReg(VDP_AUTOINC, 0); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100)); + write32(VDP_DATA_PORT, 0x01020304); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100)); + write32(VDP_DATA_PORT, 0x05060708); + vdp_wait_for_fifo_empty(); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); + write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd + write32(VDP_DATA_PORT, 0x11223344); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102)); + write32(VDP_DATA_PORT, 0x55667788); + vdp_wait_for_fifo_empty(); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100)); + v0 = read16(VDP_DATA_PORT); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100)); + v1 = read16(VDP_DATA_PORT); + + VDP_setReg(VDP_AUTOINC, 2); + + expect(ok, v0, 0x8844); + expect(ok, v1, 0x0708); + return ok; +} + +static unused int t_vdp_128k_b16_inc(void) +{ + u32 v0, v1; + int ok = 1; + + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); + write32(VDP_DATA_PORT, 0x01020304); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000)); + write32(VDP_DATA_PORT, 0x05060708); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe)); + write32(VDP_DATA_PORT, 0x090a0b0c); + vdp_wait_for_fifo_empty(); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K); + write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd + write16(VDP_DATA_PORT, 0x1122); + vdp_wait_for_fifo_empty(); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0)); + v0 = read32(VDP_DATA_PORT); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000)); + v1 = read32(VDP_DATA_PORT); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0)); + write32(VDP_DATA_PORT, 0); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000)); + write32(VDP_DATA_PORT, 0); + + expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere? + expect(ok, v1, 0x05060708); + return ok; +} + +static int t_vdp_reg_cmd(void) +{ + u32 v0; + int ok = 1; + + VDP_setReg(VDP_AUTOINC, 0); + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); + write32(VDP_DATA_PORT, 0x01020304); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + write32(VDP_DATA_PORT, 0x05060708); + + VDP_setReg(VDP_AUTOINC, 2); + write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100)); + v0 = read16(VDP_DATA_PORT); + + expect(ok, v0, 0x0304); + return ok; +} + +static int t_vdp_sr_vb(void) +{ + u16 sr[4]; + int ok = 1; + + while (read8(VDP_HV_COUNTER) != 242) + ; + sr[0] = read16(VDP_CTRL_PORT); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD); + sr[1] = read16(VDP_CTRL_PORT); + while (read8(VDP_HV_COUNTER) != 4) + ; + sr[2] = read16(VDP_CTRL_PORT); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + sr[3] = read16(VDP_CTRL_PORT); + + expect_bits(ok, sr[0], SR_VB, SR_VB); + expect_bits(ok, sr[1], SR_VB, SR_VB); + expect_bits(ok, sr[2], SR_VB, SR_VB); + expect_bits(ok, sr[3], 0, SR_VB); + return ok; +} + /* z80 tests assume busreq state */ static int t_z80mem_long_mirror(void) { @@ -755,6 +943,27 @@ static int t_z80mem_long_mirror(void) return ok; } +static int t_z80mem_noreq_w(void) +{ + u8 *zram = (u8 *)0xa00000; + int ok = 1; + + write8(&zram[0x1100], 0x11); + mem_barrier(); + write16(0xa11100, 0x000); + write8(&zram[0x1100], 0x22); + mem_barrier(); + + write16(0xa11100, 0x100); + while (read16(0xa11100) & 0x100) + ; + + expect(ok, zram[0x1100], 0x11); + return ok; +} + +#define Z80_CP_CYCLES(b) (118 + ((b) - 1) * 21 + 26 + 17) + static int t_z80mem_vdp_r(void) { u8 *zram = (u8 *)0xa00000; @@ -765,22 +974,22 @@ static int t_z80mem_vdp_r(void) write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100)); zram[0x1000] = 1; // cp - zram[0x1001] = 2; // len write16_z80le(&zram[0x1002], 0x7f00); // src - write16_z80le(&zram[0x1004], 0x1006); // dst - zram[0x1006] = zram[0x1007] = zram[0x1008] = 0x5a; + write16_z80le(&zram[0x1004], 0x1100); // dst + write16_z80le(&zram[0x1006], 2); // len + zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a; mem_barrier(); write16(0xa11100, 0x000); - burn10((98 + 40*2 + 27) * 15 / 7 * 2 / 10); + burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10); write16(0xa11100, 0x100); while (read16(0xa11100) & 0x100) ; expect(ok, zram[0x1000], 0); - expect(ok, zram[0x1006], 0x11); - expect(ok, zram[0x1007], 0x44); - expect(ok, zram[0x1008], 0x5a); + expect(ok, zram[0x1100], 0x11); + expect(ok, zram[0x1101], 0x44); + expect(ok, zram[0x1102], 0x5a); return ok; } @@ -793,16 +1002,17 @@ static unused int t_z80mem_vdp_w(void) write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); write32(VDP_DATA_PORT, 0x11223344); write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); + vdp_wait_for_fifo_empty(); zram[0x1000] = 1; // cp - zram[0x1001] = 2; // len - write16_z80le(&zram[0x1002], 0x1006); // src + write16_z80le(&zram[0x1002], 0x1100); // src write16_z80le(&zram[0x1004], 0x7f00); // dst - zram[0x1006] = 0x55; - zram[0x1007] = 0x66; + write16_z80le(&zram[0x1006], 2); // len + zram[0x1100] = 0x55; + zram[0x1101] = 0x66; mem_barrier(); write16(0xa11100, 0x000); - burn10((98 + 40*2 + 27) * 15 / 7 * 2 / 10); + burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10); write16(0xa11100, 0x100); while (read16(0xa11100) & 0x100) @@ -816,25 +1026,740 @@ static unused int t_z80mem_vdp_w(void) return ok; } +static int t_tim_loop(void) +{ + u8 vcnt; + int ok = 1; + + vdp_wait_for_line_0(); + burn10(488*220/10); + vcnt = read8(VDP_HV_COUNTER); + mem_barrier(); + + //expect_range(ok, vcnt, 0x80, 0x80); + expect(ok, vcnt, 223); + return ok; +} + +#define Z80_RD_V_CYCLES(b) (132 + (b) * 38 + 50 + 17) + +// 80 80 91 95-96 +static void z80_read_loop(u8 *zram, u16 src) +{ + const int pairs = 512 + 256; + + zram[0x1000] = 2; // read loop, save vcnt + write16_z80le(&zram[0x1002], src); // src + write16_z80le(&zram[0x1004], 0x1100); // vcnt dst + write16_z80le(&zram[0x1006], pairs); // reads/2 + zram[0x1100] = 0; + mem_barrier(); + + vdp_wait_for_line_0(); + write16(0xa11100, 0x000); + burn10(Z80_RD_V_CYCLES(pairs) * 15 / 7 * 4 / 10); + + write16(0xa11100, 0x100); + while (read16(0xa11100) & 0x100) + ; +} + +static int t_tim_z80_ram(void) +{ + u8 *zram = (u8 *)0xa00000; + int ok = 1; + + z80_read_loop(zram, 0); + + expect(ok, zram[0x1000], 0); + expect_range(ok, zram[0x1100], 0x80, 0x80); + return ok; +} + +static int t_tim_z80_ym(void) +{ + u8 *zram = (u8 *)0xa00000; + int ok = 1; + + z80_read_loop(zram, 0x4000); + + expect(ok, zram[0x1000], 0); + expect_range(ok, zram[0x1100], 0x80, 0x80); + return ok; +} + +static int t_tim_z80_vdp(void) +{ + u8 *zram = (u8 *)0xa00000; + int ok = 1; + + z80_read_loop(zram, 0x7f08); + + expect(ok, zram[0x1000], 0); +#ifndef PICO + expect_range(ok, zram[0x1100], 0x91, 0x91); +#else + expect_range(ok, zram[0x1100], 0x8e, 0x91); +#endif + return ok; +} + +static int t_tim_z80_bank_rom(void) +{ + u8 *zram = (u8 *)0xa00000; + int i, ok = 1; + + for (i = 0; i < 17; i++) + write8(0xa06000, 0); // bank 0 + + z80_read_loop(zram, 0x8000); + + expect(ok, zram[0x1000], 0); +#ifndef PICO + expect_range(ok, zram[0x1100], 0x95, 0x96); +#else + expect_range(ok, zram[0x1100], 0x93, 0x96); +#endif + return ok; +} + +/* borderline too slow */ +#if 0 +static void test_vcnt_vb(void) +{ + const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter + u32 *ram = (u32 *)0xff0000; + u16 vcnt, vcnt_expect = 0; + u16 sr, count = 0; + u32 val, old; + + vdp_wait_for_line_0(); + old = read32(srhv); + *ram++ = old; + for (;;) { + val = read32(srhv); + vcnt = val & 0xff00; + if (vcnt == vcnt_expect) + continue; + sr = val >> 16; + if (vcnt == 0 && !(sr & SR_VB)) // not VB + break; // wrapped to start of frame +// count++; + vcnt_expect += 0x100; + if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) { + old = val; + continue; + } + // should have a vcnt jump here + *ram++ = old; + *ram++ = val; + vcnt_expect = vcnt; + old = val; + } + *ram++ = val; + *ram = count; + mem_barrier(); +} +#endif + +static int t_tim_vcnt(void) +{ + const u32 *ram32 = (u32 *)0xff0000; + const u8 *ram = (u8 *)0xff0000; + u8 pal = read8(0xa10001) & 0x40; + u8 vc_jmp_b = pal ? 0x02 : 0xea; + u8 vc_jmp_a = pal ? 0xca : 0xe5; + u16 lines = pal ? 313 : 262; + int ok = 1; + + test_vcnt_vb(); + expect(ok, ram[0*4+2], 0); // line 0 + expect_bits(ok, ram[0*4+1], 0, SR_VB); + expect(ok, ram[1*4+2], 223); // last no blank + expect_bits(ok, ram[1*4+1], 0, SR_VB); + expect(ok, ram[2*4+2], 224); // 1st blank + expect_bits(ok, ram[2*4+1], SR_VB, SR_VB); + expect(ok, ram[3*4+2], vc_jmp_b); // before jump + expect_bits(ok, ram[3*4+1], SR_VB, SR_VB); + expect(ok, ram[4*4+2], vc_jmp_a); // after jump + expect_bits(ok, ram[4*4+1], SR_VB, SR_VB); + expect(ok, ram[5*4+2], 0xfe); // before vb clear + expect_bits(ok, ram[5*4+1], SR_VB, SR_VB); + expect(ok, ram[6*4+2], 0xff); // after vb clear + expect_bits(ok, ram[6*4+1], 0, SR_VB); + expect(ok, ram[7*4+2], 0); // next line 0 + expect_bits(ok, ram[7*4+1], 0, SR_VB); + expect(ok, ram32[8], lines - 1); + return ok; +} + +static int t_tim_hblank_h40(void) +{ + const u8 *r = (u8 *)0xff0000; + int ok = 1; + + test_hb(); + + // set: 0-2 + expect_bits(ok, r[2], SR_HB, SR_HB); + expect_bits(ok, r[5], SR_HB, SR_HB); + // + expect_bits(ok, r[7], SR_HB, SR_HB); + // clear: 8-11 + expect_bits(ok, r[12], 0, SR_HB); + return ok; +} + +static int t_tim_hblank_h32(void) +{ + const u8 *r = (u8 *)0xff0000; + int ok = 1; + + VDP_setReg(VDP_MODE4, 0x00); + test_hb(); + VDP_setReg(VDP_MODE4, 0x81); + +#ifndef PICO + expect_bits(ok, r[0], 0, SR_HB); +#endif + // set: 1-4 + expect_bits(ok, r[4], SR_HB, SR_HB); + expect_bits(ok, r[5], SR_HB, SR_HB); + // + expect_bits(ok, r[8], SR_HB, SR_HB); + // clear: 9-11 + expect_bits(ok, r[12], 0, SR_HB); + return ok; +} + +static int t_tim_vdp_as_vram_w(void) +{ + int ok = 1; + u8 vcnt; + + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100)); + vdp_wait_for_line_0(); + write16_x16(VDP_DATA_PORT, 112*18 / 16, 0); + vcnt = read8(VDP_HV_COUNTER); + mem_barrier(); + + expect(ok, vcnt, 112*2-1); + return ok; +} + +static int t_tim_vdp_as_cram_w(void) +{ + int ok = 1; + u8 vcnt; + + write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0)); + vdp_wait_for_line_0(); + write16_x16(VDP_DATA_PORT, 112*18 / 16, 0); + vcnt = read8(VDP_HV_COUNTER); + mem_barrier(); + + setup_default_palette(); + +#ifndef PICO + expect(ok, vcnt, 112); +#else + expect_range(ok, vcnt, 111, 112); +#endif + return ok; +} + +struct irq_test { + u16 cnt; + union { + u16 hv; + u8 v; + } first, last; +}; + +static int t_irq_hint(void) +{ + struct irq_test *it = (void *)0xfff000; + int ok = 1; + + // for more fun, disable the display + VDP_setReg(VDP_MODE2, VDP_MODE2_MD); + + it->cnt = it->first.hv = it->last.hv = 0; + memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); + VDP_setReg(10, 0); + while (read8(VDP_HV_COUNTER) != 100) + ; + while (read8(VDP_HV_COUNTER) != 229) + ; + // take the pending irq + VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); + move_sr(0x2000); + burn10(488 * 2 / 10); + move_sr(0x2700); + expect(ok, it->first.v, 229); // pending irq trigger + expect(ok, it->cnt, 1); + + // count irqs + it->cnt = it->first.hv = it->last.hv = 0; + move_sr(0x2000); + while (read8(VDP_HV_COUNTER) != 4) + ; + while (read8(VDP_HV_COUNTER) != 228) + ; + move_sr(0x2700); + expect(ok, it->cnt, 225); + expect(ok, it->first.v, 0); + expect(ok, it->last.v, 224); + + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + + // detect reload line + it->cnt = it->first.hv = it->last.hv = 0; + VDP_setReg(10, 17); + move_sr(0x2000); + while (read16(VDP_CTRL_PORT) & 8) + /* blanking */; + VDP_setReg(10, 255); + while (read8(VDP_HV_COUNTER) != 228) + ; + move_sr(0x2700); + expect(ok, it->cnt, 1); + expect(ok, it->first.v, 17); + expect(ok, it->last.v, 17); + + VDP_setReg(VDP_MODE1, VDP_MODE1_PS); + + return ok; +} + +static int t_irq_ack_v_h(void) +{ + u16 *ram = (u16 *)0xfff000; + u8 *ram8 = (u8 *)0xfff000; + u16 s0, s1, s2; + int ok = 1; + + ram[0] = ram[1] = ram[2] = + ram[4] = ram[5] = ram[6] = 0; + memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); + memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); + VDP_setReg(10, 0); + /* ensure hcnt reload */ + while (!(read16(VDP_CTRL_PORT) & 8)) + /* not blanking */; + while (read16(VDP_CTRL_PORT) & 8) + /* blanking */; + VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0); + while (read8(VDP_HV_COUNTER) != 100) + ; + while (read8(VDP_HV_COUNTER) != 226) + ; + s0 = read16(VDP_CTRL_PORT); + s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT); + burn10(666 / 10); + s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT); + burn10(488 / 10); + move_sr(0x2700); + VDP_setReg(VDP_MODE1, VDP_MODE1_PS); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + + expect(ok, ram[4], 1); // vint count + expect(ok, ram8[10], 226); // vint line + expect(ok, ram[0], 1); // hint count + expect(ok, ram8[2], 228); // hint line + expect_bits(ok, s0, SR_F, SR_F); + expect_bits(ok, s1, 0, SR_F); + expect_bits(ok, s2, 0, SR_F); + return ok; +} + +static int t_irq_ack_v_h_2(void) +{ + u16 *ram = (u16 *)0xfff000; + u8 *ram8 = (u8 *)0xfff000; + u16 s0, s1; + int ok = 1; + + ram[0] = ram[1] = ram[2] = + ram[4] = ram[5] = ram[6] = 0; + memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); + memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); + VDP_setReg(10, 0); + while (read8(VDP_HV_COUNTER) != 100) + ; + while (read8(VDP_HV_COUNTER) != 226) + ; + s0 = read16(VDP_CTRL_PORT); + test_v_h_2(); + s1 = read16(VDP_CTRL_PORT); + VDP_setReg(VDP_MODE1, VDP_MODE1_PS); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + + expect(ok, ram[4], 2); // vint count + expect(ok, ram8[10], 226); // vint line + expect(ok, ram[0], 1); // hint count + expect(ok, ram8[2], 227); // hint line + expect_bits(ok, s0, SR_F, SR_F); + expect_bits(ok, s1, 0, SR_F); + return ok; +} + +static int t_irq_ack_h_v(void) +{ + u16 *ram = (u16 *)0xfff000; + u8 *ram8 = (u8 *)0xfff000; + u16 s0, s1, s[4]; + int ok = 1; + + ram[0] = ram[1] = ram[2] = + ram[4] = ram[5] = ram[6] = 0; + memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); + memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); + VDP_setReg(10, 0); + while (read8(VDP_HV_COUNTER) != 100) + ; + while (read8(VDP_HV_COUNTER) != 226) + ; + s0 = read16(VDP_CTRL_PORT); + VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1); + move_sr(0x2000); + burn10(666 / 10); + s1 = read16(VDP_CTRL_PORT); + write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8) + | VDP_MODE2_MD | VDP_MODE2_IE0, s); + move_sr(0x2700); + VDP_setReg(VDP_MODE1, VDP_MODE1_PS); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + + expect(ok, ram[0], 1); // hint count + expect(ok, ram8[2], 226); // hint line + expect(ok, ram[4], 1); // vint count + expect(ok, ram8[10], 228); // vint line + expect_bits(ok, s0, SR_F, SR_F); + expect_bits(ok, s1, SR_F, SR_F); + expect_bits(ok, s[0], SR_F, SR_F); + expect_bits(ok, s[1], SR_F, SR_F); + expect_bits(ok, s[2], 0, SR_F); + expect_bits(ok, s[3], 0, SR_F); + return ok; +} + +static int t_irq_ack_h_v_2(void) +{ + u16 *ram = (u16 *)0xfff000; + u8 *ram8 = (u8 *)0xfff000; + u16 s0, s1; + int ok = 1; + + ram[0] = ram[1] = ram[2] = + ram[4] = ram[5] = ram[6] = 0; + memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint); + memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint); + VDP_setReg(10, 0); + while (read8(VDP_HV_COUNTER) != 100) + ; + while (read8(VDP_HV_COUNTER) != 226) + ; + s0 = read16(VDP_CTRL_PORT); + test_h_v_2(); + s1 = read16(VDP_CTRL_PORT); + VDP_setReg(VDP_MODE1, VDP_MODE1_PS); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); + + expect(ok, ram[0], 2); // hint count + expect(ok, ram8[2], 226); // hint first line + expect(ok, ram8[4], 226); // hint last line + expect(ok, ram[4], 0); // vint count + expect(ok, ram8[10], 0); // vint line + expect_bits(ok, s0, SR_F, SR_F); + expect_bits(ok, s1, 0, SR_F); + return ok; +} + +static void t_irq_f_flag(void) +{ + memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint); + memset_((void *)0xff0000, 0, 10); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP); + test_f(); + VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); +} + +static int t_irq_f_flag_h40(void) +{ + u8 f, *r = (u8 *)0xff0000; + int ok = 1; + + t_irq_f_flag(); + + expect_bits(ok, r[0], 0, SR_F); + expect_bits(ok, r[1], 0, SR_F); + expect_bits(ok, r[2], 0, SR_F); + // hits 1-3 times in range 3-9, usually ~5 + f = r[3] | r[4] | r[5] | r[6] | r[7]; + + expect_bits(ok, r[10], 0, SR_F); + expect_bits(ok, r[11], 0, SR_F); + expect_bits(ok, f, SR_F, SR_F); + return ok; +} + +static int t_irq_f_flag_h32(void) +{ + u8 f, *r = (u8 *)0xff0000; + int ok = 1; + + VDP_setReg(VDP_MODE4, 0x00); + t_irq_f_flag(); + VDP_setReg(VDP_MODE4, 0x81); + + expect_bits(ok, r[0], 0, SR_F); + expect_bits(ok, r[1], 0, SR_F); + // hits 1-3 times in range 2-7, usually 3 + f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7]; + + expect_bits(ok, r[8], 0, SR_F); + expect_bits(ok, r[9], 0, SR_F); + expect_bits(ok, r[10], 0, SR_F); + expect_bits(ok, r[11], 0, SR_F); + expect_bits(ok, f, SR_F, SR_F); + return ok; +} + +// 32X + +static int t_32x_init(void) +{ + void (*do_32x_enable)(void) = (void *)0xff0040; + u32 M_OK = MKLONG('M','_','O','K'); + u32 S_OK = MKLONG('S','_','O','K'); + u32 *r = (u32 *)0xa15100; + u16 *r16 = (u16 *)r; + int i, ok = 1; + + //v1070 = read32(0x1070); + + /* what does REN mean exactly? + * Seems to be sometimes clear after reset */ + for (i = 0; i < 1000000; i++) + if (read16(r16) & 0x80) + break; + expect(ok, r16[0x00/2], 0x82); + expect(ok, r16[0x02/2], 0); + expect(ok, r16[0x04/2], 0); + expect(ok, r16[0x06/2], 0); + expect(ok, r[0x14/4], 0); + expect(ok, r[0x18/4], 0); + expect(ok, r[0x1c/4], 0); + write32(&r[0x20/4], 0); // master resp + write32(&r[0x24/4], 0); // slave resp + write32(&r[0x28/4], 0); + write32(&r[0x2c/4], 0); + + // could just set RV, but BIOS reads ROM, so can't + memcpy_(do_32x_enable, x32x_enable, + x32x_enable_end - x32x_enable); + do_32x_enable(); + + expect(ok, r16[0x00/2], 0x83); + expect(ok, r16[0x02/2], 0); + expect(ok, r16[0x04/2], 0); + expect(ok, r16[0x06/2], 1); // RV + expect(ok, r[0x14/4], 0); + expect(ok, r[0x18/4], 0); + expect(ok, r[0x1c/4], 0); + expect(ok, r[0x20/4], M_OK); + while (!read16(&r16[0x24/2])) + ; + expect(ok, r[0x24/4], S_OK); + write32(&r[0x20/4], 0); + return ok; +} + +static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave) +{ + u16 v, *r = (u16 *)0xa15120; + u16 cmd_s = cmd | (is_slave << 15); + int i; + + write32(&r[4/2], a0); + write32(&r[8/2], a1); + mem_barrier(); + write16(r, cmd_s); + mem_barrier(); + for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++) + burn10(1); + if (v != 0) { + printf("cmd clr: %x\n", v); + mem_barrier(); + printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]); + write16(r, 0); + } + v = read16(&r[1]); + if (v != 0) { + printf("cmd err: %x\n", v); + write16(&r[1], 0); + } +} + +static int t_32x_echo(void) +{ + u16 *r = (u16 *)0xa15120; + int ok = 1; + + x32_cmd(CMD_ECHO, 0x12340000, 0, 0); + expect(ok, r[0x06/2], 0x1234); + x32_cmd(CMD_ECHO, 0x23450000, 0, 1); + expect(ok, r[0x06/2], 0xa345); + return ok; +} + +static int t_32x_md_bios(void) +{ + void (*do_call_c0)(int a, int d) = (void *)0xff0040; + u8 *rmb = (u8 *)0xff0000; + u32 *rl = (u32 *)0; + int ok = 1; + + memcpy_(do_call_c0, test_32x_b_c0, + test_32x_b_c0_end - test_32x_b_c0); + write8(rmb, 0); + do_call_c0(0xff0000, 0x5a); + + expect(ok, rmb[0], 0x5a); + expect(ok, rl[0x04/4], 0x880200); + return ok; +} + +static int t_32x_md_rom(void) +{ + u32 *rl = (u32 *)0; + int ok = 1; + + expect(ok, rl[0x004/4], 0x880200); + expect(ok, rl[0x100/4], 0x53454741); + expect(ok, rl[0x70/4], 0); + write32(&rl[0x70/4], 0xa5123456); + write32(&rl[0x78/4], ~0); + mem_barrier(); + expect(ok, rl[0x78/4], 0x8802ae); + expect(ok, rl[0x70/4], 0xa5123456); + //expect(ok, rl[0x1070/4], v1070); + write32(&rl[0x70/4], 0); + // with RV 0x880000/0x900000 hangs, can't test + return ok; +} + +static int t_32x_md_fb(void) +{ + u8 *fbb = (u8 *)0x840000; + u16 *fbw = (u16 *)fbb; + u32 *fbl = (u32 *)fbb; + u8 *fob = (u8 *)0x860000; + u16 *fow = (u16 *)fob; + u32 *fol = (u32 *)fob; + int ok = 1; + + fbl[0] = 0x12345678; + fol[1] = 0x89abcdef; + mem_barrier(); + expect(ok, fbw[1], 0x5678); + expect(ok, fow[2], 0x89ab); + fbb[0] = 0; + fob[1] = 0; + fbw[1] = 0; + fow[2] = 0; + fow[3] = 1; + mem_barrier(); + fow[3] = 0x200; + mem_barrier(); + expect(ok, fol[0], 0x12340000); + expect(ok, fbl[1], 0x89ab0201); + return ok; +} + +static int t_32x_sh_fb(void) +{ + u32 *fbl = (u32 *)0x840000; + int ok = 1; + + fbl[0] = 0x12345678; + fbl[1] = 0x89abcdef; + mem_barrier(); + write8(0xa15100, 0x80); // FM=1 + x32_cmd(CMD_WRITE8, 0x24000000, 0, 0); + x32_cmd(CMD_WRITE8, 0x24020001, 0, 0); + x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); + x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); + x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1); + write8(0xa15100, 0x00); // FM=0 + mem_barrier(); + expect(ok, fbl[0], 0x12340000); + expect(ok, fbl[1], 0x5aabcda5); + return ok; +} + +enum { + T_MD = 0, + T_32 = 1, // 32X +}; + static const struct { + u8 type; int (*test)(void); const char *name; } g_tests[] = { - { t_dma_zero_wrap, "dma zero len + wrap" }, - { t_dma_zero_fill, "dma zero len + fill" }, - { t_dma_ram_wrap, "dma ram wrap" }, - { t_dma_multi, "dma multi" }, - { t_dma_cram_wrap, "dma cram wrap" }, - { t_dma_vsram_wrap, "dma vsram wrap" }, - { t_dma_and_data, "dma and data" }, - { t_dma_fill3_odd, "dma fill3 odd" }, - { t_dma_fill3_even, "dma fill3 even" }, - // { t_dma_fill3_vsram, "dma fill3 vsram" }, // later - { t_dma_fill_dis, "dma fill disabled" }, - { t_dma_fill_src, "dma fill src incr" }, - { t_z80mem_long_mirror, "z80 ram long mirror" }, - { t_z80mem_vdp_r, "z80 vdp read" }, + { T_MD, t_dma_zero_wrap, "dma zero len + wrap" }, + { T_MD, t_dma_zero_fill, "dma zero len + fill" }, + { T_MD, t_dma_ram_wrap, "dma ram wrap" }, + { T_MD, t_dma_multi, "dma multi" }, + { T_MD, t_dma_cram_wrap, "dma cram wrap" }, + { T_MD, t_dma_vsram_wrap, "dma vsram wrap" }, + { T_MD, t_dma_and_data, "dma and data" }, + { T_MD, t_dma_short_cmd, "dma short cmd" }, + { T_MD, t_dma_fill3_odd, "dma fill3 odd" }, + { T_MD, t_dma_fill3_even, "dma fill3 even" }, +#ifndef PICO // later + { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" }, +#endif + { T_MD, t_dma_fill_dis, "dma fill disabled" }, + { T_MD, t_dma_fill_src, "dma fill src incr" }, + { T_MD, t_dma_128k, "dma 128k mode" }, + { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" }, + // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery + { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" }, + { T_MD, t_vdp_sr_vb, "vdp status reg vb" }, + { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" }, + { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" }, + { T_MD, t_z80mem_vdp_r, "z80 vdp read" }, // { t_z80mem_vdp_w, "z80 vdp write" }, // hang + { T_MD, t_tim_loop, "time loop" }, + { T_MD, t_tim_z80_ram, "time z80 ram" }, + { T_MD, t_tim_z80_ym, "time z80 ym2612" }, + { T_MD, t_tim_z80_vdp, "time z80 vdp" }, + { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" }, + { T_MD, t_tim_vcnt, "time V counter" }, + { T_MD, t_tim_hblank_h40, "time hblank h40" }, + { T_MD, t_tim_hblank_h32, "time hblank h32" }, + { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" }, + { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" }, + { T_MD, t_irq_hint, "irq4 / line" }, + { T_MD, t_irq_ack_v_h, "irq ack v-h" }, + { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" }, + { T_MD, t_irq_ack_h_v, "irq ack h-v" }, + { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" }, + { T_MD, t_irq_f_flag_h40, "irq f flag h40" }, + { T_MD, t_irq_f_flag_h32, "irq f flag h32" }, + + // the first one enables 32X, so must be kept + // all tests assume RV=1 FM=0 + { T_32, t_32x_init, "32x init" }, + { T_32, t_32x_echo, "32x echo" }, + { T_32, t_32x_md_bios, "32x md bios" }, + { T_32, t_32x_md_rom, "32x md rom" }, + { T_32, t_32x_md_fb, "32x md fb" }, + { T_32, t_32x_sh_fb, "32x sh fb" }, }; static void setup_z80(void) @@ -855,16 +1780,54 @@ static void setup_z80(void) write8(&zram[i], z80_test[i]); for (i = 0x1000; i < 0x1007; i++) write8(&zram[i], 0); + + // reset + write16(0xa11200, 0x000); + write16(0xa11100, 0x000); + burn10(1); + write16(0xa11200, 0x100); + burn10(1); + + // take back the bus + write16(0xa11100, 0x100); + while (read16(0xa11100) & 0x100) + ; +} + +static void wait_next_vsync(void) +{ + while (read16(VDP_CTRL_PORT) & 8) + /* blanking */; + while (!(read16(VDP_CTRL_PORT) & 8)) + /* not blanking */; +} + +static unused int hexinc(char *c) +{ + (*c)++; + if (*c > 'f') { + *c = '0'; + return 1; + } + if (*c == '9' + 1) + *c = 'a'; + return 0; } int main() { int passed = 0; + int skipped = 0; + int have_32x; int ret; + u8 v8; int i; setup_z80(); + /* io */ + write8(0xa10009, 0x40); + /* setup VDP */ while (read16(VDP_CTRL_PORT) & 2) ; @@ -921,33 +1884,129 @@ int main() VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP); - printf("\n"); - printf("MD version: %02x\n", read8(0xa10001)); + have_32x = read32(0xa130ec) == MKLONG('M','A','R','S'); + v8 = read8(0xa10001); + printf("MD version: %02x %s %s %s\n", v8, + (v8 & 0x80) ? "world" : "jap", + (v8 & 0x40) ? "pal" : "ntsc", + have_32x ? "32X" : ""); for (i = 0; i < ARRAY_SIZE(g_tests); i++) { // print test number if we haven't scrolled away if (printf_ypos < CSCREEN_H) { int old_ypos = printf_ypos; printf_ypos = 0; - text_pal = 0; printf("%02d/%02d", i, ARRAY_SIZE(g_tests)); printf_ypos = old_ypos; printf_xpos = 0; } - text_pal = 2; + if ((g_tests[i].type & T_32) && !have_32x) { + skipped++; + continue; + } ret = g_tests[i].test(); - if (ret != 1) + if (ret != 1) { + text_pal = 2; printf("failed %d: %s\n", i, g_tests[i].name); + text_pal = 0; + } else passed++; } text_pal = 0; - printf("%d/%d passed.\n", passed, ARRAY_SIZE(g_tests)); + printf("%d/%d passed, %d skipped.\n", + passed, ARRAY_SIZE(g_tests), skipped); printf_ypos = 0; printf(" "); + while (!(get_input() & BTNM_A)) + wait_next_vsync(); + + + { + char c[3] = { '0', '0', '0' }; + short hscroll = 0, vscroll = 0; + short hsz = 1, vsz = 0; + short cellmode = 0; + + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE)); + +#if 0 + for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) { + write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32); + c[0]++; + if (c[0] == 'z' + 1) + c[0] = 'a'; + } +#else + for (i = 0; i < 8 * 1024 / 2 / 4; i++) { + write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32); + write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32); + write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32); + write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32); + if (hexinc(&c[0])) + if (hexinc(&c[1])) + hexinc(&c[2]); + } +#endif + while (get_input() & BTNM_A) + wait_next_vsync(); + + wait_next_vsync(); + for (;;) { + int b = get_input(); + + if (b & BTNM_C) { + hscroll = 1, vscroll = -1; + do { + wait_next_vsync(); + } while (get_input() & BTNM_C); + cellmode ^= 1; + } + if (b & (BTNM_L | BTNM_R | BTNM_C)) { + hscroll += (b & BTNM_L) ? 1 : -1; + write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL)); + write16(VDP_DATA_PORT, hscroll); + } + if (b & (BTNM_U | BTNM_D | BTNM_C)) { + vscroll += (b & BTNM_U) ? -1 : 1; + write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0)); + if (cellmode) { + int end = (int)vscroll + 21; + for (i = vscroll; i < end; i++) + write32(VDP_DATA_PORT, i << 17); + VDP_setReg(VDP_MODE3, 0x04); + } + else { + write16(VDP_DATA_PORT, vscroll); + VDP_setReg(VDP_MODE3, 0x00); + } + } + if (b & BTNM_A) { + hsz = (hsz + 1) & 3; + do { + wait_next_vsync(); + } while (get_input() & BTNM_A); + } + if (b & BTNM_B) { + vsz = (vsz + 1) & 3; + do { + wait_next_vsync(); + } while (get_input() & BTNM_B); + } + VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz); + + printf_xpos = 1; + printf_ypos = 0; + text_pal = 1; + printf(" %d %d ", hsz, vsz); + + wait_next_vsync(); + } + } + for (;;) ;