X-Git-Url: https://notaz.gp2x.de/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=testpico%2Fmain.c;h=1d27128bceb9b0c8563fdfc1da264be4af9ae70f;hb=refs%2Fheads%2Fmaster;hp=9c07110576b0a6bdcabfbbe7be0443a9c7ac9cba;hpb=635f24506c5a883336e9028e0de7a4a5fb9b2226;p=megadrive.git

diff --git a/testpico/main.c b/testpico/main.c
index 9c07110..43da6e6 100644
--- a/testpico/main.c
+++ b/testpico/main.c
@@ -6,6 +6,7 @@
 #include <stdarg.h>
 #include "common.h"
 #include "asmtools.h"
+//#pragma GCC diagnostic ignored "-Wunused-function"
 
 #define VDP_DATA_PORT    0xC00000
 #define VDP_CTRL_PORT    0xC00004
@@ -231,6 +232,9 @@ static noinline int printf(const char *fmt, ...)
             for (j--; j >= 0; j--)
                 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
             break;
+        case 'c':
+            buf[d++] = va_arg(ap, int);
+            break;
         case 's':
             s = va_arg(ap, char *);
             while (*s && d < PRINTF_LEN)
@@ -342,10 +346,11 @@ void exception(const struct exc_frame *f)
         printf("  PC: %08x SR: %04x            \n", f->g.pc, f->g.sr);
         sp_add = 6;
     }
-    for (i = 0; i < 8; i++)
+    sp = (u32 *)(f->ar[7] + sp_add);
+    for (i = 0; i < 7; i++)
         printf("  D%d: %08x A%d: %08x    \n", i, f->dr[i], i, f->ar[i]);
+    printf("  D%d: %08x SP: %08x    \n", i, f->dr[i], (u32)sp);
     printf("                               \n");
-    sp = (u32 *)(f->ar[7] + sp_add);
     printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
     printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
 }
@@ -400,6 +405,14 @@ static void vdp_wait_for_line_0(void)
         ;
 }
 
+static void wait_next_vsync(void)
+{
+    while (read16(VDP_CTRL_PORT) & SR_VB)
+        /* blanking */;
+    while (!(read16(VDP_CTRL_PORT) & SR_VB))
+        /* not blanking */;
+}
+
 static void t_dma_zero_wrap_early(void)
 {
     const u32 *src = (const u32 *)0x3c0000;
@@ -437,12 +450,20 @@ static void t_dma_zero_fill_early(void)
     ram[3] = read32(VDP_DATA_PORT);
 }
 
+#define R_SKIP 0x5a5a
+
 #define expect(ok_, v0_, v1_) \
 do { if ((v0_) != (v1_)) { \
     printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
     ok_ = 0; \
 }} while (0)
 
+#define expect_sh2(ok_, sh2_, v0_, v1_) \
+do { if ((v0_) != (v1_)) { \
+    printf("%csh2: %08x %08x\n", sh2_ ? 's' : 'm', v0_, v1_); \
+    ok_ = 0; \
+}} while (0)
+
 #define expect_range(ok_, v0_, vmin_, vmax_) \
 do { if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
     printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
@@ -1409,19 +1430,34 @@ static int t_tim_ym_timerb_stop(void)
 
 static int t_tim_ym_timer_ab_sync(void)
 {
-    u16 v1, v2, v3, start, line_diff;
+    u16 v1, v2, v3, v4, v5, ln0, ln1, ln2;
     int ok = 1;
+
+    vdp_wait_for_line_0();
     v1 = test_ym_ab_sync();
-    start = get_line();
-    write8(0xa04001, 0x3f);   // clear
-    burn10(3420*11/7/10);     // ~11 scanlines
+
+    ln0 = get_line();
+    burn10(3420*15/7/10);     // ~15 scanlines
+    write8(0xa04001, 0x3f);   // clear, no reload
+    burn10(12);               // wait for busy to clear
     v2 = read8(0xa04000);
     v3 = test_ym_ab_sync2();
-    line_diff = get_line() - start;
+
+    ln1 = get_line();
+    burn10(3420*15/7/10);     // ~15 scanlines
+    v4 = test_ym_ab_sync2();
+
+    ln2 = get_line();
+    burn10(3420*30/7/10);     // ~35 scanlines
+    v5 = read8(0xa04000);
+
     expect(ok, v1, 3);
     expect(ok, v2, 0);
     expect(ok, v3, 3);
-    expect_range(ok, line_diff, 18, 19);
+    expect(ok, v4, 2);
+    expect(ok, v5, 0);
+    expect_range(ok, ln1-ln0, 18, 19);
+    expect_range(ok, ln2-ln1, 32, 34); // almost always 33
     return ok;
 }
 
@@ -1730,13 +1766,140 @@ static int t_irq_f_flag_h32(void)
 
 // 32X
 
+#define IRQ_CNT_FB_BASE 0x1ff00
+
+// see do_cmd()
+static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
+{
+    u16 v, *r = (u16 *)0xa15120;
+    u8 *r8 = (u8 *)r;
+    u16 cmd_s = cmd | (is_slave << 15);
+    int i;
+
+    write32(&r[4/2], a0);
+    write32(&r[8/2], a1);
+    mem_barrier();
+    write16(r, cmd_s);
+    mem_barrier();
+    for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
+        burn10(1);
+    if (v != 0) {
+        printf("cmd clr: %x\n", v);
+        mem_barrier();
+        printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
+        write16(r, 0);
+    }
+    v = read16(&r[1]);
+    if (v != 0) {
+        printf("cmd err: %x\n", v);
+        write16(&r[1], 0);
+    }
+}
+
+static int t_32x_reset_btn(void)
+{
+    void (*do_32x_disable)(void) = (void *)0xff0040;
+    u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+    u16 *m_icnt = (u16 *)fbl_icnt;
+    u16 *s_icnt = m_icnt + 8;
+    u32 *r32 = (u32 *)0xa15100;
+    u16 *r16 = (u16 *)r32, i, s;
+    u8 *r8 = (u8 *)r32;
+    u32 *rl = (u32 *)0;
+    int ok = 1;
+
+    if (!(read16(r16) & 1))
+        return R_SKIP;
+
+    expect(ok, r16[0x00/2], 0x8083);
+
+    write8(r8, 0x00); // FM=0
+    mem_barrier();
+    expect(ok, r16[0x00/2], 0x83);
+    expect(ok, r16[0x02/2], 0);
+    expect(ok, r16[0x04/2], 3);
+    expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
+    expect(ok, r32[0x08/4], 0x5a5a08);
+    expect(ok, r32[0x0c/4], 0x5a5a0c);
+    expect(ok, r16[0x10/2], 0x5a10);
+    expect(ok, r32[0x14/4], 0);
+    expect(ok, r32[0x18/4], 0);
+    expect(ok, r32[0x1c/4], 0);
+    expect(ok, r32[0x20/4], 0x00005a20);
+    expect(ok, r32[0x24/4], 0x5a5a5a24);
+    expect(ok, r32[0x28/4], 0x5a5a5a28);
+    expect(ok, r32[0x2c/4], 0x075a5a2c); // 7 - last_irq_vec
+    if (!(r16[0x00/2] & 0x8000)) {
+        expect(ok, r8 [0x81], 1);
+        expect(ok, r16[0x82/2], 1);
+        expect(ok, r16[0x84/2], 0xff);
+        expect(ok, r16[0x86/2], 0xffff);
+        expect(ok, r16[0x88/2], 0);
+        expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
+        expect(ok, r16[0x8c/2], 0);
+        expect(ok, r16[0x8e/2], 0);
+        // setup vdp for t_32x_init
+        r8 [0x81] = 0;
+        r16[0x82/2] = r16[0x84/2] = r16[0x86/2] = 0;
+    }
+    r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
+    for (s = 0; s < 2; s++)
+    {
+        x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
+        expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
+        // t_32x_sh_defaults will test the other bits
+    }
+    // setup for t_32x_sh_defaults
+    x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
+    x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
+
+    for (i = 0; i < 7; i++) {
+        expect(ok, m_icnt[i], 0x100);
+        expect(ok, s_icnt[i], 0x100);
+    }
+    expect(ok, m_icnt[7], 0x101); // VRES happened
+    expect(ok, s_icnt[7], 0x100); // masked on slave
+
+    x32_cmd(CMD_GETSR, 0, 0, 1);
+    expect_sh2(ok, 1, r32[0x24/4] & ~1, 0xf0); // still masked
+    x32_cmd(CMD_SETSR, 0x10, 0, 1);
+    expect(ok, r16[0x00/2], 0x8083);
+    write8(r8, 0x00); // FM=0
+    mem_barrier();
+    expect(ok, m_icnt[7], 0x101);
+    expect(ok, s_icnt[7], 0x101);
+    expect(ok, r32[0x2c/4], 0x00070000); // 7 - last_irq_vec
+    r32[0x2c/4] = 0;
+
+    memcpy_(do_32x_disable, x32x_disable,
+            x32x_disable_end - x32x_disable);
+    do_32x_disable();
+
+    expect(ok, r16[0x00/2], 0x82);
+    expect(ok, r16[0x02/2], 0);
+    expect(ok, r16[0x04/2], 3);
+    expect(ok, r16[0x06/2], 0); // RV cleared by x32x_disable
+    expect(ok, r32[0x08/4], 0x5a5a08);
+    expect(ok, r32[0x0c/4], 0x5a5a0c);
+    expect(ok, r16[0x10/2], 0x5a10);
+    expect(ok, rl[0x04/4], 0x000800);
+
+    // setup for t_32x_init, t_32x_sh_defaults
+    r16[0x04/2] = 0;
+    r16[0x10/2] = 0x1234; // warm reset indicator
+    mem_barrier();
+    expect(ok, r16[0x06/2], 0); // RV
+    return ok;
+}
+
 static int t_32x_init(void)
 {
     void (*do_32x_enable)(void) = (void *)0xff0040;
     u32 M_OK = MKLONG('M','_','O','K');
     u32 S_OK = MKLONG('S','_','O','K');
-    u32 *r = (u32 *)0xa15100;
-    u16 *r16 = (u16 *)r;
+    u32 *r32 = (u32 *)0xa15100;
+    u16 *r16 = (u16 *)r32;
+    u8 *r8 = (u8 *)r32;
     int i, ok = 1;
 
     //v1070 = read32(0x1070);
@@ -1750,13 +1913,56 @@ static int t_32x_init(void)
     expect(ok, r16[0x02/2], 0);
     expect(ok, r16[0x04/2], 0);
     expect(ok, r16[0x06/2], 0);
-    expect(ok, r[0x14/4], 0);
-    expect(ok, r[0x18/4], 0);
-    expect(ok, r[0x1c/4], 0);
-    write32(&r[0x20/4], 0); // master resp
-    write32(&r[0x24/4], 0); // slave resp
-    write32(&r[0x28/4], 0);
-    write32(&r[0x2c/4], 0);
+    expect(ok, r8 [0x08], 0);
+    //expect(ok, r32[0x08/4], 0); // garbage 24bit
+    expect(ok, r8 [0x0c], 0);
+    //expect(ok, r32[0x0c/4], 0); // garbage 24bit
+    if (r16[0x10/2] != 0x1234)    // warm reset
+        expect(ok, r16[0x10/2], 0xffff);
+    expect(ok, r16[0x12/2], 0);
+    expect(ok, r32[0x14/4], 0);
+    expect(ok, r32[0x18/4], 0);
+    expect(ok, r32[0x1c/4], 0);
+    //expect(ok, r8 [0x81], 0); // VDP; hangs without ADEN
+    r32[0x20/4] = 0; // master resp
+    r32[0x24/4] = 0; // slave resp
+    r32[0x28/4] = 0;
+    r32[0x2c/4] = 0;
+
+    // check writable bits without ADEN
+    // 08,0c have garbage or old values (survive MD's power cycle)
+    write16(&r16[0x00/2], 0);
+    mem_barrier();
+    expect(ok, r16[0x00/2], 0x80);
+    write16(&r16[0x00/2], 0xfffe);
+    mem_barrier();
+    expect(ok, r16[0x00/2], 0x8082);
+    r16[0x00/2] = 0x82;
+    r16[0x02/2] = 0xffff;
+    r32[0x04/4] = 0xffffffff;
+    r32[0x08/4] = 0xffffffff;
+    r32[0x0c/4] = 0xffffffff;
+    r16[0x10/2] = 0xffff;
+    r32[0x14/4] = 0xffffffff;
+    r32[0x18/4] = 0xffffffff;
+    r32[0x1c/4] = 0xffffffff;
+    mem_barrier();
+    expect(ok, r16[0x00/2], 0x82);
+    expect(ok, r16[0x02/2], 0x03);
+    expect(ok, r16[0x04/2], 0x03);
+    expect(ok, r16[0x06/2], 0x07);
+    expect(ok, r32[0x08/4], 0x00fffffe);
+    expect(ok, r32[0x0c/4], 0x00ffffff);
+    expect(ok, r16[0x10/2], 0xfffc);
+    expect(ok, r32[0x14/4], 0);
+    expect(ok, r16[0x18/2], 0);
+    expect(ok, r16[0x1a/2], 0x0101);
+    expect(ok, r32[0x1c/4], 0);
+    r16[0x02/2] = 0;
+    r32[0x04/4] = 0;
+    r32[0x08/4] = 0;
+    r32[0x0c/4] = 0;
+    r16[0x1a/2] = 0;
 
     // could just set RV, but BIOS reads ROM, so can't
     memcpy_(do_32x_enable, x32x_enable,
@@ -1767,52 +1973,60 @@ static int t_32x_init(void)
     expect(ok, r16[0x02/2], 0);
     expect(ok, r16[0x04/2], 0);
     expect(ok, r16[0x06/2], 1); // RV
-    expect(ok, r[0x14/4], 0);
-    expect(ok, r[0x18/4], 0);
-    expect(ok, r[0x1c/4], 0);
-    expect(ok, r[0x20/4], M_OK);
+    expect(ok, r32[0x14/4], 0);
+    expect(ok, r32[0x18/4], 0);
+    expect(ok, r32[0x1c/4], 0);
+    expect(ok, r32[0x20/4], M_OK);
     while (!read16(&r16[0x24/2]))
         ;
-    expect(ok, r[0x24/4], S_OK);
-    write32(&r[0x20/4], 0);
-    return ok;
-}
-
-static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
-{
-    u16 v, *r = (u16 *)0xa15120;
-    u16 cmd_s = cmd | (is_slave << 15);
-    int i;
-
-    write32(&r[4/2], a0);
-    write32(&r[8/2], a1);
-    mem_barrier();
-    write16(r, cmd_s);
-    mem_barrier();
-    for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
-        burn10(1);
-    if (v != 0) {
-        printf("cmd clr: %x\n", v);
-        mem_barrier();
-        printf("c, e: %02x %02x\n", r[0x0c/2],  r[0x0e/2]);
-        write16(r, 0);
-    }
-    v = read16(&r[1]);
-    if (v != 0) {
-        printf("cmd err: %x\n", v);
-        write16(&r[1], 0);
+    expect(ok, r32[0x24/4], S_OK);
+    write32(&r32[0x20/4], 0);
+    if (!(r16[0x00/2] & 0x8000)) {
+        expect(ok, r8 [0x81], 0);
+        expect(ok, r16[0x82/2], 0);
+        expect(ok, r16[0x84/2], 0);
+        expect(ok, r16[0x86/2], 0);
+        //expect(ok, r16[0x88/2], 0); // triggers fill?
+        expect(ok, r8 [0x8b] & ~2, 0);
+        expect(ok, r16[0x8c/2], 0);
+        expect(ok, r16[0x8e/2], 0);
     }
+    return ok;
 }
 
 static int t_32x_echo(void)
 {
-    u16 *r = (u16 *)0xa15120;
+    u16 *r16 = (u16 *)0xa15100;
     int ok = 1;
 
+    r16[0x2c/2] = r16[0x2e/2] = 0;
     x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
-    expect(ok, r[0x06/2], 0x1234);
+    expect_sh2(ok, 0, r16[0x26/2], 0x1234);
     x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
-    expect(ok, r[0x06/2], 0xa345);
+    expect_sh2(ok, 1, r16[0x26/2], 0xa345);
+    expect(ok, r16[0x2c/2], 0); // no last_irq_vec
+    expect(ok, r16[0x2e/2], 0); // no exception_index
+    return ok;
+}
+
+static int t_32x_sh_defaults(void)
+{
+    u32 *r32 = (u32 *)0xa15120;
+    int ok = 1, s;
+
+    for (s = 0; s < 2; s++)
+    {
+        x32_cmd(CMD_READ32, 0x20004000, 0, s);
+        expect_sh2(ok, s, r32[0x04/4], 0x02000000); // ADEN
+        x32_cmd(CMD_READ32, 0x20004004, 0, s);
+        expect_sh2(ok, s, r32[0x04/4], 0x00004001); // Empty Rv
+        x32_cmd(CMD_READ32, 0x20004008, 0, s);
+        expect_sh2(ok, s, r32[0x04/4], 0);
+        x32_cmd(CMD_READ32, 0x2000400c, 0, s);
+        expect_sh2(ok, s, r32[0x04/4], 0);
+        x32_cmd(CMD_GETGBR, 0, 0, s);
+        expect_sh2(ok, s, r32[0x04/4], 0x20004000);
+    }
     return ok;
 }
 
@@ -1885,50 +2099,151 @@ static int t_32x_md_fb(void)
 static int t_32x_sh_fb(void)
 {
     u32 *fbl = (u32 *)0x840000;
+    u8 *r8 = (u8 *)0xa15100;
     int ok = 1;
 
+    if (read8(r8) & 0x80)
+        write8(r8, 0x00); // FM=0
     fbl[0] = 0x12345678;
     fbl[1] = 0x89abcdef;
     mem_barrier();
-    write8(0xa15100, 0x80); // FM=1
-    x32_cmd(CMD_WRITE8,  0x24000000, 0, 0);
-    x32_cmd(CMD_WRITE8,  0x24020001, 0, 0);
-    x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
-    x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
+    write8(r8, 0x80);     // FM=1
+    x32_cmd(CMD_WRITE8,  0x24000000, 0, 0); // should ignore
+    x32_cmd(CMD_WRITE8,  0x24020001, 0, 0); // ignore
+    x32_cmd(CMD_WRITE16, 0x24000002, 0, 0); // ok
+    x32_cmd(CMD_WRITE16, 0x24020000, 0, 0); // ignore
     x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
-    write8(0xa15100, 0x00); // FM=0
+    write8(r8, 0x00);     // FM=0
     mem_barrier();
     expect(ok, fbl[0], 0x12340000);
     expect(ok, fbl[1], 0x5aabcda5);
     return ok;
 }
 
-static int t_32x_disable(void)
+static int t_32x_irq(void)
 {
-    void (*do_32x_disable)(void) = (void *)0xff0040;
+    u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+    u16 *m_icnt = (u16 *)fbl_icnt;
+    u16 *s_icnt = m_icnt + 8;
     u32 *r = (u32 *)0xa15100;
     u16 *r16 = (u16 *)r;
-    u32 *rl = (u32 *)0;
-    int ok = 1;
+    u8 *r8 = (u8 *)r;
+    int ok = 1, i;
 
-    expect(ok, r16[0x00/2], 0x83);
+    write8(r, 0x00); // FM=0
+    r[0x2c/4] = 0;
+    mem_barrier();
+    for (i = 0; i < 8; i++)
+        write32(&fbl_icnt[i], 0);
+    mem_barrier();
+    write16(&r16[0x02/2], 0xfffd); // INTM+unused_bits
+    mem_barrier();
+    expect(ok, r16[0x02/2], 1);
+    x32_cmd(CMD_WRITE8, 0x20004001, 2, 0); // unmask cmd
+    x32_cmd(CMD_WRITE8, 0x20004001, 2, 1); // unmask cmd slave
+    burn10(10);
+    write8(r, 0x00); // FM=0 (hangs without)
+    mem_barrier();
+    expect(ok, r16[0x02/2], 0);
+    expect(ok, r8 [0x2c], 4);
+    expect(ok, r8 [0x2d], 0);
+    expect(ok, r16[0x2e/2], 0); // no exception_index
+    expect(ok, m_icnt[4], 1);
+    expect(ok, s_icnt[4], 0);
+    write16(&r16[0x02/2], 0xaaaa); // INTS+unused_bits
+    mem_barrier();
+    expect(ok, r16[0x02/2], 2);
+    burn10(10);
+    mem_barrier();
+    expect(ok, r16[0x02/2], 0);
+    expect(ok, r8 [0x2c], 4);
+    expect(ok, r8 [0x2d], 4);
+    expect(ok, r16[0x2e/2], 0); // no exception_index
+    write8(r, 0x00); // FM=0
+    mem_barrier();
+    expect(ok, m_icnt[4], 1);
+    expect(ok, s_icnt[4], 1);
+    for (i = 0; i < 8; i++) {
+        if (i == 4)
+            continue;
+        expect(ok, m_icnt[i], 0);
+        expect(ok, s_icnt[i], 0);
+    }
+    return ok;
+}
 
-    memcpy_(do_32x_disable, x32x_disable,
-            x32x_disable_end - x32x_disable);
-    do_32x_disable();
+static int t_32x_reg_w(void)
+{
+    u32 *r32 = (u32 *)0xa15100;
+    u16 *r16 = (u16 *)r32, old;
+    int ok = 1;
 
-    expect(ok, r16[0x00/2], 0x82);
-    expect(ok, r16[0x02/2], 0);
-    expect(ok, r16[0x04/2], 0);
-    expect(ok, r16[0x06/2], 1); // RV
-    expect(ok, r[0x14/4], 0);
-    expect(ok, r[0x18/4], 0);
-    expect(ok, r[0x1c/4], 0);
-    expect(ok, rl[0x04/4], 0x000800);
+    r32[0x08/4] = ~0;
+    r32[0x0c/4] = ~0;
+    r16[0x10/2] = ~0;
+    mem_barrier();
+    expect(ok, r32[0x08/4], 0xfffffe);
+    expect(ok, r32[0x0c/4], 0xffffff);
+    expect(ok, r16[0x10/2], 0xfffc);
+    mem_barrier();
+    r32[0x08/4] = r32[0x0c/4] = 0;
+    r16[0x10/2] = 0;
+    old = r16[0x06/2];
+    x32_cmd(CMD_WRITE16, 0x20004006, ~old, 0);
+    expect(ok, r16[0x06/2], old);
+    return ok;
+}
 
-    write16(&r16[0x06/2], 0);   // can just set without ADEN
+// prepare for reset btn press tests
+static int t_32x_reset_prep(void)
+{
+    u32 *fbl = (u32 *)0x840000;
+    u32 *fbl_icnt = fbl + IRQ_CNT_FB_BASE / 4;
+    u32 *r32 = (u32 *)0xa15100;
+    u16 *r16 = (u16 *)r32;
+    u8 *r8 = (u8 *)r32;
+    int ok = 1, i;
+
+    expect(ok, r16[0x00/2], 0x83);
+    write8(r8, 0x00); // FM=0
+    r32[0x2c/4] = 0;
     mem_barrier();
-    expect(ok, r16[0x06/2], 0); // RV
+    expect(ok, r8[0x8b] & ~2, 0);
+    for (i = 0; i < 8; i++)
+        write32(&fbl_icnt[i], 0x01000100);
+    x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 0); // unmask cmd
+    x32_cmd(CMD_WRITE8, 0x20004001, 0x02, 1); // unmask slave
+    x32_cmd(CMD_SETSR, 0xf0, 0, 1);           // mask slave irqs (on the cpu)
+    burn10(10);
+    write8(r8, 0x00); // FM=0
+    expect(ok, r32[0x2c/4], 0);
+    mem_barrier();
+    for (i = 0; i < 8; i++)
+        expect(ok, fbl_icnt[i], 0x01000100);
+
+    r16[0x04/2] = 0xffff;
+    r32[0x08/4] = 0x5a5a5a08;
+    r32[0x0c/4] = 0x5a5a5a0c;
+    r16[0x10/2] = 0x5a10;
+    r32[0x20/4] = 0x00005a20; // no x32_cmd
+    r32[0x24/4] = 0x5a5a5a24;
+    r32[0x28/4] = 0x5a5a5a28;
+    r32[0x2c/4] = 0x5a5a5a2c;
+    if (!(r16[0x00/2] & 0x8000)) {
+        wait_next_vsync();
+        r16[0x8a/2] = 0x0001;
+        mem_barrier();
+        for (i = 0; i < 220/2; i++)
+            fbl[i] = 0;
+        r8 [0x81] = 1;
+        r16[0x82/2] = 0xffff;
+        r16[0x84/2] = 0xffff;
+        r16[0x86/2] = 0xffff;
+        r16[0x8a/2] = 0x0000;
+        r16[0x8c/2] = 0xffff;
+        r16[0x8e/2] = 0xffff;
+        r16[0x100/2] = 0;
+    }
     return ok;
 }
 
@@ -1942,6 +2257,9 @@ static const struct {
     int (*test)(void);
     const char *name;
 } g_tests[] = {
+    // this must be first to disable the 32x and restore the 68k vector table
+    { T_32, t_32x_reset_btn,       "32x resetbtn" },
+
     { T_MD, t_dma_zero_wrap,       "dma zero len + wrap" },
     { T_MD, t_dma_zero_fill,       "dma zero len + fill" },
     { T_MD, t_dma_ram_wrap,        "dma ram wrap" },
@@ -1993,11 +2311,14 @@ static const struct {
     // all tests assume RV=1 FM=0
     { T_32, t_32x_init,            "32x init" },
     { T_32, t_32x_echo,            "32x echo" },
+    { T_32, t_32x_sh_defaults,     "32x sh def" },
     { T_32, t_32x_md_bios,         "32x md bios" },
     { T_32, t_32x_md_rom,          "32x md rom" },
     { T_32, t_32x_md_fb,           "32x md fb" },
     { T_32, t_32x_sh_fb,           "32x sh fb" },
-    { T_32, t_32x_disable,         "32x disable" }, // must be last 32x
+    { T_32, t_32x_irq,             "32x irq" },
+    { T_32, t_32x_reg_w,           "32x reg w" },
+    { T_32, t_32x_reset_prep,      "32x rstprep" }, // must be last 32x
 };
 
 static void setup_z80(void)
@@ -2033,14 +2354,6 @@ static void setup_z80(void)
         ;
 }
 
-static void wait_next_vsync(void)
-{
-    while (read16(VDP_CTRL_PORT) & SR_VB)
-        /* blanking */;
-    while (!(read16(VDP_CTRL_PORT) & SR_VB))
-        /* not blanking */;
-}
-
 static unused int hexinc(char *c)
 {
     (*c)++;
@@ -2055,6 +2368,8 @@ static unused int hexinc(char *c)
 
 int main()
 {
+    void (*px32x_switch_rv)(short rv);
+    short (*pget_input)(void) = get_input;
     int passed = 0;
     int skipped = 0;
     int have_32x;
@@ -2125,13 +2440,19 @@ int main()
     VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
 
     have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
-    en_32x = have_32x && (read32(0xa15100) & 1);
+    en_32x = have_32x && (read16(0xa15100) & 1);
     v8 = read8(0xa10001);
     printf("MD version: %02x %s %s %s%s\n", v8,
         (v8 & 0x80) ? "world" : "jap",
         (v8 & 0x40) ? "pal" : "ntsc",
         have_32x ? "32X" : "",
         en_32x ? "+" : "");
+    printf("reset hvc %04x->%04x\n", read16(-4), read16(-2));
+
+    // sanity check
+    extern u32 sh2_test[];
+    if (sh2_test[0] != read32(0x3e0) || sh2_test[0x200/4] != read32(0x3e4))
+        printf("bad 0x3c0 tab\n");
 
     for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
         // print test number if we haven't scrolled away
@@ -2147,6 +2468,10 @@ int main()
             continue;
         }
         ret = g_tests[i].test();
+        if (ret == R_SKIP) {
+            skipped++;
+            continue;
+        }
         if (ret != 1) {
             text_pal = 2;
             printf("failed %d: %s\n", i, g_tests[i].name);
@@ -2163,14 +2488,32 @@ int main()
     printf_ypos = 0;
     printf("     ");
 
-    for (i = 0; i < 60*60 && !(get_input() & BTNM_A); i++)
-        wait_next_vsync();
+    if (have_32x && (read16(0xa15100) & 1)) {
+        u8 *p = (u8 *)0xff0040;
+        u32 len = x32x_switch_rv_end - x32x_switch_rv;
+        px32x_switch_rv = (void *)p; p += len;
+        memcpy_(px32x_switch_rv, x32x_switch_rv, len);
+
+        len = get_input_end - get_input_s;
+        pget_input = (void *)p; p += len;
+        memcpy_(pget_input, get_input_s, len);
+
+        // prepare for reset - run from 880xxx as the reset vector points there
+        // todo: broken printf
+        px32x_switch_rv(0);
+    }
+    for (i = 0; i < 60*60 && !(pget_input() & BTNM_A); i++) {
+        while (read16(VDP_CTRL_PORT) & SR_VB)
+            write16(-4, read16(VDP_HV_COUNTER)); /* blanking */
+        while (!(read16(VDP_CTRL_PORT) & SR_VB))
+            write16(-4, read16(VDP_HV_COUNTER)); /* not blanking */;
+    }
 #ifndef PICO
     // blank due to my lame tv being burn-in prone
     VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
 #endif
-    while (!(get_input() & BTNM_A))
-        burn10(488*100/10);
+    while (!(pget_input() & BTNM_A))
+        write16(-4, read16(VDP_HV_COUNTER));
     VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
 
 
@@ -2200,18 +2543,18 @@ int main()
                     hexinc(&c[2]);
         }
 #endif
-        while (get_input() & BTNM_A)
+        while (pget_input() & BTNM_A)
             wait_next_vsync();
 
         wait_next_vsync();
         for (;;) {
-            int b = get_input();
+            int b = pget_input();
 
             if (b & BTNM_C) {
                 hscroll = 1, vscroll = -1;
                 do {
                     wait_next_vsync();
-                } while (get_input() & BTNM_C);
+                } while (pget_input() & BTNM_C);
                 cellmode ^= 1;
             }
             if (b & (BTNM_L | BTNM_R | BTNM_C)) {
@@ -2237,13 +2580,13 @@ int main()
                 hsz = (hsz + 1) & 3;
                 do {
                     wait_next_vsync();
-                } while (get_input() & BTNM_A);
+                } while (pget_input() & BTNM_A);
             }
             if (b & BTNM_B) {
                 vsz = (vsz + 1) & 3;
                 do {
                     wait_next_vsync();
-                } while (get_input() & BTNM_B);
+                } while (pget_input() & BTNM_B);
             }
             VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);