#include "PicoInt.h"\r
\r
-// note: set SPLIT_MOVEL_PD to 0\r
-\r
typedef unsigned char u8;\r
\r
static unsigned int pppc, ops=0;\r
#define dprintf(f,...) printf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__)\r
\r
#if defined(EMU_C68K)\r
-#define other_get_sr() CycloneGetSr(&PicoCpuCM68k)\r
-#define other_dar(i) PicoCpuCM68k.d[i]\r
-#define other_osp PicoCpuCM68k.osp\r
-#define other_get_irq() PicoCpuCM68k.irq\r
-#define other_set_irq(irq) PicoCpuCM68k.irq=irq\r
-#define other_is_stopped() (PicoCpuCM68k.state_flags&1)\r
-#define other_is_tracing() ((PicoCpuCM68k.state_flags&2)?1:0)\r
+static struct Cyclone *currentC68k = NULL;\r
+#define other_set_sub(s) currentC68k=(s)?&PicoCpuCS68k:&PicoCpuCM68k;\r
+#define other_get_sr() CycloneGetSr(currentC68k)\r
+#define other_dar(i) currentC68k->d[i]\r
+#define other_osp currentC68k->osp\r
+#define other_get_irq() currentC68k->irq\r
+#define other_set_irq(i) currentC68k->irq=i\r
+#define other_is_stopped() (currentC68k->state_flags&1)\r
+#define other_is_tracing() ((currentC68k->state_flags&2)?1:0)\r
#elif defined(EMU_F68K)\r
#define other_set_sub(s) g_m68kcontext=(s)?&PicoCpuFS68k:&PicoCpuFM68k;\r
#define other_get_sr() g_m68kcontext->sr\r
static int otherRun(void)\r
{\r
#if defined(EMU_C68K)\r
- PicoCpuCM68k.cycles=1;\r
- CycloneRun(&PicoCpuCM68k);\r
- return 1-PicoCpuCM68k.cycles;\r
+ currentC68k->cycles=1;\r
+ CycloneRun(currentC68k);\r
+ return 1-currentC68k->cycles;\r
#elif defined(EMU_F68K)\r
return fm68k_emulate(1, 0);\r
#endif\r
have_illegal = 0;\r
m68ki_cpu.pc += 2;\r
#ifdef EMU_C68K\r
- PicoCpuCM68k.pc=PicoCpuCM68k.checkpc(PicoCpuCM68k.pc + 2);\r
+ currentC68k->pc=currentC68k->checkpc(currentC68k->pc + 2);\r
#endif\r
}\r
// hacks for test_misc2\r
// get out of "priviledge violation" loop\r
have_illegal = 1;\r
//m68ki_cpu.s_flag = SFLAG_SET;\r
- //PicoCpuCM68k.srh|=0x20;\r
+ //currentC68k->srh|=0x20;\r
}\r
\r
pppc = is_sub ? SekPcS68k : SekPc;\r
dprintf("---");\r
m68k_disassemble(buff, pppc, M68K_CPU_TYPE_68000);\r
dprintf("PC: %06x: %04x: %s", pppc, ppop, buff);\r
- //dprintf("A7: %08x", PicoCpuCM68k.a[7]);\r
+ //dprintf("A7: %08x", currentC68k->a[7]);\r
}\r
#endif\r
\r
}\r
\r
cyc_other=otherRun();\r
+ // Musashi takes irq even if it hasn't got cycles left, let othercpu do it too\r
+ if (other_get_irq() && other_get_irq() > ((other_get_sr()>>8)&7))\r
+ cyc_other+=otherRun();\r
cyc_musashi=m68k_execute(1);\r
\r
if (cyc_other != cyc_musashi) {\r
if(err) dumpPCandExit(is_sub);\r
\r
#if 0\r
- if (PicoCpuCM68k.a[7] < 0x00ff0000 || PicoCpuCM68k.a[7] >= 0x01000000)\r
+ if (m68ki_cpu.dar[15] < 0x00ff0000 || m68ki_cpu.dar[15] >= 0x01000000)\r
{\r
- PicoCpuCM68k.a[7] = m68ki_cpu.dar[15] = 0xff8000;\r
+ other_dar(15) = m68ki_cpu.dar[15] = 0xff8000;\r
}\r
#endif\r
#if 0\r
m68k_set_reg(M68K_REG_SR, ((mu_sr-1)&~0x2000)|(mu_sr&0x2000)); // broken\r
- CycloneSetSr(&PicoCpuCM68k, ((mu_sr-1)&~0x2000)|(mu_sr&0x2000));\r
- PicoCpuCM68k.stopped = m68ki_cpu.stopped = 0;\r
- if(SekPc > 0x400 && (PicoCpuCM68k.a[7] < 0xff0000 || PicoCpuCM68k.a[7] > 0xffffff))\r
- PicoCpuCM68k.a[7] = m68ki_cpu.dar[15] = 0xff8000;\r
+ CycloneSetSr(currentC68k, ((mu_sr-1)&~0x2000)|(mu_sr&0x2000));\r
+ currentC68k->stopped = m68ki_cpu.stopped = 0;\r
+ if(SekPc > 0x400 && (currentC68k->a[7] < 0xff0000 || currentC68k->a[7] > 0xffffff))\r
+ currentC68k->a[7] = m68ki_cpu.dar[15] = 0xff8000;\r
#endif\r
\r
cyc_done += cyc_other;\r
#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
\r
#ifdef EMU_CORE_DEBUG\r
+extern int dbg_irq_level;\r
#undef SekSetCyclesLeftNoMCD\r
#undef SekSetCyclesLeft\r
#undef SekCyclesBurn\r
#undef SekEndRun\r
+#undef SekInterrupt\r
#define SekSetCyclesLeftNoMCD(c)\r
#define SekSetCyclesLeft(c)\r
#define SekCyclesBurn(c) c\r
#define SekEndRun(c)\r
+#define SekInterrupt(irq) dbg_irq_level=irq\r
#endif\r
\r
// ----------------------- Z80 CPU -----------------------\r
m68ki_cpu.sp[0]=0;\r
m68k_set_irq(0);\r
m68k_pulse_reset();\r
+ REG_USP = 0; // ?\r
#endif\r
#ifdef EMU_F68K\r
{\r
}\r
return;\r
\r
-update_irq:\r
+update_irq:;\r
#ifndef EMU_CORE_DEBUG\r
// update IRQ level (Lemmings, Wiz 'n' Liz intro, ... )\r
// may break if done improperly:\r
@ update aims
ldr r8, =SekCycleAim
- ldr r9, =SekCycleAimS68k
+ ldr r10,=SekCycleAimS68k
ldr r2, [r8]
- ldr r3, [r9]
+ ldr r3, [r10]
add r2, r2, r0
add r3, r3, r1
str r2, [r8]
- str r3, [r9]
+ str r3, [r10]
ldr r1, =SekCycleCnt
ldr r0, =((488<<16)-PS_STEP_M68K)
ldr r0, [sp,#4] @ run_cycle_cnt
ldr r1, [r3]
str r4, [r7,#0x40] ;@ Save Current PC + Memory Base
- strb r9, [r7,#0x46] ;@ Save Flags (NZCV)
+ strb r10,[r7,#0x46] ;@ Save Flags (NZCV)
sub r0, r0, r5 @ subtract leftover cycles (which should be negative)
add r0, r0, r1
str r0, [r3]
schedule_s68k:
ldr r8, =SekCycleCntS68k
- ldr r9, =SekCycleAimS68k
+ ldr r10,=SekCycleAimS68k
ldr r3, [sp]
ldr r8, [r8]
- ldr r9, [r9]
+ ldr r10,[r10]
- sub r0, r9, r8
+ sub r0, r10, r8
mov r2, r3
add r3, r3, r2, asr #1
add r3, r3, r2, asr #3 @ cycn_s68k = (cycn + cycn/2 + cycn/8)
ldr r0, [sp,#4] @ run_cycle_cnt
ldr r1, [r3]
str r4, [r7,#0x40] ;@ Save Current PC + Memory Base
- strb r9, [r7,#0x46] ;@ Save Flags (NZCV)
+ strb r10,[r7,#0x46] ;@ Save Flags (NZCV)
sub r0, r0, r5 @ subtract leftover cycles (should be negative)
add r0, r0, r1
str r0, [r3]
ldr r1, =PS_STEP_M68K
ldr r3, [sp] @ main_cycle_cnt
ldr r8, =SekCycleCnt
- ldr r9, =SekCycleAim
+ ldr r10,=SekCycleAim
subs r3, r3, r1
bmi SekRunPS_end
ldr r8, [r8]
- ldr r9, [r9]
+ ldr r10,[r10]
str r3, [sp] @ update main_cycle_cnt
- sub r0, r9, r8
+ sub r0, r10, r8
subs r5, r0, r3, asr #16
ble schedule_s68k @ m68k has not enough cycles
;@ r6 = Opcode Jump table
;@ r7 = Pointer to Cpu Context
;@ r8 = Current Opcode
- ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)
+ ldrb r10,[r7,#0x46];@ r10 = Flags (NZCV)
ldr r1,[r7,#0x44] ;@ get SR high and IRQ level
- orr r9,r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format
- ;@ r10 = Source value / Memory Base
+ orr r10,r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format
;@ CheckInterrupt:
movs r0,r1,lsr #24 ;@ Get IRQ level
ldr r0,[r7,#0x58] ;@ state_flags
ldrh r8,[r4],#2 ;@ Fetch first opcode
tst r0,#0x03 ;@ special state?
- andeq r9,r9,#0xf0000000
+ andeq r10,r10,#0xf0000000
ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler
CycloneSpecial2:
case 1: str = "hw horizontal"; break;
case 2: str = "hw horiz. + vert."; break;
case 3: str = "sw horizontal"; break;
- case 1: str = "ON"; break;
}
fprintf(f, "Scaling = %s", str);
#endif
OBJS += ../../unzip/unzip.o ../../unzip/unzip_stream.o\r
# debug\r
ifeq "$(debug_cyclone)" "1"\r
-OBJS += ../../Pico/_cyclone_debug.o ../../cpu/musashi/m68kdasm.o\r
+OBJS += ../../Pico/Debug.o ../../cpu/musashi/m68kdasm.o\r
endif\r
# CPU cores\r
ifeq "$(use_musashi)" "1"\r