+ u32 tmp3, tmp4, sr;
+
+ if (drcf.delayed_op > 0)
+ drcf.delayed_op--;
+
+ i = find_in_array(branch_target_pc, branch_target_count, pc);
+ if (i >= 0)
+ {
+ if (pc != sh2->pc)
+ {
+ /* make "subblock" - just a mid-block entry */
+ block_desc *subblock;
+ u16 *drcblk;
+ int blkid;
+
+ sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
+ emith_sub_r_imm(sr, cycles << 12);
+ cycles = 0;
+ rcache_flush();
+ do_host_disasm(tcache_id);
+
+ subblock = dr_add_block(pc, tcache_id, &blkid);
+ if (subblock == NULL)
+ return NULL;
+ subblock->end_addr = pc;
+
+ if (tcache_id != 0) { // data array, BIOS
+ drcblk = Pico32xMem->drcblk_da[sh2->is_slave];
+ drcblk += (pc & 0x00fff) >> SH2_DRCBLK_DA_SHIFT;
+ *drcblk = (blkid << 1) | 1;
+ } else if ((this_block->addr & 0xc7fc0000) == 0x06000000) { // DRAM
+ drcblk = Pico32xMem->drcblk_ram;
+ drcblk += (pc & 0x3ffff) >> SH2_DRCBLK_RAM_SHIFT;
+ *drcblk = (blkid << 1) | 1;
+ }
+
+ dbg(1, "=== %csh2 subblock #%d,%d %08x -> %p", sh2->is_slave ? 's' : 'm',
+ tcache_id, blkid, pc, tcache_ptr);
+ }
+ branch_target_ptr[i] = tcache_ptr;
+
+ // must update PC
+ emit_move_r_imm32(SHR_PC, pc);
+ rcache_clean();
+
+ // check cycles
+ sr = rcache_get_reg(SHR_SR, RC_GR_READ);
+ emith_cmp_r_imm(sr, 0);
+ emith_jump_cond(DCOND_LE, sh2_drc_exit);
+ }