+#define IRQ_CNT_FB_BASE 0x1ff00
+
+// see do_cmd()
+static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
+{
+ u16 v, *r = (u16 *)0xa15120;
+ u8 *r8 = (u8 *)r;
+ u16 cmd_s = cmd | (is_slave << 15);
+ int i;
+
+ write32(&r[4/2], a0);
+ write32(&r[8/2], a1);
+ mem_barrier();
+ write16(r, cmd_s);
+ mem_barrier();
+ for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
+ burn10(1);
+ if (v != 0) {
+ printf("cmd clr: %x\n", v);
+ mem_barrier();
+ printf("exc m s: %02x %02x\n", r8[0x0e], r8[0x0f]);
+ write16(r, 0);
+ }
+ v = read16(&r[1]);
+ if (v != 0) {
+ printf("cmd err: %x\n", v);
+ write16(&r[1], 0);
+ }
+}
+
+static int t_32x_reset_btn(void)
+{
+ void (*do_32x_disable)(void) = (void *)0xff0040;
+ u32 *fbl_icnt = (u32 *)(0x840000 + IRQ_CNT_FB_BASE);
+ u16 *m_icnt = (u16 *)fbl_icnt;
+ u16 *s_icnt = m_icnt + 8;
+ u32 *r32 = (u32 *)0xa15100;
+ u16 *r16 = (u16 *)r32, i, s;
+ u8 *r8 = (u8 *)r32;
+ u32 *rl = (u32 *)0;
+ int ok = 1;
+
+ if (!(read16(r16) & 1))
+ return R_SKIP;
+
+ expect(ok, r16[0x00/2], 0x8083);
+
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, r16[0x00/2], 0x83);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 3);
+ expect(ok, r16[0x06/2], 1); // RV (set in sega_gcc.s reset handler)
+ expect(ok, r32[0x08/4], 0x5a5a08);
+ expect(ok, r32[0x0c/4], 0x5a5a0c);
+ expect(ok, r16[0x10/2], 0x5a10);
+ expect(ok, r32[0x14/4], 0);
+ expect(ok, r32[0x18/4], 0);
+ expect(ok, r32[0x1c/4], 0);
+ expect(ok, r32[0x20/4], 0x00005a20);
+ expect(ok, r32[0x24/4], 0x5a5a5a24);
+ expect(ok, r32[0x28/4], 0x5a5a5a28);
+ expect(ok, r32[0x2c/4], 0x075a5a2c); // 7 - last_irq_vec
+ if (!(r16[0x00/2] & 0x8000)) {
+ expect(ok, r8 [0x81], 1);
+ expect(ok, r16[0x82/2], 1);
+ expect(ok, r16[0x84/2], 0xff);
+ expect(ok, r16[0x86/2], 0xffff);
+ expect(ok, r16[0x88/2], 0);
+ expect(ok, r8 [0x8b] & ~2, 0); // FEN toggles periodically?
+ expect(ok, r16[0x8c/2], 0);
+ expect(ok, r16[0x8e/2], 0);
+ // setup vdp for t_32x_init
+ r8 [0x81] = 0;
+ r16[0x82/2] = r16[0x84/2] = r16[0x86/2] = 0;
+ }
+ r32[0x20/4] = r32[0x24/4] = r32[0x28/4] = r32[0x2c/4] = 0;
+ for (s = 0; s < 2; s++)
+ {
+ x32_cmd(CMD_READ32, 0x20004000, 0, s); // not cleared by hw
+ expect_sh2(ok, s, r32[0x24/4], 0x02020000); // ADEN | cmd
+ // t_32x_sh_defaults will test the other bits
+ }
+ // setup for t_32x_sh_defaults
+ x32_cmd(CMD_WRITE8, 0x20004001, 0, 0);
+ x32_cmd(CMD_WRITE8, 0x20004001, 0, 1);
+
+ for (i = 0; i < 7; i++) {
+ expect(ok, m_icnt[i], 0x100);
+ expect(ok, s_icnt[i], 0x100);
+ }
+ expect(ok, m_icnt[7], 0x101); // VRES happened
+ expect(ok, s_icnt[7], 0x100); // masked on slave
+
+ x32_cmd(CMD_GETSR, 0, 0, 1);
+ expect_sh2(ok, 1, r32[0x24/4] & ~1, 0xf0); // still masked
+ x32_cmd(CMD_SETSR, 0x10, 0, 1);
+ expect(ok, r16[0x00/2], 0x8083);
+ write8(r8, 0x00); // FM=0
+ mem_barrier();
+ expect(ok, m_icnt[7], 0x101);
+ expect(ok, s_icnt[7], 0x101);
+ expect(ok, r32[0x2c/4], 0x00070000); // 7 - last_irq_vec
+ r32[0x2c/4] = 0;
+
+ memcpy_(do_32x_disable, x32x_disable,
+ x32x_disable_end - x32x_disable);
+ do_32x_disable();
+
+ expect(ok, r16[0x00/2], 0x82);
+ expect(ok, r16[0x02/2], 0);
+ expect(ok, r16[0x04/2], 3);
+ expect(ok, r16[0x06/2], 0); // RV cleared by x32x_disable
+ expect(ok, r32[0x08/4], 0x5a5a08);
+ expect(ok, r32[0x0c/4], 0x5a5a0c);
+ expect(ok, r16[0x10/2], 0x5a10);
+ expect(ok, rl[0x04/4], 0x000800);
+
+ // setup for t_32x_init, t_32x_sh_defaults
+ r16[0x04/2] = 0;
+ r16[0x10/2] = 0x1234; // warm reset indicator
+ mem_barrier();
+ expect(ok, r16[0x06/2], 0); // RV
+ return ok;
+}
+