+ // -- pr ae nmif dme
+ // pr - priority: chan0 > chan1 or round-robin
+ // ae - address error
+ // nmif - nmi occurred
+ // dme - DMA master enable
+ #define DMA_DME (1 << 0)
+};
+
+static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
+{
+ char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
+ struct dmac *dmac = (void *)(regs + 0x180);
+ int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
+ int vector = (chan == &dmac->chan[0]) ?
+ dmac->vcrdma0 : dmac->vcrdma1;
+
+ elprintf(EL_32X, "dmac irq %d %d", level, vector);
+ sh2_internal_irq(sh2, level, vector & 0x7f);
+}
+
+static void dmac_transfer_complete(SH2 *sh2, struct dma_chan *chan)
+{
+ chan->chcr |= DMA_TE; // DMA has ended normally
+
+ p32x_sh2_poll_event(sh2, SH2_STATE_SLEEP, SekCyclesDoneT());
+ if (chan->chcr & DMA_IE)
+ dmac_te_irq(sh2, chan);
+}
+
+static void dmac_transfer_one(SH2 *sh2, struct dma_chan *chan)
+{
+ u32 size, d;
+
+ size = (chan->chcr >> 10) & 3;
+ switch (size) {
+ case 0:
+ d = p32x_sh2_read8(chan->sar, sh2);
+ p32x_sh2_write8(chan->dar, d, sh2);
+ case 1:
+ d = p32x_sh2_read16(chan->sar, sh2);
+ p32x_sh2_write16(chan->dar, d, sh2);
+ break;
+ case 2:
+ d = p32x_sh2_read32(chan->sar, sh2);
+ p32x_sh2_write32(chan->dar, d, sh2);
+ break;
+ case 3:
+ elprintf(EL_32X|EL_ANOMALY, "TODO: 16byte DMA");
+ chan->sar += 16; // always?
+ chan->tcr -= 4;
+ return;
+ }
+ chan->tcr--;
+
+ size = 1 << size;
+ if (chan->chcr & (1 << 15))
+ chan->dar -= size;
+ if (chan->chcr & (1 << 14))
+ chan->dar += size;
+ if (chan->chcr & (1 << 13))
+ chan->sar -= size;
+ if (chan->chcr & (1 << 12))
+ chan->sar += size;
+}