*/\r
\r
// NB code assumes fifo_* arrays have size 2^n\r
-// last transferred FIFO data, ...x = index XXX currently only CPU\r
-static short fifo_data[4], fifo_dx; // XXX must go into save?\r
+static struct VdpFIFO { // XXX this must go into save file!\r
+ // last transferred FIFO data, ...x = index XXX currently only CPU\r
+ unsigned short fifo_data[4], fifo_dx;\r
\r
-// queued FIFO transfers, ...x = index, ...l = queue length\r
-// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags\r
-static int fifo_queue[8], fifo_qx, fifo_ql; // XXX must go into save?\r
-enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!\r
-static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)\r
+ // queued FIFO transfers, ...x = index, ...l = queue length\r
+ // each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags (FQ_*)\r
+ unsigned int fifo_queue[8], fifo_qx, fifo_ql;\r
+ unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)\r
+\r
+ unsigned short fifo_slot; // last executed slot in current scanline\r
+ unsigned short fifo_maxslot;// #slots in scanline\r
\r
-static unsigned short fifo_slot; // last executed slot in current scanline\r
-static unsigned short fifo_maxslot;// #slots in scanline\r
+ const unsigned char *fifo_cyc2sl;\r
+ const unsigned short *fifo_sl2cyc;\r
+} VdpFIFO;\r
\r
-static const unsigned char *fifo_cyc2sl;\r
-static const unsigned short *fifo_sl2cyc;\r
+enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!\r
\r
// do the FIFO math\r
-static __inline int AdvanceFIFOEntry(struct PicoVideo *pv, int slots)\r
+static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, int slots)\r
{\r
- int l = slots, b = fifo_queue[fifo_qx] & FQ_BYTE;\r
+ int l = slots, b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;\r
+ int cnt = pv->fifo_cnt;\r
\r
// advance currently active FIFO entry\r
- if (l > pv->fifo_cnt)\r
- l = pv->fifo_cnt;\r
- if (!(fifo_queue[fifo_qx] & FQ_BGDMA))\r
- fifo_total -= ((pv->fifo_cnt & b) + l) >> b;\r
- pv->fifo_cnt -= l;\r
+ if (l > cnt)\r
+ l = cnt;\r
+ if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))\r
+ vf->fifo_total -= ((cnt & b) + l) >> b;\r
+ cnt -= l;\r
\r
// if entry has been processed...\r
- if (pv->fifo_cnt == 0) {\r
+ if (cnt == 0) {\r
// remove entry from FIFO\r
- if (fifo_ql)\r
- fifo_qx ++, fifo_qx &= 7, fifo_ql --;\r
+ if (vf->fifo_ql)\r
+ vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;\r
// start processing for next entry if there is one\r
- if (fifo_ql)\r
- pv->fifo_cnt = (fifo_queue[fifo_qx] >> 3) << (fifo_queue[fifo_qx] & FQ_BYTE);\r
- else { // FIFO empty\r
+ if (vf->fifo_ql) {\r
+ b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;\r
+ cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;\r
+ } else { // FIFO empty\r
pv->status &= ~PVS_FIFORUN;\r
- fifo_total = 0;\r
+ vf->fifo_total = 0;\r
}\r
}\r
+\r
+ pv->fifo_cnt = cnt;\r
return l;\r
}\r
\r
-static __inline void SetFIFOState(struct PicoVideo *pv)\r
+static __inline void SetFIFOState(struct VdpFIFO *vf, struct PicoVideo *pv)\r
{\r
+ unsigned int st = pv->status, cmd = pv->command;\r
// release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
- if (fifo_total <= 4) {\r
- pv->status &= ~PVS_CPUWR;\r
- if (!(pv->status & (PVS_DMABG|PVS_DMAFILL))) {\r
- pv->status &= ~SR_DMA;\r
- pv->command &= ~0x80;\r
+ if (vf->fifo_total <= 4) {\r
+ st &= ~PVS_CPUWR;\r
+ if (!(st & (PVS_DMABG|PVS_DMAFILL))) {\r
+ st &= ~SR_DMA;\r
+ cmd &= ~0x80;\r
}\r
}\r
- if (fifo_total == 0) {\r
- pv->status &= ~PVS_CPURD;\r
+ if (pv->fifo_cnt == 0) {\r
+ st &= ~PVS_CPURD;\r
// terminate DMA if applicable\r
- if (!(pv->status & (PVS_FIFORUN|PVS_DMAFILL))) {\r
- pv->status &= ~(SR_DMA|PVS_DMABG);\r
- pv->command &= ~0x80;\r
+ if (!(st & (PVS_FIFORUN|PVS_DMAFILL))) {\r
+ st &= ~(SR_DMA|PVS_DMABG);\r
+ cmd &= ~0x80;\r
}\r
}\r
+ pv->status = st;\r
+ pv->command = cmd;\r
}\r
\r
// sync FIFO to cycles\r
void PicoVideoFIFOSync(int cycles)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int slots, done;\r
\r
// calculate #slots since last executed slot\r
- slots = fifo_cyc2sl[cycles>>1] - fifo_slot;\r
+ slots = vf->fifo_cyc2sl[cycles>>1] - vf->fifo_slot;\r
\r
// advance FIFO queue by #done slots\r
done = slots;\r
while (done > 0 && pv->fifo_cnt) {\r
- int l = AdvanceFIFOEntry(pv, done);\r
- fifo_slot += l;\r
+ int l = AdvanceFIFOEntry(vf, pv, done);\r
+ vf->fifo_slot += l;\r
done -= l;\r
}\r
\r
if (done != slots)\r
- SetFIFOState(pv);\r
+ SetFIFOState(vf, pv);\r
}\r
\r
// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.\r
-int PicoVideoFIFODrain(int level, int cycles, int bgdma)\r
+static int PicoVideoFIFODrain(int level, int cycles, int bgdma)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
unsigned ocyc = cycles;\r
int burn = 0;\r
+//int osl = fifo_slot;\r
\r
// process FIFO entries until low level is reached\r
- while (fifo_total > level && fifo_slot < fifo_maxslot &&\r
- (!(fifo_queue[fifo_qx] & FQ_BGDMA) || bgdma)) {\r
- int b = fifo_queue[fifo_qx] & FQ_BYTE;\r
- int cnt = ((fifo_total-level) << b) - (pv->fifo_cnt & b);\r
- int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + fifo_slot; // target slot\r
-\r
- if (slot > fifo_maxslot) {\r
- // target in later scanline, advance to eol\r
- slot = fifo_maxslot;\r
+ while (vf->fifo_slot < vf->fifo_maxslot && cycles < 488 &&\r
+ (vf->fifo_total > level || (vf->fifo_queue[vf->fifo_qx] & bgdma))) {\r
+ int b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;\r
+ int cnt = bgdma ? pv->fifo_cnt : ((vf->fifo_total-level)<<b) - (pv->fifo_cnt&b);\r
+ int slot = (pv->fifo_cnt<cnt ? pv->fifo_cnt:cnt) + vf->fifo_slot;\r
+\r
+ if (slot > vf->fifo_maxslot) {\r
+ // target slot in later scanline, advance to eol\r
+ slot = vf->fifo_maxslot;\r
cycles = 488;\r
} else {\r
// advance FIFO to target slot and CPU to cycles at that slot\r
- cycles = fifo_sl2cyc[slot]<<1;\r
+ cycles = vf->fifo_sl2cyc[slot]<<1;\r
+ }\r
+ if (slot > vf->fifo_slot) {\r
+ AdvanceFIFOEntry(vf, pv, slot - vf->fifo_slot);\r
+ vf->fifo_slot = slot;\r
}\r
- AdvanceFIFOEntry(pv, slot - fifo_slot);\r
- fifo_slot = slot;\r
}\r
- burn = cycles - ocyc;\r
+ if (cycles > ocyc)\r
+ burn = cycles - ocyc;\r
\r
- SetFIFOState(pv);\r
+ SetFIFOState(vf, pv);\r
\r
return burn;\r
}\r
\r
// read VDP data port\r
-int PicoVideoFIFORead(void)\r
+static int PicoVideoFIFORead(void)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
int burn = 0;\r
if (pv->fifo_cnt) {\r
PicoVideoFIFOSync(lc);\r
// advance FIFO and CPU until FIFO is empty\r
- burn = PicoVideoFIFODrain(0, lc, 1);\r
+ burn = PicoVideoFIFODrain(0, lc, FQ_BGDMA);\r
lc += burn;\r
}\r
\r
- if (fifo_total > 0)\r
+ if (pv->fifo_cnt)\r
pv->status |= PVS_CPURD; // target slot is in later scanline\r
else {\r
// use next VDP access slot for reading, block 68k until then\r
- fifo_slot = fifo_cyc2sl[lc>>1] + 1;\r
- burn += (fifo_sl2cyc[fifo_slot]<<1) - lc;\r
+ vf->fifo_slot = vf->fifo_cyc2sl[lc>>1] + 1;\r
+ burn += (vf->fifo_sl2cyc[vf->fifo_slot]<<1) - lc;\r
}\r
\r
return burn;\r
// write VDP data port\r
int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int lc = SekCyclesDone()-Pico.t.m68c_line_start;\r
- int burn = 0, x, head = 0;\r
+ int burn = 0;\r
\r
if (pv->fifo_cnt)\r
PicoVideoFIFOSync(lc);\r
pv->status = (pv->status & ~sr_mask) | sr_flags;\r
\r
- if (count && fifo_ql < 8) {\r
- // update FIFO state if it was empty\r
- if (fifo_ql == 0) {\r
- fifo_slot = fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots\r
- pv->fifo_cnt = count << (flags & FQ_BYTE);\r
- pv->status |= PVS_FIFORUN;\r
- }\r
-\r
+ if (count && vf->fifo_ql < 8) {\r
// determine queue position for entry\r
- x = (fifo_qx + fifo_ql - 1) & 7;\r
- if (fifo_ql && (fifo_queue[x] & FQ_BGDMA)) {\r
+ int x = (vf->fifo_qx + vf->fifo_ql - 1) & 7;\r
+ if (unlikely(vf->fifo_ql && (vf->fifo_queue[x] & FQ_BGDMA))) {\r
// CPU FIFO writes have priority over a background DMA Fill/Copy\r
- fifo_queue[(x+1) & 7] = fifo_queue[x];\r
- if (x == fifo_qx) { // overtaking to queue head?\r
- // XXX if interrupting a DMA fill, fill data changes\r
- int f = fifo_queue[x] & 7;\r
- fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
- pv->fifo_cnt = count << (flags & FQ_BYTE);\r
- head = 1;\r
- }\r
+ // XXX if interrupting a DMA fill, fill data changes\r
+ if (x == vf->fifo_qx) { // overtaking to queue head?\r
+ int f = vf->fifo_queue[x] & 7;\r
+ vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
+ pv->status &= ~PVS_FIFORUN;\r
+ } else\r
+ // push background DMA back\r
+ vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];\r
x = (x-1) & 7;\r
}\r
\r
- // create xfer queue entry\r
- if (fifo_ql && !head && (fifo_queue[x] & 7) == flags) {\r
+ if ((pv->status & PVS_FIFORUN) && (vf->fifo_queue[x] & 7) == flags) {\r
// amalgamate entries if of same type\r
- fifo_queue[x] += (count << 3);\r
- if (x == fifo_qx) // modifiying fifo head, adjust count\r
+ vf->fifo_queue[x] += (count << 3);\r
+ if (x == vf->fifo_qx)\r
pv->fifo_cnt += count << (flags & FQ_BYTE);\r
} else {\r
- fifo_ql ++;\r
+ // create new xfer queue entry\r
+ vf->fifo_ql ++;\r
x = (x+1) & 7;\r
- fifo_queue[x] = (count << 3) | flags;\r
+ vf->fifo_queue[x] = (count << 3) | flags;\r
+ }\r
+\r
+ // update FIFO state if it was empty\r
+ if (!(pv->status & PVS_FIFORUN)) {\r
+ vf->fifo_slot = vf->fifo_cyc2sl[(lc+8)>>1]; // FIFO latency ~3 vdp slots\r
+ pv->status |= PVS_FIFORUN;\r
+ pv->fifo_cnt = count << (flags & FQ_BYTE);\r
}\r
if (!(flags & FQ_BGDMA))\r
- fifo_total += count;\r
+ vf->fifo_total += count;\r
}\r
\r
// if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
// at HINT, advance FIFO to new scanline\r
int PicoVideoFIFOHint(void)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int burn = 0;\r
\r
// reset slot to start of scanline\r
- fifo_slot = 0;\r
+ vf->fifo_slot = 0;\r
\r
// if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
if (pv->status & PVS_CPURD)\r
static const unsigned short *vdpsl2cyc[2][2] =\r
{ {vdpsl2cyc_32_bl, vdpsl2cyc_40_bl} , {vdpsl2cyc_32, vdpsl2cyc_40} };\r
\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int lc = SekCyclesDone() - Pico.t.m68c_line_start;\r
active = active && !(pv->status & PVS_VB2);\r
\r
- if (fifo_maxslot)\r
+ if (vf->fifo_maxslot)\r
PicoVideoFIFOSync(lc);\r
\r
- fifo_cyc2sl = vdpcyc2sl[active][h40];\r
- fifo_sl2cyc = vdpsl2cyc[active][h40];\r
+ vf->fifo_cyc2sl = vdpcyc2sl[active][h40];\r
+ vf->fifo_sl2cyc = vdpsl2cyc[active][h40];\r
// recalculate FIFO slot for new mode\r
- fifo_slot = fifo_cyc2sl[lc>>1]-1;\r
- fifo_maxslot = fifo_cyc2sl[488>>1];\r
+ vf->fifo_slot = vf->fifo_cyc2sl[lc>>1]-1;\r
+ vf->fifo_maxslot = vf->fifo_cyc2sl[488>>1];\r
}\r
\r
\r
\r
static unsigned int VideoRead(void)\r
{\r
- unsigned int a, d = fifo_data[(fifo_dx+1)&3];\r
+ unsigned int a, d = VdpFIFO.fifo_data[(VdpFIFO.fifo_dx+1)&3];\r
\r
a=Pico.video.addr; a>>=1;\r
\r
{\r
case 0: d=PicoMem.vram [a & 0x7fff]; break;\r
case 8: d=PicoMem.cram [a & 0x003f] | (d & ~0x0eee); break;\r
-\r
case 4: if ((a & 0x3f) >= 0x28) a = 0;\r
d=PicoMem.vsram [a & 0x003f] | (d & ~0x07ff); break;\r
case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;\r
PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);\r
if (pvid->status & SR_DMA) {\r
elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",\r
- fifo_total, SekPc);\r
- pvid->fifo_cnt = fifo_total = fifo_ql = 0;\r
+ VdpFIFO.fifo_total, SekPc);\r
+ pvid->fifo_cnt = VdpFIFO.fifo_total = VdpFIFO.fifo_ql = 0;\r
+ pvid->status &= ~(PVS_FIFORUN|PVS_DMAFILL);\r
}\r
\r
len = GetDmaLength();\r
\r
if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))\r
{\r
- fifo_data[++fifo_dx&3] = d;\r
+ VdpFIFO.fifo_data[++VdpFIFO.fifo_dx&3] = d;\r
SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));\r
\r
elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",\r
\r
// start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.\r
if (pvid->status & PVS_DMAFILL)\r
- DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);\r
+ DmaFill(VdpFIFO.fifo_data[(VdpFIFO.fifo_dx + !!(pvid->type&~0x81))&3]);\r
\r
break;\r
\r
d |= SR_HB;\r
\r
PicoVideoFIFOSync(c);\r
- if (fifo_total >= 4)\r
+ if (VdpFIFO.fifo_total >= 4)\r
d |= SR_FULL;\r
- else if (!fifo_total)\r
+ else if (!VdpFIFO.fifo_total)\r
d |= SR_EMPT;\r
return d;\r
}\r
\r
void PicoVideoSave(void)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int l, x;\r
\r
// account for all outstanding xfers XXX kludge, entry attr's not saved\r
- for (l = fifo_ql, x = fifo_qx + l-1; l > 1; l--, x--)\r
- pv->fifo_cnt += (fifo_queue[x&7] >> 3) << (fifo_queue[x&7] & FQ_BYTE);\r
+ for (l = vf->fifo_ql, x = vf->fifo_qx + l-1; l > 1; l--, x--)\r
+ pv->fifo_cnt += (vf->fifo_queue[x&7] >> 3) << (vf->fifo_queue[x&7] & FQ_BYTE);\r
}\r
\r
void PicoVideoLoad(void)\r
{\r
+ struct VdpFIFO *vf = &VdpFIFO;\r
struct PicoVideo *pv = &Pico.video;\r
int l;\r
\r
if (Pico.m.dma_xfers) {\r
pv->status = SR_DMA|PVS_FIFORUN;\r
pv->fifo_cnt = Pico.m.dma_xfers * (pv->type == 1 ? 2 : 1);\r
- fifo_total = Pico.m.dma_xfers;\r
+ vf->fifo_total = Pico.m.dma_xfers;\r
Pico.m.dma_xfers = 0;\r
}\r
\r
notaz.gp2x.de / picodrive.git / commitdiff