u32 cycles = SekCyclesDone();\r
u32 clkdiff = cycles - Pico_mcd->m.m68k_poll_clk;\r
pcd_sync_s68k(cycles, 0);\r
- if (a >= 0x0e && !Pico_mcd->m.need_sync) {\r
+ if (a == 0x0e && !Pico_mcd->m.need_sync && (Pico_mcd->s68k_regs[3]&0x4)) {\r
// there are cases when slave updates comm and only switches RAM\r
- // over after that (mcd1b), so there must be a resync..\r
+ // over after that (mcd1 bios), so there must be a resync..\r
SekEndRun(64);\r
Pico_mcd->m.need_sync = 1;\r
}\r
}\r
Pico_mcd->m.m68k_poll_cnt++;\r
if(Pico_mcd->m.m68k_poll_cnt >= POLL_LIMIT)\r
- SekEndRun(0);\r
+ SekEndRun(8);\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
// slave. This can produce race conditions where slave switches RAM back to\r
// master while master is delayed by interrupt before the check executes.\r
// Delay slave a bit to make sure master can check before slave changes.\r
- SekCycleCntS68k += 24;\r
+ SekCycleCntS68k += 24; // Silpheed\r
}\r
if (Pico_mcd->m.s68k_poll_a == (a & ~1))\r
{\r
elprintf(EL_CDPOLL, "s68k poll release, a=%02x", a);\r
SekSetStopS68k(0);\r
}\r
- Pico_mcd->m.s68k_poll_a = 0;\r
+ Pico_mcd->m.s68k_poll_cnt = 0;\r
}\r
}\r
\r
u32 cycles, cnt = 0;\r
if (SekIsStoppedS68k())\r
return d;\r
+ SekEndRunS68k(8);\r
\r
cycles = SekCyclesDoneS68k();\r
if (!SekNotPollingS68k && a == Pico_mcd->m.s68k_poll_a) {\r
if (clkdiff <= POLL_CYCLES) {\r
cnt = Pico_mcd->m.s68k_poll_cnt + 1;\r
//printf("-- diff: %u, cnt = %i\n", clkdiff, cnt);\r
- if (Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {\r
+ if (cnt > POLL_LIMIT) {\r
SekSetStopS68k(1);\r
elprintf(EL_CDPOLL, "s68k poll detected @%06x, a=%02x",\r
SekPcS68k, a);\r
\r
Pico_mcd->s68k_regs[a] = (u8) d;\r
if (Pico_mcd->m.m68k_poll_cnt)\r
- SekEndRunS68k(0);\r
+ SekEndRunS68k(8);\r
Pico_mcd->m.m68k_poll_cnt = 0;\r
}\r
\r
r[a] = d >> 8;\r
r[a + 1] = d;\r
if (Pico_mcd->m.m68k_poll_cnt)\r
- SekEndRunS68k(0);\r
+ SekEndRunS68k(8);\r
Pico_mcd->m.m68k_poll_cnt = 0;\r
}\r
\r