readend:
if (PicoAHW & PAHW_MCD)
{
- /* after load events */
- if (Pico_mcd->s68k_regs[3] & 4) // 1M mode?
- wram_2M_to_1M(Pico_mcd->word_ram2M);
- PicoMemRemapCD(Pico_mcd->s68k_regs[3]);
-#ifdef _ASM_CD_MEMORY_C
- if (Pico_mcd->s68k_regs[3] & 4)
- PicoMemResetCDdecode(Pico_mcd->s68k_regs[3]);
-#endif
+ PicoMemStateLoaded();
+
if (!(Pico_mcd->s68k_regs[0x36] & 1) && (Pico_mcd->scd.Status_CDC & 1))
cdda_start_play();
- // restore hint vector
- *(unsigned short *)(Pico_mcd->bios + 0x72) = Pico_mcd->m.hint_vector;
// must unpack after other CD stuff is loaded
PicoAreaUnpackCpu(buff_s68k, 1);
\r
// -----------------------------------------------------------------\r
\r
+// provided by ASM code:\r
+#ifdef _ASM_CD_MEMORY_C\r
+u32 PicoReadM68k8_io(u32 a);\r
+u32 PicoReadM68k16_io(u32 a);\r
+void PicoWriteM68k8_io(u32 a, u32 d);\r
+void PicoWriteM68k16_io(u32 a, u32 d);\r
+\r
+u32 PicoReadS68k8_pr(u32 a);\r
+u32 PicoReadS68k16_pr(u32 a);\r
+void PicoWriteS68k8_pr(u32 a, u32 d);\r
+void PicoWriteS68k16_pr(u32 a, u32 d);\r
+\r
+u32 PicoReadM68k8_cell0(u32 a);\r
+u32 PicoReadM68k8_cell1(u32 a);\r
+u32 PicoReadM68k16_cell0(u32 a);\r
+u32 PicoReadM68k16_cell1(u32 a);\r
+void PicoWriteM68k8_cell0(u32 a, u32 d);\r
+void PicoWriteM68k8_cell1(u32 a, u32 d);\r
+void PicoWriteM68k16_cell0(u32 a, u32 d);\r
+void PicoWriteM68k16_cell1(u32 a, u32 d);\r
+\r
+u32 PicoReadS68k8_dec0(u32 a);\r
+u32 PicoReadS68k8_dec1(u32 a);\r
+u32 PicoReadS68k16_dec0(u32 a);\r
+u32 PicoReadS68k16_dec1(u32 a);\r
+void PicoWriteS68k8_dec_m0b0(u32 a, u32 d);\r
+void PicoWriteS68k8_dec_m1b0(u32 a, u32 d);\r
+void PicoWriteS68k8_dec_m2b0(u32 a, u32 d);\r
+void PicoWriteS68k8_dec_m0b1(u32 a, u32 d);\r
+void PicoWriteS68k8_dec_m1b1(u32 a, u32 d);\r
+void PicoWriteS68k8_dec_m2b1(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m0b0(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m1b0(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m2b0(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m0b1(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m1b1(u32 a, u32 d);\r
+void PicoWriteS68k16_dec_m2b1(u32 a, u32 d);\r
+#endif\r
+\r
+static void remap_prg_window(void);\r
+static void remap_word_ram(int r3);\r
+\r
// poller detection\r
#define POLL_LIMIT 16\r
#define POLL_CYCLES 124\r
if (!(d & 1))\r
d |= 2; // verified: reset also gives bus\r
if ((d ^ Pico_mcd->m.busreq) & 2)\r
- PicoMemRemapCD(Pico_mcd->s68k_regs[3]);\r
+ remap_prg_window();\r
Pico_mcd->m.busreq = d;\r
return;\r
case 2:\r
Pico_mcd->s68k_regs[3] = (d & 0xc2) | (dold & 0x1f);\r
if ((d ^ dold) & 0xc0) {\r
elprintf(EL_CDREGS, "m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
- PicoMemRemapCD(Pico_mcd->s68k_regs[3]);\r
+ remap_prg_window();\r
}\r
#ifdef USE_POLL_DETECT\r
if ((s68k_poll_adclk&0xfe) == 2 && s68k_poll_cnt > POLL_LIMIT) {\r
d |= dold & 0xc2;\r
if (d & 4)\r
{\r
- if ((d ^ dold) & 5) {\r
+ if ((d ^ dold) & 0x1d) {\r
d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
- PicoMemRemapCD(d);\r
+ remap_word_ram(d);\r
}\r
-#ifdef _ASM_CD_MEMORY_C\r
- if ((d ^ dold) & 0x1d)\r
- PicoMemResetCDdecode(d);\r
-#endif\r
if (!(dold & 4)) {\r
elprintf(EL_CDREG3, "wram mode 2M->1M");\r
wram_2M_to_1M(Pico_mcd->word_ram2M);\r
d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode\r
}\r
wram_1M_to_2M(Pico_mcd->word_ram2M);\r
- PicoMemRemapCD(d);\r
+ remap_word_ram(d);\r
}\r
// s68k can only set RET, writing 0 has no effect\r
else if ((dold ^ d) & d & 1) { // RET being set\r
\r
#ifndef _ASM_CD_MEMORY_C\r
#include "cell_map.c"\r
-#endif\r
\r
// WORD RAM, cell aranged area (220000 - 23ffff)\r
-static u32 PicoReadM68k8_cell(u32 a)\r
+static u32 PicoReadM68k8_cell0(u32 a)\r
{\r
- int bank = Pico_mcd->s68k_regs[3] & 1;\r
a = (a&3) | (cell_map(a >> 2) << 2); // cell arranged\r
- return Pico_mcd->word_ram1M[bank][a ^ 1];\r
+ return Pico_mcd->word_ram1M[0][a ^ 1];\r
+}\r
+\r
+static u32 PicoReadM68k8_cell1(u32 a)\r
+{\r
+ a = (a&3) | (cell_map(a >> 2) << 2);\r
+ return Pico_mcd->word_ram1M[1][a ^ 1];\r
+}\r
+\r
+static u32 PicoReadM68k16_cell0(u32 a)\r
+{\r
+ a = (a&2) | (cell_map(a >> 2) << 2);\r
+ return *(u16 *)(Pico_mcd->word_ram1M[0] + a);\r
}\r
\r
-static u32 PicoReadM68k16_cell(u32 a)\r
+static u32 PicoReadM68k16_cell1(u32 a)\r
{\r
- int bank = Pico_mcd->s68k_regs[3] & 1;\r
a = (a&2) | (cell_map(a >> 2) << 2);\r
- return *(u16 *)(Pico_mcd->word_ram1M[bank] + a);\r
+ return *(u16 *)(Pico_mcd->word_ram1M[1] + a);\r
}\r
\r
-static void PicoWriteM68k8_cell(u32 a, u32 d)\r
+static void PicoWriteM68k8_cell0(u32 a, u32 d)\r
{\r
- int bank = Pico_mcd->s68k_regs[3] & 1;\r
a = (a&3) | (cell_map(a >> 2) << 2);\r
- Pico_mcd->word_ram1M[bank][a ^ 1] = d;\r
+ Pico_mcd->word_ram1M[0][a ^ 1] = d;\r
}\r
\r
-static void PicoWriteM68k16_cell(u32 a, u32 d)\r
+static void PicoWriteM68k8_cell1(u32 a, u32 d)\r
{\r
- int bank = Pico_mcd->s68k_regs[3] & 1;\r
a = (a&3) | (cell_map(a >> 2) << 2);\r
- *(u16 *)(Pico_mcd->word_ram1M[bank] + a) = d;\r
+ Pico_mcd->word_ram1M[1][a ^ 1] = d;\r
}\r
\r
+static void PicoWriteM68k16_cell0(u32 a, u32 d)\r
+{\r
+ a = (a&3) | (cell_map(a >> 2) << 2);\r
+ *(u16 *)(Pico_mcd->word_ram1M[0] + a) = d;\r
+}\r
+\r
+static void PicoWriteM68k16_cell1(u32 a, u32 d)\r
+{\r
+ a = (a&3) | (cell_map(a >> 2) << 2);\r
+ *(u16 *)(Pico_mcd->word_ram1M[1] + a) = d;\r
+}\r
+#endif\r
+\r
// RAM cart (40000 - 7fffff, optional)\r
static u32 PicoReadM68k8_ramc(u32 a)\r
{\r
}\r
\r
// IO/control/cd registers (a10000 - ...)\r
+#ifndef _ASM_CD_MEMORY_C\r
static u32 PicoReadM68k8_io(u32 a)\r
{\r
u32 d;\r
\r
PicoWrite16_io(a, d);\r
}\r
+#endif\r
\r
// -----------------------------------------------------------------\r
// Sub 68k\r
elprintf(EL_UIO, "s68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);\r
}\r
\r
+// PRG RAM protected range (000000 - 00ff00)?\r
+// XXX verify: ff00 or 1fe00 max?\r
+static void PicoWriteS68k8_prgwp(u32 a, u32 d)\r
+{\r
+ if (a >= (Pico_mcd->s68k_regs[2] << 8))\r
+ Pico_mcd->prg_ram[a ^ 1] = d;\r
+}\r
+\r
+static void PicoWriteS68k16_prgwp(u32 a, u32 d)\r
+{\r
+ if (a >= (Pico_mcd->s68k_regs[2] << 8))\r
+ *(u16 *)(Pico_mcd->prg_ram + a) = d;\r
+}\r
+\r
+#ifndef _ASM_CD_MEMORY_C\r
+\r
// decode (080000 - 0bffff, in 1M mode)\r
-static u32 PicoReadS68k8_dec(u32 a)\r
+static u32 PicoReadS68k8_dec0(u32 a)\r
+{\r
+ u32 d = Pico_mcd->word_ram1M[0][((a >> 1) ^ 1) & 0x1ffff];\r
+ if (a & 1)\r
+ d &= 0x0f;\r
+ else\r
+ d >>= 4;\r
+ return d;\r
+}\r
+\r
+static u32 PicoReadS68k8_dec1(u32 a)\r
{\r
- u32 d, bank;\r
- bank = (Pico_mcd->s68k_regs[3] & 1) ^ 1;\r
- d = Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff];\r
+ u32 d = Pico_mcd->word_ram1M[1][((a >> 1) ^ 1) & 0x1ffff];\r
if (a & 1)\r
d &= 0x0f;\r
else\r
return d;\r
}\r
\r
-static u32 PicoReadS68k16_dec(u32 a)\r
+static u32 PicoReadS68k16_dec0(u32 a)\r
{\r
- u32 d, bank;\r
- bank = (Pico_mcd->s68k_regs[3] & 1) ^ 1;\r
- d = Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff];\r
+ u32 d = Pico_mcd->word_ram1M[0][((a >> 1) ^ 1) & 0x1ffff];\r
d |= d << 4;\r
d &= ~0xf0;\r
return d;\r
}\r
\r
-/* check: jaguar xj 220 (draws entire world using decode) */\r
-static void PicoWriteS68k8_dec(u32 a, u32 d)\r
+static u32 PicoReadS68k16_dec1(u32 a)\r
{\r
- u8 r3 = Pico_mcd->s68k_regs[3];\r
- u8 *pd = &Pico_mcd->word_ram1M[(r3 & 1) ^ 1][((a >> 1) ^ 1) & 0x1ffff];\r
- u8 oldmask = (a & 1) ? 0xf0 : 0x0f;\r
-\r
- r3 &= 0x18;\r
- d &= 0x0f;\r
- if (!(a & 1))\r
- d <<= 4;\r
-\r
- if (r3 == 8) {\r
- if ((!(*pd & (~oldmask))) && d)\r
- goto do_it;\r
- } else if (r3 > 8) {\r
- if (d)\r
- goto do_it;\r
- } else\r
- goto do_it;\r
-\r
- return;\r
-\r
-do_it:\r
- *pd = d | (*pd & oldmask);\r
+ u32 d = Pico_mcd->word_ram1M[1][((a >> 1) ^ 1) & 0x1ffff];\r
+ d |= d << 4;\r
+ d &= ~0xf0;\r
+ return d;\r
}\r
\r
-static void PicoWriteS68k16_dec(u32 a, u32 d)\r
-{\r
- u8 r3 = Pico_mcd->s68k_regs[3];\r
- u8 *pd = &Pico_mcd->word_ram1M[(r3 & 1) ^ 1][((a >> 1) ^ 1) & 0x1ffff];\r
+/* check: jaguar xj 220 (draws entire world using decode) */\r
+#define mk_decode_w8(bank) \\r
+static void PicoWriteS68k8_dec_m0b##bank(u32 a, u32 d) \\r
+{ \\r
+ u8 *pd = &Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff]; \\r
+ \\r
+ if (!(a & 1)) \\r
+ *pd = (*pd & 0x0f) | (d << 4); \\r
+ else \\r
+ *pd = (*pd & 0xf0) | (d & 0x0f); \\r
+} \\r
+ \\r
+static void PicoWriteS68k8_dec_m1b##bank(u32 a, u32 d) \\r
+{ \\r
+ u8 *pd = &Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff]; \\r
+ u8 mask = (a & 1) ? 0x0f : 0xf0; \\r
+ \\r
+ if (!(*pd & mask) && (d & 0x0f)) /* underwrite */ \\r
+ PicoWriteS68k8_dec_m0b##bank(a, d); \\r
+} \\r
+ \\r
+static void PicoWriteS68k8_dec_m2b##bank(u32 a, u32 d) /* ...and m3? */ \\r
+{ \\r
+ if (d & 0x0f) /* overwrite */ \\r
+ PicoWriteS68k8_dec_m0b##bank(a, d); \\r
+}\r
\r
- //if ((a & 0x3ffff) < 0x28000) return;\r
+mk_decode_w8(0)\r
+mk_decode_w8(1)\r
+\r
+#define mk_decode_w16(bank) \\r
+static void PicoWriteS68k16_dec_m0b##bank(u32 a, u32 d) \\r
+{ \\r
+ u8 *pd = &Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff]; \\r
+ \\r
+ d &= 0x0f0f; \\r
+ *pd = d | (d >> 4); \\r
+} \\r
+ \\r
+static void PicoWriteS68k16_dec_m1b##bank(u32 a, u32 d) \\r
+{ \\r
+ u8 *pd = &Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff]; \\r
+ \\r
+ d &= 0x0f0f; /* underwrite */ \\r
+ if (!(*pd & 0xf0)) *pd |= d >> 4; \\r
+ if (!(*pd & 0x0f)) *pd |= d; \\r
+} \\r
+ \\r
+static void PicoWriteS68k16_dec_m2b##bank(u32 a, u32 d) \\r
+{ \\r
+ u8 *pd = &Pico_mcd->word_ram1M[bank][((a >> 1) ^ 1) & 0x1ffff]; \\r
+ \\r
+ d &= 0x0f0f; /* overwrite */ \\r
+ d |= d >> 4; \\r
+ \\r
+ if (!(d & 0xf0)) d |= *pd & 0xf0; \\r
+ if (!(d & 0x0f)) d |= *pd & 0x0f; \\r
+ *pd = d; \\r
+}\r
\r
- r3 &= 0x18;\r
- d &= 0x0f0f;\r
- d |= d >> 4;\r
+mk_decode_w16(0)\r
+mk_decode_w16(1)\r
\r
- if (r3 == 8) {\r
- u8 dold = *pd;\r
- if (!(dold & 0xf0)) dold |= d & 0xf0;\r
- if (!(dold & 0x0f)) dold |= d & 0x0f;\r
- *pd = dold;\r
- } else if (r3 > 8) {\r
- u8 dold = *pd;\r
- if (!(d & 0xf0)) d |= dold & 0xf0;\r
- if (!(d & 0x0f)) d |= dold & 0x0f;\r
- *pd = d;\r
- } else {\r
- *pd = d;\r
- }\r
-}\r
+#endif\r
\r
// backup RAM (fe0000 - feffff)\r
static u32 PicoReadS68k8_bram(u32 a)\r
SRam.changed = 1;\r
}\r
\r
+#ifndef _ASM_CD_MEMORY_C\r
+\r
// PCM and registers (ff0000 - ffffff)\r
static u32 PicoReadS68k8_pr(u32 a)\r
{\r
}\r
\r
// PCM\r
+ // XXX: verify: probably odd addrs only?\r
if ((a & 0x8000) == 0x0000) {\r
a &= 0x7fff;\r
if (a >= 0x2000)\r
s68k_unmapped_write16(a, d);\r
}\r
\r
+#endif\r
+\r
+static const void *m68k_cell_read8[] = { PicoReadM68k8_cell0, PicoReadM68k8_cell1 };\r
+static const void *m68k_cell_read16[] = { PicoReadM68k16_cell0, PicoReadM68k16_cell1 };\r
+static const void *m68k_cell_write8[] = { PicoWriteM68k8_cell0, PicoWriteM68k8_cell1 };\r
+static const void *m68k_cell_write16[] = { PicoWriteM68k16_cell0, PicoWriteM68k16_cell1 };\r
+\r
+static const void *s68k_dec_read8[] = { PicoReadS68k8_dec0, PicoReadS68k8_dec1 };\r
+static const void *s68k_dec_read16[] = { PicoReadS68k16_dec0, PicoReadS68k16_dec1 };\r
+\r
+static const void *s68k_dec_write8[2][4] = {\r
+ { PicoWriteS68k8_dec_m0b0, PicoWriteS68k8_dec_m1b0, PicoWriteS68k8_dec_m2b0, PicoWriteS68k8_dec_m2b0 },\r
+ { PicoWriteS68k8_dec_m0b1, PicoWriteS68k8_dec_m1b1, PicoWriteS68k8_dec_m2b1, PicoWriteS68k8_dec_m2b1 },\r
+};\r
+\r
+static const void *s68k_dec_write16[2][4] = {\r
+ { PicoWriteS68k16_dec_m0b0, PicoWriteS68k16_dec_m1b0, PicoWriteS68k16_dec_m2b0, PicoWriteS68k16_dec_m2b0 },\r
+ { PicoWriteS68k16_dec_m0b1, PicoWriteS68k16_dec_m1b1, PicoWriteS68k16_dec_m2b1, PicoWriteS68k16_dec_m2b1 },\r
+};\r
+\r
// -----------------------------------------------------------------\r
\r
-// TODO: probably split\r
-void PicoMemRemapCD(int r3)\r
+static void remap_prg_window(void)\r
{\r
- void *bank;\r
-\r
// PRG RAM\r
if (Pico_mcd->m.busreq & 2) {\r
- bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3] >> 6];\r
+ void *bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3] >> 6];\r
cpu68k_map_all_ram(0x020000, 0x03ffff, bank, 0);\r
}\r
else {\r
m68k_map_unmap(0x020000, 0x03ffff);\r
}\r
+}\r
+\r
+static void remap_word_ram(int r3)\r
+{\r
+ void *bank;\r
\r
// WORD RAM\r
if (!(r3 & 4)) {\r
// TODO: handle 0x0c0000\r
}\r
else {\r
- bank = Pico_mcd->word_ram1M[r3 & 1];\r
+ int b0 = r3 & 1;\r
+ int m = (r3 & 0x18) >> 3;\r
+ bank = Pico_mcd->word_ram1M[b0];\r
cpu68k_map_all_ram(0x200000, 0x21ffff, bank, 0);\r
- bank = Pico_mcd->word_ram1M[(r3 & 1) ^ 1];\r
+ bank = Pico_mcd->word_ram1M[b0 ^ 1];\r
cpu68k_map_all_ram(0x0c0000, 0x0effff, bank, 1);\r
// "cell arrange" on m68k\r
- cpu68k_map_set(m68k_read8_map, 0x220000, 0x23ffff, PicoReadM68k8_cell, 1);\r
- cpu68k_map_set(m68k_read16_map, 0x220000, 0x23ffff, PicoReadM68k16_cell, 1);\r
- cpu68k_map_set(m68k_write8_map, 0x220000, 0x23ffff, PicoWriteM68k8_cell, 1);\r
- cpu68k_map_set(m68k_write16_map, 0x220000, 0x23ffff, PicoWriteM68k16_cell, 1);\r
+ cpu68k_map_set(m68k_read8_map, 0x220000, 0x23ffff, m68k_cell_read8[b0], 1);\r
+ cpu68k_map_set(m68k_read16_map, 0x220000, 0x23ffff, m68k_cell_read16[b0], 1);\r
+ cpu68k_map_set(m68k_write8_map, 0x220000, 0x23ffff, m68k_cell_write8[b0], 1);\r
+ cpu68k_map_set(m68k_write16_map, 0x220000, 0x23ffff, m68k_cell_write16[b0], 1);\r
// "decode format" on s68k\r
- cpu68k_map_set(s68k_read8_map, 0x080000, 0x0bffff, PicoReadS68k8_dec, 1);\r
- cpu68k_map_set(s68k_read16_map, 0x080000, 0x0bffff, PicoReadS68k16_dec, 1);\r
- cpu68k_map_set(s68k_write8_map, 0x080000, 0x0bffff, PicoWriteS68k8_dec, 1);\r
- cpu68k_map_set(s68k_write16_map, 0x080000, 0x0bffff, PicoWriteS68k16_dec, 1);\r
+ cpu68k_map_set(s68k_read8_map, 0x080000, 0x0bffff, s68k_dec_read8[b0 ^ 1], 1);\r
+ cpu68k_map_set(s68k_read16_map, 0x080000, 0x0bffff, s68k_dec_read16[b0 ^ 1], 1);\r
+ cpu68k_map_set(s68k_write8_map, 0x080000, 0x0bffff, s68k_dec_write8[b0 ^ 1][m], 1);\r
+ cpu68k_map_set(s68k_write16_map, 0x080000, 0x0bffff, s68k_dec_write16[b0 ^ 1][m], 1);\r
}\r
\r
#ifdef EMU_F68K\r
#endif\r
}\r
\r
+void PicoMemStateLoaded(void)\r
+{\r
+ int r3 = Pico_mcd->s68k_regs[3];\r
+\r
+ /* after load events */\r
+ if (r3 & 4) // 1M mode?\r
+ wram_2M_to_1M(Pico_mcd->word_ram2M);\r
+ remap_word_ram(r3);\r
+ remap_prg_window();\r
+\r
+ // restore hint vector\r
+ *(unsigned short *)(Pico_mcd->bios + 0x72) = Pico_mcd->m.hint_vector;\r
+}\r
+\r
#ifdef EMU_M68K\r
static void m68k_mem_setup_cd(void);\r
#endif\r
// setup default main68k map\r
PicoMemSetup();\r
\r
- // PicoMemRemapCD() will set up RAMs, so not done here\r
-\r
// main68k map (BIOS mapped by PicoMemSetup()):\r
// RAM cart\r
if (PicoOpt & POPT_EN_MCD_RAMCART) {\r
cpu68k_map_set(s68k_read16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
cpu68k_map_set(s68k_write8_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
cpu68k_map_set(s68k_write16_map, 0x000000, 0x07ffff, Pico_mcd->prg_ram, 0);\r
+ cpu68k_map_set(s68k_write8_map, 0x000000, 0x00ffff, PicoWriteS68k8_prgwp, 1);\r
+ cpu68k_map_set(s68k_write16_map, 0x000000, 0x00ffff, PicoWriteS68k16_prgwp, 1);\r
\r
// BRAM\r
cpu68k_map_set(s68k_read8_map, 0xfe0000, 0xfeffff, PicoReadS68k8_bram, 1);\r
cpu68k_map_set(s68k_write8_map, 0xff0000, 0xffffff, PicoWriteS68k8_pr, 1);\r
cpu68k_map_set(s68k_write16_map, 0xff0000, 0xffffff, PicoWriteS68k16_pr, 1);\r
\r
+ // RAMs\r
+ remap_word_ram(1);\r
+\r
#ifdef EMU_C68K\r
// s68k\r
PicoCpuCS68k.read8 = (void *)s68k_read8_map;\r
// WORD RAM 2M area\r
for (i = M68K_FETCHBANK1*0x08/0x100; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < 0xc0000; i++)\r
PicoCpuFS68k.Fetch[i] = (unsigned int)Pico_mcd->word_ram2M - 0x80000;\r
- // PicoMemRemapCD() will setup word ram for both\r
+ // remap_word_ram() will setup word ram for both\r
}\r
#endif\r
#ifdef EMU_M68K\r
@ vim:filetype=armasm
@ Memory I/O handlers for Sega/Mega CD emulation
-@ (c) Copyright 2007, Grazvydas "notaz" Ignotas
-
+@ (c) Copyright 2007-2009, Grazvydas "notaz" Ignotas
.equiv PCM_STEP_SHIFT, 11
-.equiv POLL_LIMIT, 16
-
-@ jump tables
-.data
-.align 4
-
-.altmacro
-.macro mk_m68k_jump_table on sz @ operation name, size
- .long m_m68k_&\on&\sz&_bios @ 0x000000 - 0x01ffff
- .long m_m68k_&\on&\sz&_prgbank @ 0x020000 - 0x03ffff
- .long m_&\on&_null, m_&\on&_null @ 0x040000 - 0x07ffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x080000 - 0x0fffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x100000 - 0x17ffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x180000 - 0x1fffff
- .long m_m68k_&\on&\sz&_wordram0_2M @ 0x200000 - 0x21ffff
- .long m_m68k_&\on&\sz&_wordram1_2M @ 0x220000 - 0x23ffff
- .long m_&\on&_null, m_&\on&_null @ 0x240000 - 0x27ffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x280000 - 0x2fffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x300000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x3fffff
- .long m_m68k_&\on&\sz&_bcram_size @ 0x400000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x420000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x4fffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x500000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x5fffff
- .long m_m68k_&\on&\sz&_bcram @ 0x600000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x620000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x6fffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x700000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x7dffff
- .long m_m68k_&\on&\sz&_bcram_reg @ 0x7e0000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x800000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x8fffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0x900000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0x9fffff
- .long m_m68k_&\on&\sz&_system_io @ 0xa00000 - 0xa1ffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa20000 - 0xa7ffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xa80000 - 0xafffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xb00000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xbfffff
- .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ 0xc00000
- .long m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp, m_m68k_&\on&\sz&_vdp @ - 0xcfffff
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ 0xd00000
- .long m_&\on&_null, m_&\on&_null, m_&\on&_null, m_&\on&_null @ - 0xdfffff
- .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xe00000
- .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xefffff
- .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ 0xf00000
- .long m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram, m_m68k_&\on&\sz&_ram @ - 0xffffff
-.endm
-
-.macro mk_s68k_jump_table on sz @ operation name, size
- .long m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg, m_s68k_&\on&\sz&_prg @ 0x000000 - 0x07ffff
- .long m_s68k_&\on&\sz&_wordram_2M @ 0x080000 - 0x09ffff
- .long m_s68k_&\on&\sz&_wordram_2M @ 0x0a0000 - 0x0bffff
- .long m_&\on&_null @ 0x0c0000 - 0x0dffff, 1M area
- .long m_&\on&_null @ 0x0e0000 - 0x0fffff
-.endm
-
-
-@ the jumptables themselves.
-m_m68k_read8_table: mk_m68k_jump_table read 8
-m_m68k_read16_table: mk_m68k_jump_table read 16
-m_m68k_read32_table: mk_m68k_jump_table read 32
-m_m68k_write8_table: mk_m68k_jump_table write 8
-m_m68k_write16_table: mk_m68k_jump_table write 16
-m_m68k_write32_table: mk_m68k_jump_table write 32
-
-m_s68k_read8_table: mk_s68k_jump_table read 8
-m_s68k_read16_table: mk_s68k_jump_table read 16
-m_s68k_read32_table: mk_s68k_jump_table read 32
-m_s68k_write8_table: mk_s68k_jump_table write 8
-m_s68k_write16_table: mk_s68k_jump_table write 16
-m_s68k_write32_table: mk_s68k_jump_table write 32
-
-m_s68k_decode_write_table:
- .long m_s68k_write8_2M_decode_b0_m0
- .long m_s68k_write16_2M_decode_b0_m0
- .long m_s68k_write32_2M_decode_b0_m0
- .long m_s68k_write8_2M_decode_b0_m1
- .long m_s68k_write16_2M_decode_b0_m1
- .long m_s68k_write32_2M_decode_b0_m1
- .long m_s68k_write8_2M_decode_b0_m2
- .long m_s68k_write16_2M_decode_b0_m2
- .long m_s68k_write32_2M_decode_b0_m2
- .long m_s68k_write8_2M_decode_b1_m0
- .long m_s68k_write16_2M_decode_b1_m0
- .long m_s68k_write32_2M_decode_b1_m0
- .long m_s68k_write8_2M_decode_b1_m1
- .long m_s68k_write16_2M_decode_b1_m1
- .long m_s68k_write32_2M_decode_b1_m1
- .long m_s68k_write8_2M_decode_b1_m2
- .long m_s68k_write16_2M_decode_b1_m2
- .long m_s68k_write32_2M_decode_b1_m2
-
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
.text
-.align 4
-
-.global PicoMemResetCD
-.global PicoMemResetCDdecode
-.global PicoReadM68k8
-.global PicoReadM68k16
-.global PicoReadM68k32
-.global PicoWriteM68k8
-.global PicoWriteM68k16
-.global PicoWriteM68k32
-.global PicoReadS68k8
-.global PicoReadS68k16
-.global PicoReadS68k32
-.global PicoWriteS68k8
-.global PicoWriteS68k16
-.global PicoWriteS68k32
+.align 2
+
+.global PicoReadM68k8_io
+.global PicoReadM68k16_io
+.global PicoWriteM68k8_io
+.global PicoWriteM68k16_io
+
+.global PicoReadS68k8_pr
+.global PicoReadS68k16_pr
+.global PicoWriteS68k8_pr
+.global PicoWriteS68k16_pr
+
+.global PicoReadM68k8_cell0
+.global PicoReadM68k8_cell1
+.global PicoReadM68k16_cell0
+.global PicoReadM68k16_cell1
+.global PicoWriteM68k8_cell0
+.global PicoWriteM68k8_cell1
+.global PicoWriteM68k16_cell0
+.global PicoWriteM68k16_cell1
+
+.global PicoReadS68k8_dec0
+.global PicoReadS68k8_dec1
+.global PicoReadS68k16_dec0
+.global PicoReadS68k16_dec1
+.global PicoWriteS68k8_dec_m0b0
+.global PicoWriteS68k8_dec_m1b0
+.global PicoWriteS68k8_dec_m2b0
+.global PicoWriteS68k8_dec_m0b1
+.global PicoWriteS68k8_dec_m1b1
+.global PicoWriteS68k8_dec_m2b1
+.global PicoWriteS68k16_dec_m0b0
+.global PicoWriteS68k16_dec_m1b0
+.global PicoWriteS68k16_dec_m2b0
+.global PicoWriteS68k16_dec_m0b1
+.global PicoWriteS68k16_dec_m1b1
+.global PicoWriteS68k16_dec_m2b1
@ externs, just for reference
.extern Pico
-.extern z80Read8
-.extern OtherRead16
-.extern PicoVideoRead
-.extern PicoVideoRead8
.extern Read_CDC_Host
.extern m68k_reg_write8
-.extern OtherWrite16
-.extern gfx_cd_read
.extern s68k_reg_read16
-.extern SRam
-.extern gfx_cd_write16
.extern s68k_reg_write8
.extern s68k_poll_adclk
-.extern PicoCpuMS68k
.extern s68k_poll_detect
-.extern SN76496Write
-.extern m_m68k_read8_misc
-.extern m_m68k_write8_misc
-
-
-@ r0=reg3, r1-r3=temp
-.macro mk_update_table on sz @ operation name, size
- @ we only set word-ram handlers
- ldr r1, =m_m68k_&\on&\sz&_table
- ldr r12,=m_s68k_&\on&\sz&_table
- tst r0, #4
- bne 0f @ pmr_8_1M
-
-@ pmr_8_2M:
- ldr r2, =m_m68k_&\on&\sz&_wordram0_2M
- ldr r3, =m_s68k_&\on&\sz&_wordram_2M
- str r2, [r1, #16*4]
- str r2, [r1, #17*4]
- ldr r2, =m_&\on&_null
- str r3, [r12,#4*4]
- str r3, [r12,#5*4]
- str r2, [r12,#6*4]
- b 9f @ pmr_8_done
-
-0: @ pmr_8_1M:
- tst r0, #1
- bne 1f @ pmr_8_1M1
-
-@ pmr_8_1M0:
- ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b0
- ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b0
- str r2, [r1, #16*4]
- str r3, [r1, #17*4]
- ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b1
-.ifeqs "\on", "read"
- ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b1
- str r2, [r12,#4*4]
- str r2, [r12,#5*4]
-.endif
- str r3, [r12,#6*4]
- b 9f @ pmr_8_done
-
-1: @ pmr_8_1M1:
- ldr r2, =m_m68k_&\on&\sz&_wordram0_1M_b1
- ldr r3, =m_m68k_&\on&\sz&_wordram1_1M_b1
- str r2, [r1, #16*4]
- str r3, [r1, #17*4]
- ldr r3, =m_s68k_&\on&\sz&_wordram_1M_b0
-.ifeqs "\on", "read"
- ldr r2, =m_s68k_&\on&\sz&_wordram_2M_decode_b0
- str r2, [r12,#4*4]
- str r2, [r12,#5*4]
-.endif
- str r3, [r12,#6*4]
-
-9: @ pmr_8_done:
-.endm
-
-
-PicoMemResetCD: @ r3
- mk_update_table read 8
- mk_update_table read 16
- mk_update_table read 32
- mk_update_table write 8
- mk_update_table write 16
- mk_update_table write 32
- bx lr
-
-
-PicoMemResetCDdecode: @reg3
- tst r0, #4
- bxeq lr @ we should not be called in 2M mode
- ldr r1, =m_s68k_write8_table
- ldr r3, =m_s68k_decode_write_table
- and r2, r0, #0x18
- mov r2, r2, lsr #3
- cmp r2, #3
- moveq r2, #2 @ mode3 is same as mode2?
- tst r0, #1
- addeq r2, r2, #3 @ bank1 (r2=0..5)
- add r2, r2, r2, lsl #1 @ *= 3
- add r2, r3, r2, lsl #2
- ldmia r2, {r0,r3,r12}
- str r0, [r1, #4*4]
- str r0, [r1, #5*4]
- str r3, [r1, #4*4+8*4]
- str r3, [r1, #5*4+8*4]
- str r12,[r1, #4*4+8*4*2]
- str r12,[r1, #5*4+8*4*2]
- bx lr
-
-
-.pool
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-.macro mk_entry_m68k table
- ldr r2, =\table
- bic r0, r0, #0xff000000
- and r3, r0, #0x00fe0000
- ldr pc, [r2, r3, lsr #15]
-.endm
-
-PicoReadM68k8: @ u32 a
- mk_entry_m68k m_m68k_read8_table
-
-PicoReadM68k16: @ u32 a
- mk_entry_m68k m_m68k_read16_table
-
-PicoReadM68k32: @ u32 a
- mk_entry_m68k m_m68k_read32_table
-
-PicoWriteM68k8: @ u32 a, u8 d
- mk_entry_m68k m_m68k_write8_table
-
-PicoWriteM68k16: @ u32 a, u16 d
- mk_entry_m68k m_m68k_write16_table
-
-PicoWriteM68k32: @ u32 a, u32 d
- mk_entry_m68k m_m68k_write32_table
-
-
-.macro mk_entry_s68k on sz
- bic r0, r0, #0xff000000
- cmp r0, #0x00080000
- blt m_s68k_&\on&\sz&_prg
- cmp r0, #0x000e0000
- ldrlt r2, =m_s68k_&\on&\sz&_table
- andlt r3, r0, #0x000e0000
- ldrlt pc, [r2, r3, lsr #15]
- mov r3, #0x00ff0000
- orr r3, r3, #0x00008000
- cmp r0, r3
- bge m_s68k_&\on&\sz&_regs
- cmp r0, #0x00ff0000
- bge m_s68k_&\on&\sz&_pcm
- cmp r0, #0x00fe0000
- bge m_s68k_&\on&\sz&_backup
- mov r0, #0
- bx lr
-.endm
-
-PicoReadS68k8: @ u32 a
- mk_entry_s68k read 8
-
-PicoReadS68k16: @ u32 a
- mk_entry_s68k read 16
-
-PicoReadS68k32: @ u32 a
- mk_entry_s68k read 32
-
-PicoWriteS68k8: @ u32 a, u8 d
- mk_entry_s68k write 8
-
-PicoWriteS68k16: @ u32 a, u16 d
- mk_entry_s68k write 16
-
-PicoWriteS68k32: @ u32 a, u32 d
- mk_entry_s68k write 32
-
+.extern gfx_cd_read
+.extern gfx_cd_write16
+.extern PicoCpuCS68k
+.extern PicoRead8_io
+.extern PicoRead16_io
+.extern PicoWrite8_io
+.extern PicoWrite16_io
-.pool
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
.endm
-@ r0=prt1, r1=ptr2; unaligned ptr MUST be r0
-.macro m_read32_gen
- tst r0, #2
- ldrneh r0, [r1, r0]!
- ldrneh r1, [r1, #2]
- ldreq r0, [r1, r0]
- moveq r0, r0, ror #16
- orrne r0, r1, r0, lsl #16
-.endm
-
-
-@ r0=prt1, r1=data, r2=ptr2; unaligned ptr MUST be r0
-.macro m_write32_gen
- tst r0, #2
- mov r1, r1, ror #16
- strneh r1, [r2, r0]!
- movne r1, r1, lsr #16
- strneh r1, [r2, #2]
- streq r1, [r2, r0]
-.endm
-
-@
-.macro bcram_reg_rw is_read addr_check
- rsb r0, r0, #0x800000
- ldr r2, =(Pico+0x22200)
- cmp r0, #(0x800000-\addr_check)
- ldreq r2, [r2]
-.if \is_read
- movne r0, #0
-.endif
- bxne lr
- add r2, r2, #0x110000
- add r2, r2, #0x002200
-.if \is_read
- ldrb r0, [r2, #0x18] @ Pico_mcd->m.bcram_reg
-.else
- strb r1, [r2, #0x18]
-.endif
- bx lr
-.endm
-
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
bx lr
-m_m68k_read8_bios:
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #0xfe0000
- ldr r1, [r1]
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_prgbank:
- ldr r1, =(Pico+0x22200)
- eor r0, r0, #1
- ldr r1, [r1]
- mov r2, #0x110000
- orr r3, r2, #0x002200
- ldr r3, [r1, r3]
- ldr r2, [r1, r2]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- moveq r0, #0
- bxeq lr
- and r2, r2, #0xc0000000 @ r3 & 0xC0
- add r1, r1, r2, lsr #12
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_read8_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r1, [r1]
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r1, [r1]
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r1, [r1]
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r1, [r1]
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
+PicoReadM68k8_cell0: @ 0x220000 - 0x23ffff, cell arranged
+ mov r3, #0x0c0000
+ b 0f
-m_m68k_read8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
+PicoReadM68k8_cell1: @ 0x220000 - 0x23ffff, cell arranged
+ mov r3, #0x0e0000
+0:
cell_map
ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0e0000
+ add r0, r0, r3
ldr r1, [r1]
eor r0, r0, #1
ldrb r0, [r1, r0]
bx lr
-m_m68k_read8_bcram_size: @ 0x400000
- sub r0, r0, #1
- cmp r0, #0x400000
- ldreq r1, =SRam
- mov r0, #0
- ldreq r1, [r1]
- bxne lr
- tst r1, r1
- movne r0, #3 @ pretend to be a 64k cart (8<<3)
- bx lr
-
-
-m_m68k_read8_bcram: @ 0x600000 - 0x61ffff
- ldr r1, =SRam
- bic r0, r0, #0xfe0000
- ldr r1, [r1]
- mov r0, r0, lsr #1
- tst r1, r1
- moveq r0, #0
- bxeq lr
- add r1, r1, #0x2000
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_m68k_read8_bcram_reg: @ 0x7fffff
- bcram_reg_rw 1, 0x7fffff
-
-
-m_m68k_read8_system_io:
- bic r2, r0, #0xfe0000
- bic r2, r2, #0x3f
- cmp r2, #0x012000
- bne m_m68k_read8_misc @ now from Pico/Memory.s
+PicoReadM68k8_io:
+ and r1, r0, #0xff00
+ cmp r1, #0x2000 @ a120xx?
+ bne PicoRead8_io
ldr r1, =(Pico+0x22200)
and r0, r0, #0x3f
ldrb r0, [r1, r0]
bx lr
-/*
-m_m68k_read8_misc:
- bic r2, r0, #0x00ff
- bic r2, r2, #0xbf00
- cmp r2, #0xa00000 @ Z80 RAM?
- beq z80Read8
-@ ldreq r2, =z80Read8
-@ bxeq r2
- stmfd sp!,{r0,lr}
- bic r0, r0, #1
- mov r1, #8
- bl OtherRead16 @ non-MCD version should be ok too
- ldmfd sp!,{r1,lr}
- tst r1, #1
- moveq r0, r0, lsr #8
- bx lr
-*/
-
-m_m68k_read8_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid read
- b PicoVideoRead8
-
-
-m_m68k_read8_ram:
- ldr r1, =Pico
- bic r0, r0, #0xff0000
- eor r0, r0, #1
- ldrb r0, [r1, r0]
- bx lr
-
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-m_m68k_read16_bios:
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #0xfe0000
- ldr r1, [r1]
- bic r0, r0, #1
- ldrh r0, [r1, r0]
- bx lr
-
-
-m_m68k_read16_prgbank:
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r1, [r1]
- mov r2, #0x110000
- orr r3, r2, #0x002200
- ldr r3, [r1, r3]
- ldr r2, [r1, r2]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- moveq r0, #0
- bxeq lr
- and r2, r2, #0xc0000000 @ r3 & 0xC0
- add r1, r1, r2, lsr #12
- ldrh r0, [r1, r0]
- bx lr
-
-
-m_m68k_read16_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_read16_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r1, [r1]
- bic r0, r0, #1
- ldrh r0, [r1, r0]
- bx lr
-
-
-m_m68k_read16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r1, [r1]
- bic r0, r0, #1
- ldrh r0, [r1, r0]
- bx lr
-
-
-m_m68k_read16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r1, [r1]
- bic r0, r0, #1
- ldrh r0, [r1, r0]
- bx lr
-
-
-m_m68k_read16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- @ Warning: read32 relies on NOT using r3 and r12 here
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r1, [r1]
- bic r0, r0, #1
- ldrh r0, [r1, r0]
- bx lr
-
+PicoReadM68k16_cell0: @ 0x220000 - 0x23ffff, cell arranged
+ mov r3, #0x0c0000
+ b 0f
-m_m68k_read16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
+PicoReadM68k16_cell1: @ 0x220000 - 0x23ffff, cell arranged
+ mov r3, #0x0e0000
+0:
cell_map
ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0e0000
+ add r0, r0, r3
ldr r1, [r1]
bic r0, r0, #1
ldrh r0, [r1, r0]
bx lr
-m_m68k_read16_bcram_size: @ 0x400000
- cmp r0, #0x400000
- ldreq r1, =SRam
- mov r0, #0
- ldreq r1, [r1]
- bxne lr
- tst r1, r1
- movne r0, #3 @ pretend to be a 64k cart
- bx lr
-
-
-@ m_m68k_read16_bcram: @ 0x600000 - 0x61ffff
-.equiv m_m68k_read16_bcram, m_m68k_read8_bcram
-
-
-m_m68k_read16_bcram_reg: @ 0x7fffff
- bcram_reg_rw 1, 0x7ffffe
-
-
-m_m68k_read16_system_io:
- bic r1, r0, #0xfe0000
- bic r1, r1, #0x3f
- cmp r1, #0x012000
- bne m_m68k_read16_misc
+PicoReadM68k16_io:
+ and r1, r0, #0xff00
+ cmp r1, #0x2000 @ a120xx
+ bne PicoRead16_io
m_m68k_read16_m68k_regs:
ldr r1, =(Pico+0x22200)
bx lr
-m_m68k_read16_misc:
- bic r0, r0, #1
- mov r1, #16
- b OtherRead16
-
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-m_m68k_read16_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid read
- bic r0, r0, #1
- b PicoVideoRead
+PicoWriteM68k8_cell0: @ 0x220000 - 0x23ffff, cell arranged
+ mov r12,#0x0c0000
+ b 0f
-m_m68k_read16_ram:
- ldr r1, =Pico
- bic r0, r0, #0xff0000
- bic r0, r0, #1
- ldrh r0, [r1, r0]
+PicoWriteM68k8_cell1: @ 0x220000 - 0x23ffff, cell arranged
+ mov r12,#0x0e0000
+0:
+ mov r3, r1
+ cell_map
+ ldr r2, =(Pico+0x22200)
+ add r0, r0, r12
+ ldr r2, [r2]
+ eor r0, r0, #1
+ strb r3, [r2, r0]
bx lr
+PicoWriteM68k8_io:
+ and r2, r0, #0xff00
+ cmp r2, #0x2000 @ a120xx?
+ beq m68k_reg_write8
+ b PicoWrite8_io
+
+
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-m_m68k_read32_bios:
+PicoWriteM68k16_cell0: @ 0x220000 - 0x23ffff, cell arranged
+ mov r12, #0x0c0000
+ b 0f
+
+PicoWriteM68k16_cell1: @ 0x220000 - 0x23ffff, cell arranged
+ mov r12, #0x0e0000
+0:
+ mov r3, r1
+ cell_map
ldr r1, =(Pico+0x22200)
- bic r0, r0, #0xfe0000
+ add r0, r0, r12
ldr r1, [r1]
bic r0, r0, #1
- m_read32_gen
+ strh r3, [r1, r0]
bx lr
-m_m68k_read32_prgbank:
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r1, [r1]
- mov r2, #0x110000
- orr r3, r2, #0x002200
- ldr r3, [r1, r3]
- ldr r2, [r1, r2]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- moveq r0, #0
- bxeq lr
- and r2, r2, #0xc0000000 @ r3 & 0xC0
- add r1, r1, r2, lsr #12
- m_read32_gen
- bx lr
+PicoWriteM68k16_io:
+ and r2, r0, #0xff00
+ cmp r2, #0x2000 @ a120xx?
+ bne PicoWrite16_io
+m_m68k_write16_regs:
+ and r0, r0, #0x3e
+ cmp r0, #0x0e
+ beq m_m68k_write16_regs_spec
+ and r3, r1, #0xff
+ add r2, r0, #1
+ stmfd sp!,{r2,r3,lr}
+ mov r1, r1, lsr #8
+ bl m68k_reg_write8
+ ldmfd sp!,{r0,r1,lr}
+ b m68k_reg_write8
-m_m68k_read32_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_read32_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r1, [r1]
- bic r0, r0, #1
- m_read32_gen
+m_m68k_write16_regs_spec: @ special case
+ ldr r2, =(Pico+0x22200)
+ ldr r3, =s68k_poll_adclk
+ mov r0, #0x110000
+ ldr r2, [r2]
+ add r0, r0, #0x00000e
+ mov r1, r1, lsr #8
+ strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
+ ldr r2, [r3]
+ mov r1, #0
+ and r2, r2, #0xfe
+ cmp r2, #0x0e
+ bxne lr
+ ldr r0, =PicoCpuCS68k
+ str r1, [r0, #0x58] @ push s68k out of stopped state
+ str r1, [r3]
bx lr
-m_m68k_read32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r1, [r1]
- bic r0, r0, #1
- m_read32_gen
- bx lr
-
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
+@ Sub 68k
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-m_m68k_read32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r1, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r1, [r1]
- bic r0, r0, #1
- m_read32_gen
- bx lr
+PicoReadS68k8_dec0: @ 0x080000 - 0x0bffff
+ mov r3, #0x080000 @ + ^ / 2
+ b 0f
-m_m68k_read32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- tst r0, #2
- bne m_m68k_read32_wordram1_1M_b0_unal
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r1, [r1]
- bic r0, r0, #1
- m_read32_gen
- bx lr
-m_m68k_read32_wordram1_1M_b0_unal:
- @ hopefully this doesn't happen too often
- mov r12,lr
- mov r3, r0
- bl m_m68k_read16_wordram1_1M_b0 @ must not trash r12 and r3
- add r1, r3, #2
- mov r3, r0
- mov r0, r1
- bl m_m68k_read16_wordram1_1M_b0
- orr r0, r0, r3, lsl #16
- bx r12
-
-
-m_m68k_read32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
- tst r0, #2
- bne m_m68k_read32_wordram1_1M_b1_unal
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0e0000
- ldr r1, [r1]
- bic r0, r0, #1
- m_read32_gen
- bx lr
-m_m68k_read32_wordram1_1M_b1_unal:
- mov r12,lr
- mov r3, r0
- bl m_m68k_read16_wordram1_1M_b1 @ must not trash r12 and r3
- add r1, r3, #2
- mov r3, r0
- mov r0, r1
- bl m_m68k_read16_wordram1_1M_b1
- orr r0, r0, r3, lsl #16
- bx r12
-
-
-m_m68k_read32_bcram_size: @ 0x400000
- cmp r0, #0x400000
- ldreq r1, =SRam
- mov r0, #0
- ldreq r1, [r1]
- bxne lr
- tst r1, r1
- movne r0, #0x30000 @ pretend to be a 64k cart
- bx lr
-
-
-m_m68k_read32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
- mov r12,lr
- add r3, r0, #2
- bl m_m68k_read8_bcram
- mov r1, r0
- mov r0, r3
- mov r3, r1
- bl m_m68k_read8_bcram
- orr r0, r0, r3, lsl #16
- bx r12
-
-
-m_m68k_read32_bcram_reg: @ 0x7fffff
- bcram_reg_rw 1, 0x7ffffc
-
-
-@ it is not very practical to use long access on hw registers, so I assume it is not used too much.
-m_m68k_read32_system_io:
- bic r1, r0, #0xfe0000
- bic r1, r1, #0x3f
- cmp r1, #0x012000
- bne m_m68k_read32_misc
- and r1, r0, #0x3e
- cmp r1, #0x0e
- blt m_m68k_read32_misc
- cmp r1, #0x30
- movge r0, #0
- bxge lr
- @ I have seen the range 0x0e-0x2f accessed quite frequently with long i/o, so here is some code for that
- mov r0, r1
- ldr r1, =(Pico+0x22200)
- mov r2, #0xff
- ldr r1, [r1]
- orr r2, r2, r2, lsl #16
- add r1, r1, #0x110000
- m_read32_gen
- and r1, r2, r0 @ data is big-endian read as little, have to byteswap
- and r0, r2, r0, lsr #8
- orr r0, r0, r1, lsl #8
- bx lr
-
-m_m68k_read32_misc:
- add r1, r0, #2
- stmfd sp!,{r1,lr}
- bl m_m68k_read16_system_io
- swp r0, r0, [sp]
- bl m_m68k_read16_system_io
- ldmfd sp!,{r1,lr}
- orr r0, r0, r1, lsl #16
- bx lr
-
-
-m_m68k_read32_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid read
- bic r0, r0, #1
- add r1, r0, #2
- stmfd sp!,{r1,lr}
- bl PicoVideoRead
- swp r0, r0, [sp]
- bl PicoVideoRead
- ldmfd sp!,{r1,lr}
- orr r0, r0, r1, lsl #16
- bx lr
-
-
-m_m68k_read32_ram:
- ldr r1, =Pico
- bic r0, r0, #0xff0000
- bic r0, r0, #1
- m_read32_gen
- bx lr
-
-.pool
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-
-m_write_null:
-m_m68k_write8_bios:
-m_m68k_write8_bcram_size: @ 0x400000
- bx lr
-
-
-m_m68k_write8_prgbank:
- ldr r2, =(Pico+0x22200)
- eor r0, r0, #1
- ldr r2, [r2]
- mov r12,#0x110000
- orr r3, r12, #0x002200
- ldr r3, [r2, r3]
- ldr r12,[r2, r12]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- bxeq lr
- and r12,r12,#0xc0000000 @ r3 & 0xC0
- add r2, r2, r12, lsr #12
- strb r1, [r2, r0]
- bx lr
-
-
-m_m68k_write8_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_write8_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r2, [r2]
- eor r0, r0, #1
- strb r1, [r2, r0]
- bx lr
-
-
-m_m68k_write8_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r2, [r2]
- eor r0, r0, #1
- strb r1, [r2, r0]
- bx lr
-
-
-m_m68k_write8_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r2, [r2]
- eor r0, r0, #1
- strb r1, [r2, r0]
- bx lr
-
-
-m_m68k_write8_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- mov r3, r1
- cell_map
- ldr r2, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r2, [r2]
- eor r0, r0, #1
- strb r3, [r2, r0]
- bx lr
-
-
-m_m68k_write8_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
- mov r3, r1
- cell_map
- ldr r2, =(Pico+0x22200)
- add r0, r0, #0x0e0000
- ldr r2, [r2]
- eor r0, r0, #1
- strb r3, [r2, r0]
- bx lr
-
-
-m_m68k_write8_bcram: @ 0x600000 - 0x61ffff
- @ can't use r3 or r12, because of write32
- ldr r2, =SRam
- bic r0, r0, #0xfe0000
- ldr r2, [r2]
- tst r2, r2
- bxeq lr
- add r0, r2, r0, lsr #1
- ldr r2, =(Pico+0x22200)
- ldr r2, [r2]
- add r0, r0, #0x2000
- add r2, r2, #0x110000
- add r2, r2, #0x002200
- ldr r2, [r2, #0x18]
- tst r2, #1 @ check bcram reg
- bxeq lr
- strb r1, [r0]
- ldr r2, =SRam
- mov r0, #1
- strb r0, [r2, #0x0e] @ SRam.changed = 1
- bx lr
-
-
-m_m68k_write8_bcram_reg: @ 0x7fffff
- bcram_reg_rw 0, 0x7fffff
-
-
-m_m68k_write8_system_io:
- bic r2, r0, #0xfe0000
- bic r2, r2, #0x3f
- cmp r2, #0x012000
- beq m68k_reg_write8
- mov r2, #8
-@ b OtherWrite8
- b m_m68k_write8_misc
-
-
-m_m68k_write8_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid
- and r2, r0, #0x19
- cmp r2, #0x11
- andeq r0, r1, #0xff
- beq SN76496Write
- and r1, r1, #0xff
- orr r1, r1, r1, lsl #8 @ byte access gets mirrored
- b PicoVideoWrite
-
-
-m_m68k_write8_ram:
- ldr r2, =Pico
- bic r0, r0, #0xff0000
- eor r0, r0, #1
- strb r1, [r2, r0]
- bx lr
-
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-
-m_m68k_write16_bios:
-m_m68k_write16_bcram_size: @ 0x400000
- bx lr
-
-
-m_m68k_write16_prgbank:
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
- mov r12,#0x110000
- orr r3, r12, #0x002200
- ldr r3, [r2, r3]
- ldr r12,[r2, r12]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- bxeq lr
- and r12,r12,#0xc0000000 @ r3 & 0xC0
- add r2, r2, r12, lsr #12
- strh r1, [r2, r0]
- bx lr
-
-
-m_m68k_write16_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_write16_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r2, [r2]
- bic r0, r0, #1
- strh r1, [r2, r0]
- bx lr
-
-
-m_m68k_write16_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r2, [r2]
- bic r0, r0, #1
- strh r1, [r2, r0]
- bx lr
-
-
-m_m68k_write16_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r2, [r2]
- bic r0, r0, #1
- strh r1, [r2, r0]
- bx lr
-
-
-m_m68k_write16_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- @ Warning: write32 relies on NOT using r12 and and keeping data in r3
- mov r3, r1
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r1, [r1]
- bic r0, r0, #1
- strh r3, [r1, r0]
- bx lr
-
-
-m_m68k_write16_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
- mov r3, r1
- cell_map
- ldr r1, =(Pico+0x22200)
- add r0, r0, #0x0e0000
- ldr r1, [r1]
- bic r0, r0, #1
- strh r3, [r1, r0]
- bx lr
-
-
-@ m_m68k_write16_bcram: @ 0x600000 - 0x61ffff
-.equiv m_m68k_write16_bcram, m_m68k_write8_bcram
-
-
-m_m68k_write16_bcram_reg: @ 0x7fffff
- bcram_reg_rw 0, 0x7ffffe
-
-
-m_m68k_write16_system_io:
- bic r0, r0, #1
- bic r2, r0, #0xfe0000
- bic r2, r2, #0x3f
- cmp r2, #0x012000
- bne OtherWrite16
-
-m_m68k_write16_regs:
- and r0, r0, #0x3e
- cmp r0, #0x0e
- beq m_m68k_write16_regs_spec
- and r3, r1, #0xff
- add r2, r0, #1
- stmfd sp!,{r2,r3,lr}
- mov r1, r1, lsr #8
- bl m68k_reg_write8
- ldmfd sp!,{r0,r1,lr}
- b m68k_reg_write8
-
-m_m68k_write16_regs_spec: @ special case
- ldr r2, =(Pico+0x22200)
- ldr r3, =s68k_poll_adclk
- mov r0, #0x110000
- ldr r2, [r2]
- add r0, r0, #0x00000e
- mov r1, r1, lsr #8
- strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0x0e] = d >> 8;
- ldr r2, [r3]
- mov r1, #0
- and r2, r2, #0xfe
- cmp r2, #0x0e
- bxne lr
- ldr r0, =PicoCpuCS68k
- str r1, [r0, #0x58] @ push s68k out of stopped state
- str r1, [r3]
- bx lr
-
-
-m_m68k_write16_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid
- bic r0, r0, #1
- and r2, r0, #0x18
- cmp r2, #0x10
- bne PicoVideoWrite
- and r0, r1, #0xff
- b SN76496Write @ lsb goes to 0x11
-
-
-m_m68k_write16_ram:
- ldr r2, =Pico
- bic r0, r0, #0xff0000
- bic r0, r0, #1
- strh r1, [r2, r0]
- bx lr
-
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-
-m_m68k_write32_bios:
-m_m68k_write32_bcram_size: @ 0x400000
- bx lr
-
-
-m_m68k_write32_prgbank:
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
- mov r12,#0x110000
- orr r3, r12, #0x002200
- ldr r3, [r2, r3]
- ldr r12,[r2, r12]
- and r3, r3, #0x00030000
- cmp r3, #0x00010000 @ have bus or in reset state?
- bxeq lr
- and r12,r12,#0xc0000000 @ r3 & 0xC0
- add r2, r2, r12, lsr #12
- m_write32_gen
- bx lr
-
-
-m_m68k_write32_wordram0_2M: @ 0x200000 - 0x21ffff
-m_m68k_write32_wordram1_2M: @ 0x220000 - 0x23ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x160000 @ map to our offset, which is 0x0a0000
- ldr r2, [r2]
- bic r0, r0, #1
- m_write32_gen
- bx lr
-
-
-m_m68k_write32_wordram0_1M_b0: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x140000 @ map to our offset, which is 0x0c0000
- ldr r2, [r2]
- bic r0, r0, #1
- m_write32_gen
- bx lr
-
-
-m_m68k_write32_wordram0_1M_b1: @ 0x200000 - 0x21ffff
- ldr r2, =(Pico+0x22200)
- sub r0, r0, #0x120000 @ map to our offset, which is 0x0e0000
- ldr r2, [r2]
- bic r0, r0, #1
- m_write32_gen
- bx lr
-
-
-m_m68k_write32_wordram1_1M_b0: @ 0x220000 - 0x23ffff, cell arranged
- tst r0, #2
- bne m_m68k_write32_wordram1_1M_b0_unal
- mov r3, r1
- cell_map
- ldr r2, =(Pico+0x22200)
- add r0, r0, #0x0c0000
- ldr r2, [r2]
- bic r0, r0, #1
- mov r1, r3
- m_write32_gen
- bx lr
-m_m68k_write32_wordram1_1M_b0_unal:
- @ hopefully this doesn't happen too often
- add r12,r0, #2
- mov r1, r1, ror #16
- stmfd sp!,{lr}
- bl m_m68k_write16_wordram1_1M_b0 @ must not trash r12 and keep data in r3
- ldmfd sp!,{lr}
- mov r0, r12
- mov r1, r3, lsr #16
- b m_m68k_write16_wordram1_1M_b0
-
-
-m_m68k_write32_wordram1_1M_b1: @ 0x220000 - 0x23ffff, cell arranged
- tst r0, #2
- bne m_m68k_write32_wordram1_1M_b1_unal
- mov r3, r1
- cell_map
- ldr r2, =(Pico+0x22200)
- add r0, r0, #0x0e0000
- ldr r2, [r2]
- bic r0, r0, #1
- mov r1, r3
- m_write32_gen
- bx lr
-m_m68k_write32_wordram1_1M_b1_unal:
- add r12,r0, #2
- mov r1, r1, ror #16
- stmfd sp!,{lr}
- bl m_m68k_write16_wordram1_1M_b1 @ same as above
- ldmfd sp!,{lr}
- mov r0, r12
- mov r1, r3, lsr #16
- b m_m68k_write16_wordram1_1M_b1
-
-
-m_m68k_write32_bcram: @ 0x600000 - 0x61ffff, not likely to be called
- mov r12,lr
- add r3, r0, #2
- mov r1, r1, ror #16
- bl m_m68k_write8_bcram
- mov r0, r3
- mov r1, r1, ror #16
- bl m_m68k_write8_bcram
- bx r12
-
-
-m_m68k_write32_bcram_reg: @ 0x7fffff
- bcram_reg_rw 0, 0x7ffffc
-
-
-
-@ it is not very practical to use long access on hw registers, so I assume it is not used too much.
-m_m68k_write32_system_io:
- bic r2, r0, #0xfe0000
- bic r2, r2, #0x3f
- cmp r2, #0x012000
- bne m_m68k_write32_misc
- and r2, r0, #0x3e
- cmp r2, #0x20
- bxge lr
- cmp r2, #0x10
- bge m_m68k_write32_regs_comm
- cmp r2, #0x0c
- bge m_m68k_write32_regs_spec @ hits the nasty comm reg qiurk
-
- bic r0, r0, #1
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #24
- bl m68k_reg_write8
- ldr r0, [sp]
- ldr r1, [sp, #4]
- add r0, r0, #1
- mov r1, r1, lsr #16
- bl m68k_reg_write8
- ldr r0, [sp]
- ldr r1, [sp, #4]
- add r0, r0, #2
- mov r1, r1, lsr #8
- bl m68k_reg_write8
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #3
- b m68k_reg_write8
-
-m_m68k_write32_regs_comm: @ Handle the 0x10-0x1f range
- ldr r0, =(Pico+0x22200)
- mov r3, #0xff
- ldr r0, [r0]
- orr r3, r3, r3, lsl #16
- add r0, r0, #0x110000
- and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
- and r1, r3, r1, ror #24
- orr r1, r1, r12,lsl #8 @ end of byteswap
- cmp r2, #0x1e
- strh r1, [r2, r0]!
- ldr r3, =s68k_poll_adclk
- ldr r0, [r3]
- movne r1, r1, lsr #16
- strneh r1, [r2, #2]
- cmp r0, #0x10
- bxlt lr
- ldr r0, =PicoCpuCS68k @ remove poll detected state for s68k
- mov r1, #0
- str r1, [r0, #0x58]
- str r1, [r3]
- bx lr
-
-m_m68k_write32_misc:
- bic r0, r0, #1
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl OtherWrite16
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #2
- b OtherWrite16
-
-m_m68k_write32_regs_spec:
- bic r0, r0, #1
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl m_m68k_write16_regs
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #2
- b m_m68k_write16_regs
-
-
-m_m68k_write32_vdp:
- tst r0, #0x70000
- tsteq r0, #0x000e0
- bxne lr @ invalid
- and r2, r0, #0x18
- cmp r2, #0x10
- moveq r0, r1, lsr #16
- beq SN76496Write @ which game is crazy enough to do that?
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl PicoVideoWrite
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #2
- b PicoVideoWrite
-
-
-m_m68k_write32_ram:
- ldr r2, =Pico
- bic r0, r0, #0xff0000
- bic r0, r0, #1
- m_write32_gen
- bx lr
-
-.pool
-
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-
-.macro m_s68k_read8_ram map_addr
- ldr r1, =(Pico+0x22200)
- eor r0, r0, #1
- ldr r1, [r1]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- ldrb r0, [r1, r0]
- bx lr
-.endm
-
-.macro m_s68k_read8_wordram_2M_decode map_addr
+PicoReadS68k8_dec1:
+ mov r3, #0x0a0000 @ + ^ / 2
+0:
ldr r2, =(Pico+0x22200)
eor r0, r0, #2
ldr r2, [r2]
movs r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
+ add r2, r2, r3 @ map to our address
ldrb r0, [r2, r0]
movcc r0, r0, lsr #4
andcs r0, r0, #0xf
bx lr
-.endm
-
-m_s68k_read8_prg: @ 0x000000 - 0x07ffff
-m_s68k_read8_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_read8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_read8_ram 0x020000
-
-
-m_s68k_read8_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
- m_s68k_read8_wordram_2M_decode 0x080000 @ + ^ / 2
-
-
-m_s68k_read8_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
- m_s68k_read8_wordram_2M_decode 0x0a0000 @ + ^ / 2
-
-
-m_s68k_read8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_read8_ram 0
-
-
-m_s68k_read8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
- @ must not trash r3 and r12
- ldr r1, =(Pico+0x22200)
- mov r0, r0, lsr #1
- ldr r1, [r1]
- bic r0, r0, #0xff0000
- bic r0, r0, #0x00e000
- add r1, r1, #0x110000
- add r1, r1, #0x000200
- ldrb r0, [r1, r0]
- bx lr
-
-
-m_s68k_read8_pcm:
- @ must not trash r3 and r12
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #0xff0000
-@ bic r0, r0, #0x008000
- ldr r1, [r1]
- mov r2, #0x110000
- orr r2, r2, #0x002200
- cmp r0, #0x2000
- bge m_s68k_read8_pcm_ram
- cmp r0, #0x20
- movlt r0, #0
- bxlt lr
- orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
- add r1, r1, r2
- and r2, r0, #0x1c
- ldr r1, [r1, r2, lsl #2]
- tst r0, #2
- moveq r0, r1, lsr #PCM_STEP_SHIFT
- movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
- and r0, r0, #0xff
- bx lr
-
-m_s68k_read8_pcm_ram:
- orr r2, r2, #0x40
- ldr r2, [r1, r2]
- add r1, r1, #0x100000 @ pcm_ram
- and r2, r2, #0x0f000000 @ bank
- add r1, r1, r2, lsr #12
- bic r0, r0, #0x00e000
- mov r0, r0, lsr #1
- ldrb r0, [r1, r0]
- bx lr
+PicoReadS68k8_pr:
+ and r2, r0, #0xfe00
+ cmp r2, #0x8000
+ bne m_s68k_read8_pcm
m_s68k_read8_regs:
bic r0, r0, #0xff0000
bic r0, r0, #0x008000
- tst r0, #0x7e00
- movne r0, #0
- bxne lr
sub r2, r0, #0x0e
cmp r2, #(0x30-0x0e)
blo m_s68k_read8_comm
b s68k_poll_detect
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
+m_s68k_read8_pcm:
+ tst r0, #0x8000
+ bne m_read_null
-.macro m_s68k_read16_ram map_addr
+ @ must not trash r3 and r12
ldr r1, =(Pico+0x22200)
- bic r0, r0, #1
+ bic r0, r0, #0xff0000
+@ bic r0, r0, #0x008000
ldr r1, [r1]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- ldrh r0, [r1, r0]
- bx lr
-.endm
-
-.macro m_s68k_read16_wordram_2M_decode map_addr
- ldr r2, =(Pico+0x22200)
- eor r0, r0, #2
- ldr r2, [r2]
- mov r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
- ldrb r0, [r2, r0]
- orr r0, r0, r0, lsl #4
- bic r0, r0, #0xf0
+ mov r2, #0x110000
+ orr r2, r2, #0x002200
+ cmp r0, #0x2000
+ bge m_s68k_read8_pcm_ram
+ cmp r0, #0x20
+ movlt r0, #0
+ bxlt lr
+ orr r2, r2, #(0x48+8) @ pcm.ch + addr_offset
+ add r1, r1, r2
+ and r2, r0, #0x1c
+ ldr r1, [r1, r2, lsl #2]
+ tst r0, #2
+ moveq r0, r1, lsr #PCM_STEP_SHIFT
+ movne r0, r1, lsr #(PCM_STEP_SHIFT+8)
+ and r0, r0, #0xff
bx lr
-.endm
-
-
-m_s68k_read16_prg: @ 0x000000 - 0x07ffff
-m_s68k_read16_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_read16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_read16_ram 0x020000
-
-m_s68k_read16_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
- m_s68k_read16_wordram_2M_decode 0x080000
-
-
-m_s68k_read16_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
- m_s68k_read16_wordram_2M_decode 0x0a0000
-
-
-m_s68k_read16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_read16_ram 0
-
-
-@ m_s68k_read16_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
-@ bram is not meant to be accessed by words, does any game do this?
-.equiv m_s68k_read16_backup, m_s68k_read8_backup
-
-
-@ m_s68k_read16_pcm:
-@ pcm is on 8-bit bus, would this be same as byte access?
-.equiv m_s68k_read16_pcm, m_s68k_read8_pcm
-
-
-m_s68k_read16_regs:
- bic r0, r0, #0xff0000
- bic r0, r0, #0x008000
- bic r0, r0, #0x000001
- tst r0, #0x7e00
- movne r0, #0
- bxne lr
- sub r2, r0, #0x58
- cmp r2, #0x10
- blo gfx_cd_read
- cmp r0, #8
- bne s68k_reg_read16
- mov r0, #1
- b Read_CDC_Host
+m_s68k_read8_pcm_ram:
+ orr r2, r2, #0x40
+ ldr r2, [r1, r2]
+ add r1, r1, #0x100000 @ pcm_ram
+ and r2, r2, #0x0f000000 @ bank
+ add r1, r1, r2, lsr #12
+ bic r0, r0, #0x00e000
+ mov r0, r0, lsr #1
+ ldrb r0, [r1, r0]
+ bx lr
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-.macro m_s68k_read32_ram map_addr
- ldr r1, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r1, [r1]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- m_read32_gen
- bx lr
-.endm
+PicoReadS68k16_dec0: @ 0x080000 - 0x0bffff
+ mov r3, #0x080000 @ + ^ / 2
+ b 0f
-.macro m_s68k_read32_wordram_2M_decode map_addr
+PicoReadS68k16_dec1:
+ mov r3, #0x0a0000 @ + ^ / 2
+0:
ldr r2, =(Pico+0x22200)
eor r0, r0, #2
ldr r2, [r2]
mov r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
- ldrb r1, [r2, r0]!
- tst r0, #1
- ldrneb r0, [r2, #-1]
- ldreqb r0, [r2, #2]
- orr r1, r1, r1, lsl #4
- bic r1, r1, #0xf0
+ add r2, r2, r3 @ map to our address
+ ldrb r0, [r2, r0]
orr r0, r0, r0, lsl #4
bic r0, r0, #0xf0
- orr r0, r0, r1, lsl #16
bx lr
-.endm
-m_s68k_read32_prg: @ 0x000000 - 0x07ffff
-m_s68k_read32_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_read32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_read32_ram 0x020000
+PicoReadS68k16_pr:
+ and r2, r0, #0xfe00
+ cmp r2, #0x8000
+ @ pcm is on 8-bit bus, would this be same as byte access?
+ bne m_s68k_read8_pcm
-
-m_s68k_read32_wordram_2M_decode_b0: @ 0x080000 - 0x0bffff
- m_s68k_read32_wordram_2M_decode 0x080000
-
-
-m_s68k_read32_wordram_2M_decode_b1: @ 0x080000 - 0x0bffff
- m_s68k_read32_wordram_2M_decode 0x0a0000
-
-
-m_s68k_read32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_read32_ram 0
-
-
-m_s68k_read32_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
- @ bram is not meant to be accessed by words, does any game do this?
- mov r12,lr
- mov r3, r0
- bl m_s68k_read8_backup @ must preserve r3 and r12
- mov r1, r0
- add r0, r3, #2
- mov r3, r1
- bl m_s68k_read8_backup
- orr r0, r0, r3, lsl #16
- bx r12
-
-
-m_s68k_read32_pcm:
- mov r12,lr
- mov r3, r0
- bl m_s68k_read8_pcm @ must preserve r3 and r12
- mov r1, r0
- add r0, r3, #2
- mov r3, r1
- bl m_s68k_read8_pcm
- orr r0, r0, r3, lsl #16
- bx r12
-
-
-m_s68k_read32_regs:
+m_s68k_read16_regs:
bic r0, r0, #0xff0000
bic r0, r0, #0x008000
bic r0, r0, #0x000001
- tst r0, #0x7e00
- movne r0, #0
- bxne lr
sub r2, r0, #0x58
cmp r2, #0x10
- add r1, r0, #2
- blo m_s68k_read32_regs_gfx
- stmfd sp!,{r1,lr}
- bl s68k_reg_read16
- swp r0, r0, [sp]
- bl s68k_reg_read16
- ldmfd sp!,{r1,lr}
- orr r0, r0, r1, lsl #16
- bx lr
-
-
-m_s68k_read32_regs_gfx:
- stmfd sp!,{r1,lr}
- bl gfx_cd_read
- swp r0, r0, [sp]
- bl gfx_cd_read
- ldmfd sp!,{r1,lr}
- orr r0, r0, r1, lsl #16
- bx lr
+ blo gfx_cd_read
+ cmp r0, #8
+ bne s68k_reg_read16
+ mov r0, #1
+ b Read_CDC_Host
-.pool
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-.macro m_s68k_write8_ram map_addr
- ldr r2, =(Pico+0x22200)
- eor r0, r0, #1
- ldr r2, [r2]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- strb r1, [r2, r0]
- bx lr
-.endm
-
-.macro m_s68k_write8_2M_decode map_addr
+.macro m_s68k_write8_2M_decode
ldr r2, =(Pico+0x22200)
eor r0, r0, #2
- ldr r2, [r2]
+ ldr r2, [r2] @ Pico.rom
movs r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
+ add r2, r2, r3 @ map to our address
.endm
-.macro m_s68k_write8_2M_decode_m0 map_addr @ mode off
- m_s68k_write8_2M_decode \map_addr
+PicoWriteS68k8_dec_m2b0: @ overwrite
+ ands r1, r1, #0x0f
+ bxeq lr
+
+PicoWriteS68k8_dec_m0b0:
+ mov r3, #0x080000
+ b 0f
+
+PicoWriteS68k8_dec_m2b1: @ overwrite
+ ands r1, r1, #0x0f
+ bxeq lr
+
+PicoWriteS68k8_dec_m0b1:
+ mov r3, #0x0a0000
+0:
+ m_s68k_write8_2M_decode
ldrb r0, [r2, r0]!
and r1, r1, #0x0f
movcc r1, r1, lsl #4
andcc r3, r0, #0x0f
andcs r3, r0, #0xf0
orr r3, r3, r1
- cmp r0, r3 @ avoid writing if result is same
strneb r3, [r2]
bx lr
-.endm
-.macro m_s68k_write8_2M_decode_m1 map_addr @ mode underwrite
+PicoWriteS68k8_dec_m1b0: @ underwrite
+ mov r3, #0x080000
+ b 0f
+
+PicoWriteS68k8_dec_m1b1:
+ mov r3, #0x0a0000
+0:
ands r1, r1, #0x0f
bxeq lr
- m_s68k_write8_2M_decode \map_addr
+ m_s68k_write8_2M_decode
ldrb r0, [r2, r0]!
movcc r1, r1, lsl #4
andcc r3, r0, #0x0f
andcs r3, r0, #0xf0
- tst r3, r3
- bxeq lr
+ teq r3, r0
+ bxne lr
orr r3, r3, r1
- cmp r0, r3
strneb r3, [r2]
bx lr
-.endm
-
-.macro m_s68k_write8_2M_decode_m2 map_addr @ mode overwrite
- ands r1, r1, #0x0f
- bxeq lr
- m_s68k_write8_2M_decode_m0 \map_addr @ same as in off mode
-.endm
-
-
-
-m_s68k_write8_prg: @ 0x000000 - 0x07ffff
- ldr r2, =(Pico+0x22200)
- eor r0, r0, #1
- ldr r2, [r2]
- add r3, r0, #0x020000 @ map to our address
- add r12,r2, #0x110000
- ldr r12,[r12]
- and r12,r12,#0x00ff0000 @ wp
- cmp r0, r12, lsr #8
- strgeb r1, [r2, r3]
- bx lr
-
-
-m_s68k_write8_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_write8_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_write8_ram 0x020000
-
-
-m_s68k_write8_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
- m_s68k_write8_2M_decode_m0 0x080000
-m_s68k_write8_2M_decode_b0_m1:
- m_s68k_write8_2M_decode_m1 0x080000
-m_s68k_write8_2M_decode_b0_m2:
- m_s68k_write8_2M_decode_m2 0x080000
+PicoWriteS68k8_pr:
+ and r2, r0, #0xfe00
+ cmp r2, #0x8000
+ bne m_s68k_write8_pcm
-m_s68k_write8_2M_decode_b1_m0:
- m_s68k_write8_2M_decode_m0 0x0a0000
-
-m_s68k_write8_2M_decode_b1_m1:
- m_s68k_write8_2M_decode_m1 0x0a0000
-
-m_s68k_write8_2M_decode_b1_m2:
- m_s68k_write8_2M_decode_m2 0x0a0000
-
-
-m_s68k_write8_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_write8_ram 0
-
-
-m_s68k_write8_backup: @ 0xfe0000 - 0xfe3fff (repeated?)
- @ must not trash r3 and r12
- ldr r2, =(Pico+0x22200)
- mov r0, r0, lsr #1
- ldr r2, [r2]
+m_s68k_write8_regs:
bic r0, r0, #0xff0000
- bic r0, r0, #0x00e000
- add r2, r2, #0x110000
- add r2, r2, #0x000200
- strb r1, [r2, r0]
- ldr r1, =SRam
- mov r0, #1
- strb r0, [r1, #0x0e] @ SRam.changed = 1
- bx lr
+ bic r0, r0, #0x008000
+ tst r0, #0x7e00
+ movne r0, #0
+ bxne lr
+ sub r2, r0, #0x58
+ cmp r2, #0x10
+ bhs s68k_reg_write8
+ bic r0, r0, #1
+ orr r1, r1, r1, lsl #8
+ b gfx_cd_write16
m_s68k_write8_pcm:
+ tst r0, #0x8000
+ bxne lr
bic r0, r0, #0xff0000
cmp r0, #0x12
movlt r0, r0, lsr #1
bx lr
-m_s68k_write8_regs:
- bic r0, r0, #0xff0000
- bic r0, r0, #0x008000
- tst r0, #0x7e00
- movne r0, #0
- bxne lr
- sub r2, r0, #0x58
- cmp r2, #0x10
- bhs s68k_reg_write8
- bic r0, r0, #1
- orr r1, r1, r1, lsl #8
- b gfx_cd_write16
-
-
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-.macro m_s68k_write16_ram map_addr
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- strh r1, [r2, r0]
- bx lr
-.endm
-
-.macro m_s68k_write16_2M_decode map_addr
+.macro m_s68k_write16_2M_decode
ldr r2, =(Pico+0x22200)
eor r0, r0, #2
ldr r2, [r2]
mov r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
+ add r2, r2, r3 @ map to our address
.endm
-.macro m_s68k_write16_2M_decode_m0 map_addr @ mode off
- m_s68k_write16_2M_decode \map_addr
+PicoWriteS68k16_dec_m0b0:
+ mov r3, #0x080000
+ b 0f
+
+PicoWriteS68k16_dec_m0b1:
+ mov r3, #0x0a0000
+0:
+ m_s68k_write16_2M_decode
bic r1, r1, #0xf0
orr r1, r1, r1, lsr #4
strb r1, [r2, r0]
bx lr
-.endm
-.macro m_s68k_write16_2M_decode_m1 map_addr @ mode underwrite
+PicoWriteS68k16_dec_m1b0: @ underwrite
+ mov r3, #0x080000
+ b 0f
+
+PicoWriteS68k16_dec_m1b1:
+ mov r3, #0x0a0000
+0:
bics r1, r1, #0xf000
bicnes r1, r1, #0x00f0
bxeq lr
orr r1, r1, r1, lsr #4
- m_s68k_write16_2M_decode \map_addr
+ m_s68k_write16_2M_decode
ldrb r0, [r2, r0]!
and r3, r1, #0x0f
and r1, r1, #0xf0
orreq r0, r0, r1
strb r0, [r2]
bx lr
-.endm
-.macro m_s68k_write16_2M_decode_m2 map_addr @ mode overwrite
+PicoWriteS68k16_dec_m2b0: @ overwrite
+ mov r3, #0x080000
+ b 0f
+
+PicoWriteS68k16_dec_m2b1:
+ mov r3, #0x0a0000
+0:
bics r1, r1, #0xf000
bicnes r1, r1, #0x00f0
bxeq lr
orr r1, r1, r1, lsr #4
- m_s68k_write16_2M_decode \map_addr
+ m_s68k_write16_2M_decode
ldrb r0, [r2, r0]!
ands r3, r1, #0x0f
andne r0, r0, #0xf0
orrne r0, r0, r1
strb r0, [r2]
bx lr
-.endm
-
-
-
-m_s68k_write16_prg: @ 0x000000 - 0x07ffff
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
- add r3, r0, #0x020000 @ map to our address
- add r12,r2, #0x110000
- ldr r12,[r12]
- and r12,r12,#0x00ff0000 @ wp
- cmp r0, r12, lsr #8
- strgeh r1, [r2, r3]
- bx lr
-
-
-m_s68k_write16_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_write16_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_write16_ram 0x020000
-
-
-m_s68k_write16_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
- m_s68k_write16_2M_decode_m0 0x080000
-
-m_s68k_write16_2M_decode_b0_m1:
- m_s68k_write16_2M_decode_m1 0x080000
-m_s68k_write16_2M_decode_b0_m2:
- m_s68k_write16_2M_decode_m2 0x080000
-
-m_s68k_write16_2M_decode_b1_m0:
- m_s68k_write16_2M_decode_m0 0x0a0000
-
-m_s68k_write16_2M_decode_b1_m1:
- m_s68k_write16_2M_decode_m1 0x0a0000
-
-m_s68k_write16_2M_decode_b1_m2:
- m_s68k_write16_2M_decode_m2 0x0a0000
-
-
-m_s68k_write16_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_write16_ram 0
-
-
-@ m_s68k_write16_backup:
-.equiv m_s68k_write16_backup, m_s68k_write8_backup
-
-
-@ m_s68k_write16_pcm:
-.equiv m_s68k_write16_pcm, m_s68k_write8_pcm
+PicoWriteS68k16_pr:
+ and r2, r0, #0xfe00
+ cmp r2, #0x8000
+ bne m_s68k_write8_pcm
m_s68k_write16_regs:
bic r0, r0, #0xff0000
strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
bx lr
-
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-
-
-.macro m_s68k_write32_ram map_addr
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
-.if \map_addr
- add r0, r0, #\map_addr @ map to our address
-.endif
- m_write32_gen
- bx lr
-.endm
-
-.macro m_s68k_write32_2M_decode map_addr
- ldr r2, =(Pico+0x22200)
- eor r0, r0, #2
- ldr r2, [r2]
- mov r0, r0, lsr #1 @ +4-6 <<16
- add r2, r2, #\map_addr @ map to our address
-.endm
-
-.macro m_s68k_write32_2M_decode_m0 map_addr @ mode off
- m_s68k_write32_2M_decode \map_addr
- bic r1, r1, #0x000000f0
- bic r1, r1, #0x00f00000
- orr r1, r1, r1, lsr #4
- mov r3, r1, lsr #16
- strb r3, [r2, r0]!
- tst r0, #1
- strneb r1, [r2, #-1]
- streqb r1, [r2, #3]
- bx lr
-.endm
-
-.macro m_s68k_write32_2M_decode_m1 map_addr @ mode underwrite
- bics r1, r1, #0x000000f0
- bicnes r1, r1, #0x0000f000
- bicnes r1, r1, #0x00f00000
- bicnes r1, r1, #0xf0000000
- bxeq lr
- orr r1, r1, r1, lsr #4
- m_s68k_write32_2M_decode \map_addr
- ldrb r3, [r2, r0]!
- tst r0, #1
- ldrneb r0, [r2, #-1]
- ldreqb r0, [r2, #3]
- and r12,r1, #0x0000000f
- orr r0, r0, r3, lsl #16
- orrne r0, r0, #0x80000000 @ remember addr lsb bit
- tst r0, #0x0000000f
- orreq r0, r0, r12
- tst r0, #0x000000f0
- andeq r12,r1, #0x000000f0
- orreq r0, r0, r12
- tst r0, #0x000f0000
- andeq r12,r1, #0x000f0000
- orreq r0, r0, r12
- tst r0, #0x00f00000
- andeq r12,r1, #0x00f00000
- orreq r0, r0, r12
- tst r0, #0x80000000
- strneb r0, [r2, #-1]
- streqb r0, [r2, #3]
- mov r0, r0, lsr #16
- strb r0, [r2]
- bx lr
-.endm
-
-.macro m_s68k_write32_2M_decode_m2 map_addr @ mode overwrite
- bics r1, r1, #0x000000f0
- bicnes r1, r1, #0x0000f000
- bicnes r1, r1, #0x00f00000
- bicnes r1, r1, #0xf0000000
- bxeq lr
- orr r1, r1, r1, lsr #4
- m_s68k_write32_2M_decode \map_addr
- ldrb r3, [r2, r0]!
- tst r0, #1
- ldrneb r0, [r2, #-1]
- ldreqb r0, [r2, #3]
- orrne r1, r1, #0x80000000 @ remember addr lsb bit
- orr r0, r0, r3, lsl #16
- tst r1, #0x0000000f
- andeq r12,r0, #0x0000000f
- orreq r1, r1, r12
- tst r1, #0x000000f0
- andeq r12,r0, #0x000000f0
- orreq r1, r1, r12
- tst r1, #0x000f0000
- andeq r12,r0, #0x000f0000
- orreq r1, r1, r12
- tst r1, #0x00f00000
- andeq r12,r0, #0x00f00000
- orreq r1, r1, r12
- cmp r0, r1
- bxeq lr
- tst r1, #0x80000000
- strneb r1, [r2, #-1]
- streqb r1, [r2, #3]
- mov r1, r1, lsr #16
- strb r1, [r2]
- bx lr
-.endm
-
-
-
-m_s68k_write32_prg: @ 0x000000 - 0x07ffff
- ldr r2, =(Pico+0x22200)
- bic r0, r0, #1
- ldr r2, [r2]
- add r3, r0, #0x020000 @ map to our address
- add r12,r2, #0x110000
- ldr r12,[r12]
- and r12,r12,#0x00ff0000 @ wp
- cmp r0, r12, lsr #8
- bxlt lr
- mov r0, r1, lsr #16
- strh r0, [r2, r3]!
- strh r1, [r2, #2]
- bx lr
-
-
-m_s68k_write32_wordram_2M: @ 0x080000 - 0x0bffff
-m_s68k_write32_wordram_1M_b1: @ 0x0c0000 - 0x0dffff, maps to 0x0e0000
- m_s68k_write32_ram 0x020000
-
-
-m_s68k_write32_2M_decode_b0_m0: @ 0x080000 - 0x0bffff
- m_s68k_write32_2M_decode_m0 0x080000
-
-m_s68k_write32_2M_decode_b0_m1:
- m_s68k_write32_2M_decode_m1 0x080000
-
-m_s68k_write32_2M_decode_b0_m2:
- m_s68k_write32_2M_decode_m2 0x080000
-
-m_s68k_write32_2M_decode_b1_m0:
- m_s68k_write32_2M_decode_m0 0x0a0000
-
-m_s68k_write32_2M_decode_b1_m1:
- m_s68k_write32_2M_decode_m1 0x0a0000
-
-m_s68k_write32_2M_decode_b1_m2:
- m_s68k_write32_2M_decode_m2 0x0a0000
-
-
-m_s68k_write32_wordram_1M_b0: @ 0x0c0000 - 0x0dffff (same as our offset :)
- m_s68k_write32_ram 0
-
-
-m_s68k_write32_backup:
- add r12,r0, #2
- mov r3, r1
- mov r1, r1, lsr #16
- stmfd sp!,{lr}
- bl m_s68k_write8_backup @ must preserve r3 and r12
- ldmfd sp!,{lr}
- mov r0, r12
- mov r1, r3
- b m_s68k_write8_backup
-
-
-m_s68k_write32_pcm:
- bic r0, r0, #0xff0000
- cmp r0, #0x12
- blt m_s68k_write32_pcm_reg
-
- cmp r0, #0x2000
- bxlt lr
-
-m_s68k_write32_pcm_ram:
- ldr r3, =(Pico+0x22200)
- bic r0, r0, #0x00e000
- ldr r3, [r3]
- mov r0, r0, lsr #1
- add r2, r3, #0x110000
- add r2, r2, #0x002200
- add r2, r2, #0x000040
- ldr r2, [r2]
- add r3, r3, #0x100000 @ pcm_ram
- and r2, r2, #0x0f000000 @ bank
- add r3, r3, r2, lsr #12
- mov r1, r1, ror #16
- strb r1, [r3, r0]!
- mov r1, r1, ror #16
- strb r1, [r3]
- bx lr
-
-m_s68k_write32_pcm_reg:
- mov r0, r0, lsr #1
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl pcm_write
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #1
- b pcm_write
-
-
-m_s68k_write32_regs:
- bic r0, r0, #0xff0000
- bic r0, r0, #0x008000
- bic r0, r0, #1
- tst r0, #0x7e00
- bxne lr
- sub r2, r0, #0x58
- cmp r2, #0x10
- blo m_s68k_write32_regs_gfx
- and r2, r0, #0x1fc
- cmp r2, #0x0c
- beq m_s68k_write32_regs_spec @ hits 0x0f
- and r2, r0, #0x1f0
- cmp r2, #0x20
- beq m_s68k_write32_regs_comm
-
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #24
- bl s68k_reg_write8
- ldr r0, [sp]
- ldr r1, [sp, #4]
- add r0, r0, #1
- mov r1, r1, lsr #16
- bl s68k_reg_write8
- ldr r0, [sp]
- ldr r1, [sp, #4]
- add r0, r0, #2
- mov r1, r1, lsr #8
- bl s68k_reg_write8
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #3
- b s68k_reg_write8
-
-m_s68k_write32_regs_gfx:
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl gfx_cd_write16
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #2
- b gfx_cd_write16
-
-m_s68k_write32_regs_comm: @ Handle the 0x20-0x2f range
- ldr r2, =(Pico+0x22200)
- mov r3, #0xff
- ldr r2, [r2]
- orr r3, r3, r3, lsl #16
- add r2, r2, #0x110000
- and r12,r3, r1, ror #16 @ data is big-endian to be written as little, have to byteswap
- and r1, r3, r1, ror #24
- orr r1, r1, r12,lsl #8 @ end of byteswap
- cmp r0, #0x2e
- strh r1, [r0, r2]!
- movne r1, r1, lsr #16
- strneh r1, [r0, #2]
- bx lr
-
-m_s68k_write32_regs_spec:
- stmfd sp!,{r0,r1,lr}
- mov r1, r1, lsr #16
- bl m_s68k_write16_regs
- ldmfd sp!,{r0,r1,lr}
- add r0, r0, #2
- b m_s68k_write16_regs
-
+.pool
memset(Pico_mcd->pcm_ram, 0, sizeof(Pico_mcd->pcm_ram));
memset(Pico_mcd->bram, 0, sizeof(Pico_mcd->bram));
memcpy(Pico_mcd->bram + sizeof(Pico_mcd->bram) - fmt_size, formatted_bram, fmt_size);
- PicoMemRemapCD(1);
}
PICO_INTERNAL int PicoResetMCD(void)
unsigned long m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];\r
\r
static void xmap_set(unsigned long *map, int shift, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+ const void *func_or_mh, int is_func)\r
{\r
unsigned long addr = (unsigned long)func_or_mh;\r
int mask = (1 << shift) - 1;\r
}\r
\r
void z80_map_set(unsigned long *map, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+ const void *func_or_mh, int is_func)\r
{\r
xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
}\r
\r
void cpu68k_map_set(unsigned long *map, int start_addr, int end_addr,\r
- void *func_or_mh, int is_func)\r
+ const void *func_or_mh, int is_func)\r
{\r
xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);\r
}\r
static int ym2612_write_local(u32 a, u32 d, int is_from_z80);\r
static void z80_mem_setup(void);\r
\r
+#ifdef _ASM_MEMORY_C\r
+u32 PicoRead8_sram(u32 a);\r
+u32 PicoRead16_sram(u32 a);\r
+#endif\r
\r
#ifdef EMU_CORE_DEBUG\r
u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};\r
// -----------------------------------------------------------------\r
// memmap helpers\r
\r
-static int PadRead(int i)\r
+#ifndef _ASM_MEMORY_C\r
+static\r
+#endif\r
+int PadRead(int i)\r
{\r
int pad,value,data_reg;\r
pad=~PicoPadInt[i]; // Get inverse of pad MXYZ SACB RLDU\r
return value; // will mirror later\r
}\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
static u32 io_ports_read(u32 a)\r
{\r
u32 d;\r
Pico.ioports[a] = d;\r
}\r
\r
-static void NOINLINE ctl_write_z80busreq(u32 d)\r
+#endif // _ASM_MEMORY_C\r
+\r
+void NOINLINE ctl_write_z80busreq(u32 d)\r
{\r
d&=1; d^=1;\r
elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);\r
}\r
}\r
\r
-static void NOINLINE ctl_write_z80reset(u32 d)\r
+void NOINLINE ctl_write_z80reset(u32 d)\r
{\r
d&=1; d^=1;\r
elprintf(EL_BUSREQ, "set_zreset: %i->%i [%i] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);\r
\r
// -----------------------------------------------------------------\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
// cart (save) RAM area (usually 0x200000 - ...)\r
static u32 PicoRead8_sram(u32 a)\r
{\r
return m68k_unmapped_read16(a);\r
}\r
\r
+#endif // _ASM_MEMORY_C\r
+\r
static void PicoWrite8_sram(u32 a, u32 d)\r
{\r
if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
SN76496Write(d);\r
return;\r
}\r
-#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)\r
if ((a & 0x7f00) == 0x6000) // Z80 BANK register\r
{\r
Pico.m.z80_bank68k >>= 1;\r
elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);\r
return;\r
}\r
-#endif\r
elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);\r
}\r
\r
PicoWrite8_z80(a, d >> 8);\r
}\r
\r
+#ifndef _ASM_MEMORY_C\r
+\r
// IO/control area (0xa10000 - 0xa1ffff)\r
u32 PicoRead8_io(u32 a)\r
{\r
m68k_unmapped_write16(a, d);\r
}\r
\r
+#endif // _ASM_MEMORY_C\r
+\r
// VDP area (0xc00000 - 0xdfffff)\r
// TODO: verify if lower byte goes to PSG on word writes\r
static u32 PicoRead8_vdp(u32 a)\r
extern unsigned long s68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
void z80_map_set(unsigned long *map, int start_addr, int end_addr,
- void *func_or_mh, int is_func);
+ const void *func_or_mh, int is_func);
void cpu68k_map_set(unsigned long *map, int start_addr, int end_addr,
- void *func_or_mh, int is_func);
+ const void *func_or_mh, int is_func);
void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub);
void m68k_map_unmap(int start_addr, int end_addr);
# memory handlers with banking support for SSF II - The New Challengers
# mostly based on Gens code
+# OUT OF DATE
# (c) Copyright 2007, Grazvydas "notaz" Ignotas
# All Rights Reserved
@ vim:filetype=armasm\r
\r
-@ memory handlers with banking support for SSF II - The New Challengers\r
-@ mostly based on Gens code\r
-\r
-@ (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas\r
+@ (c) Copyright 2006-2009, Grazvydas "notaz" Ignotas\r
@ All Rights Reserved\r
\r
\r
-.include "port_config.s"\r
-\r
-.text\r
-.align 4\r
-\r
-@ default jump tables\r
-\r
-m_read8_def_table:\r
- .long m_read8_rom0 @ 0x000000 - 0x07FFFF\r
- .long m_read8_rom1 @ 0x080000 - 0x0FFFFF\r
- .long m_read8_rom2 @ 0x100000 - 0x17FFFF\r
- .long m_read8_rom3 @ 0x180000 - 0x1FFFFF\r
- .long m_read8_rom4 @ 0x200000 - 0x27FFFF\r
- .long m_read8_rom5 @ 0x280000 - 0x2FFFFF\r
- .long m_read8_rom6 @ 0x300000 - 0x37FFFF\r
- .long m_read8_rom7 @ 0x380000 - 0x3FFFFF\r
- .long m_read8_rom8 @ 0x400000 - 0x47FFFF - for all those large ROM hacks\r
- .long m_read8_rom9 @ 0x480000 - 0x4FFFFF\r
- .long m_read8_romA @ 0x500000 - 0x57FFFF\r
- .long m_read8_romB @ 0x580000 - 0x5FFFFF\r
- .long m_read8_romC @ 0x600000 - 0x67FFFF\r
- .long m_read8_romD @ 0x680000 - 0x6FFFFF\r
- .long m_read8_romE @ 0x700000 - 0x77FFFF\r
- .long m_read8_romF @ 0x780000 - 0x7FFFFF\r
- .long m_read8_rom10 @ 0x800000 - 0x87FFFF\r
- .long m_read8_rom11 @ 0x880000 - 0x8FFFFF\r
- .long m_read8_rom12 @ 0x900000 - 0x97FFFF\r
- .long m_read8_rom13 @ 0x980000 - 0x9FFFFF\r
- .long m_read8_misc @ 0xA00000 - 0xA7FFFF\r
- .long m_read_null @ 0xA80000 - 0xAFFFFF\r
- .long m_read_null @ 0xB00000 - 0xB7FFFF\r
- .long m_read_null @ 0xB80000 - 0xBFFFFF\r
- .long m_read8_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read8_vdp @ 0xC80000 - 0xCFFFFF\r
- .long m_read8_vdp @ 0xD00000 - 0xD7FFFF\r
- .long m_read8_vdp @ 0xD80000 - 0xDFFFFF\r
- .long m_read8_ram @ 0xE00000 - 0xE7FFFF\r
- .long m_read8_ram @ 0xE80000 - 0xEFFFFF\r
- .long m_read8_ram @ 0xF00000 - 0xF7FFFF\r
- .long m_read8_ram @ 0xF80000 - 0xFFFFFF\r
-\r
-m_read16_def_table:\r
- .long m_read16_rom0 @ 0x000000 - 0x07FFFF\r
- .long m_read16_rom1 @ 0x080000 - 0x0FFFFF\r
- .long m_read16_rom2 @ 0x100000 - 0x17FFFF\r
- .long m_read16_rom3 @ 0x180000 - 0x1FFFFF\r
- .long m_read16_rom4 @ 0x200000 - 0x27FFFF\r
- .long m_read16_rom5 @ 0x280000 - 0x2FFFFF\r
- .long m_read16_rom6 @ 0x300000 - 0x37FFFF\r
- .long m_read16_rom7 @ 0x380000 - 0x3FFFFF\r
- .long m_read16_rom8 @ 0x400000 - 0x47FFFF\r
- .long m_read16_rom9 @ 0x480000 - 0x4FFFFF\r
- .long m_read16_romA @ 0x500000 - 0x57FFFF\r
- .long m_read16_romB @ 0x580000 - 0x5FFFFF\r
- .long m_read16_romC @ 0x600000 - 0x67FFFF\r
- .long m_read16_romD @ 0x680000 - 0x6FFFFF\r
- .long m_read16_romE @ 0x700000 - 0x77FFFF\r
- .long m_read16_romF @ 0x780000 - 0x7FFFFF\r
- .long m_read16_rom10 @ 0x800000 - 0x87FFFF\r
- .long m_read16_rom11 @ 0x880000 - 0x8FFFFF\r
- .long m_read16_rom12 @ 0x900000 - 0x97FFFF\r
- .long m_read16_rom13 @ 0x980000 - 0x9FFFFF\r
- .long m_read16_misc @ 0xA00000 - 0xA7FFFF\r
- .long m_read_null @ 0xA80000 - 0xAFFFFF\r
- .long m_read_null @ 0xB00000 - 0xB7FFFF\r
- .long m_read_null @ 0xB80000 - 0xBFFFFF\r
- .long m_read16_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read16_vdp @ 0xC80000 - 0xCFFFFF\r
- .long m_read16_vdp @ 0xD00000 - 0xD7FFFF\r
- .long m_read16_vdp @ 0xD80000 - 0xDFFFFF\r
- .long m_read16_ram @ 0xE00000 - 0xE7FFFF\r
- .long m_read16_ram @ 0xE80000 - 0xEFFFFF\r
- .long m_read16_ram @ 0xF00000 - 0xF7FFFF\r
- .long m_read16_ram @ 0xF80000 - 0xFFFFFF\r
-\r
-m_read32_def_table:\r
- .long m_read32_rom0 @ 0x000000 - 0x07FFFF\r
- .long m_read32_rom1 @ 0x080000 - 0x0FFFFF\r
- .long m_read32_rom2 @ 0x100000 - 0x17FFFF\r
- .long m_read32_rom3 @ 0x180000 - 0x1FFFFF\r
- .long m_read32_rom4 @ 0x200000 - 0x27FFFF\r
- .long m_read32_rom5 @ 0x280000 - 0x2FFFFF\r
- .long m_read32_rom6 @ 0x300000 - 0x37FFFF\r
- .long m_read32_rom7 @ 0x380000 - 0x3FFFFF\r
- .long m_read32_rom8 @ 0x400000 - 0x47FFFF\r
- .long m_read32_rom9 @ 0x480000 - 0x4FFFFF\r
- .long m_read32_romA @ 0x500000 - 0x57FFFF\r
- .long m_read32_romB @ 0x580000 - 0x5FFFFF\r
- .long m_read32_romC @ 0x600000 - 0x67FFFF\r
- .long m_read32_romD @ 0x680000 - 0x6FFFFF\r
- .long m_read32_romE @ 0x700000 - 0x77FFFF\r
- .long m_read32_romF @ 0x780000 - 0x7FFFFF\r
- .long m_read32_rom10 @ 0x800000 - 0x87FFFF\r
- .long m_read32_rom11 @ 0x880000 - 0x8FFFFF\r
- .long m_read32_rom12 @ 0x900000 - 0x97FFFF\r
- .long m_read32_rom13 @ 0x980000 - 0x9FFFFF\r
- .long m_read32_misc @ 0xA00000 - 0xA7FFFF\r
- .long m_read_null @ 0xA80000 - 0xAFFFFF\r
- .long m_read_null @ 0xB00000 - 0xB7FFFF\r
- .long m_read_null @ 0xB80000 - 0xBFFFFF\r
- .long m_read32_vdp @ 0xC00000 - 0xC7FFFF\r
- .long m_read32_vdp @ 0xC80000 - 0xCFFFFF\r
- .long m_read32_vdp @ 0xD00000 - 0xD7FFFF\r
- .long m_read32_vdp @ 0xD80000 - 0xDFFFFF\r
- .long m_read32_ram @ 0xE00000 - 0xE7FFFF\r
- .long m_read32_ram @ 0xE80000 - 0xEFFFFF\r
- .long m_read32_ram @ 0xF00000 - 0xF7FFFF\r
- .long m_read32_ram @ 0xF80000 - 0xFFFFFF\r
-\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-.bss\r
-.align 4\r
-@.section .bss, "brw"\r
-@.data\r
-\r
-@ used tables\r
-m_read8_table:\r
- .skip 32*4\r
-\r
-m_read16_table:\r
- .skip 32*4\r
-\r
-m_read32_table:\r
- .skip 32*4\r
+@@ .include "port_config.s"\r
\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
+.equ SRR_MAPPED, (1 << 0)\r
+.equ SRR_READONLY, (1 << 1)\r
+.equ SRF_EEPROM, (1 << 1)\r
+.equ POPT_6BTN_PAD, (1 << 5)\r
+.equ POPT_DIS_32X, (1 << 20)\r
\r
.text\r
.align 4\r
\r
-.global PicoMemReset\r
-.global PicoRead8\r
-.global PicoRead16\r
-.global PicoRead32\r
-.global PicoWrite8\r
-.global PicoWriteRomHW_SSF2\r
-.global m_m68k_read8_misc\r
-.global m_m68k_write8_misc\r
-\r
-\r
-PicoMemReset:\r
- ldr r12,=(Pico+0x22204)\r
- ldr r12,[r12] @ romsize\r
- add r12,r12,#0x80000\r
- sub r12,r12,#1\r
- mov r12,r12,lsr #19\r
-\r
- ldr r0, =m_read8_table\r
- ldr r1, =m_read8_def_table\r
- mov r2, #32\r
-1:\r
- ldr r3, [r1], #4\r
- str r3, [r0], #4\r
- subs r2, r2, #1\r
- bne 1b\r
-\r
- ldr r0, =m_read16_table\r
- ldr r1, =m_read16_def_table\r
- mov r2, #32\r
-1:\r
- subs r2, r2, #1\r
- ldr r3, [r1], #4\r
- str r3, [r0], #4\r
- bne 1b\r
-\r
- ldr r0, =m_read32_table\r
- ldr r1, =m_read32_def_table\r
- mov r2, #32\r
-1:\r
- subs r2, r2, #1\r
- ldr r3, [r1], #4\r
- str r3, [r0], #4\r
- bne 1b\r
-\r
- @ update memhandlers according to ROM size\r
- ldr r1, =m_read8_above_rom\r
- ldr r0, =m_read8_table\r
- mov r2, #20\r
-1:\r
- sub r2, r2, #1\r
- cmp r2, r12\r
- blt 2f\r
- cmp r2, #4\r
- beq 1b @ do not touch the SRAM area\r
- str r1, [r0, r2, lsl #2]\r
- b 1b\r
-2:\r
- ldr r1, =m_read16_above_rom\r
- ldr r0, =m_read16_table\r
- mov r2, #20\r
-1:\r
- sub r2, r2, #1\r
- cmp r2, r12\r
- blt 2f\r
- cmp r2, #4\r
- beq 1b\r
- str r1, [r0, r2, lsl #2]\r
- b 1b\r
-2:\r
- ldr r1, =m_read32_above_rom\r
- ldr r0, =m_read32_table\r
- mov r2, #20\r
-1:\r
- sub r2, r2, #1\r
- cmp r2, r12\r
- blt 2f\r
- cmp r2, #4\r
- beq 1b\r
- str r1, [r0, r2, lsl #2]\r
- b 1b\r
-2:\r
- bx lr\r
-\r
-.pool\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-PicoRead8: @ u32 a\r
- ldr r2, =m_read8_table\r
- bic r0, r0, #0xff000000\r
- and r1, r0, #0x00f80000\r
- ldr pc, [r2, r1, lsr #17]\r
-\r
-PicoRead16: @ u32 a\r
- ldr r2, =m_read16_table\r
- bic r0, r0, #0xff000000\r
- and r1, r0, #0x00f80000\r
- ldr pc, [r2, r1, lsr #17]\r
-\r
-PicoRead32: @ u32 a\r
- ldr r2, =m_read32_table\r
- bic r0, r0, #0xff000000\r
- and r1, r0, #0x00f80000\r
- ldr pc, [r2, r1, lsr #17]\r
-\r
-.pool\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-m_read_null:\r
- mov r0, #0\r
- bx lr\r
-\r
-\r
-.macro m_read8_rom sect\r
- ldr r1, =(Pico+0x22200)\r
- bic r0, r0, #0xf80000\r
- ldr r1, [r1]\r
-.if \sect\r
- orr r0, r0, #0x080000*\sect\r
-.endif\r
- eor r0, r0, #1\r
- ldrb r0, [r1, r0]\r
- bx lr\r
-.endm\r
-\r
-\r
-m_read8_rom0: @ 0x000000 - 0x07ffff\r
- m_read8_rom 0\r
-\r
-m_read8_rom1: @ 0x080000 - 0x0fffff\r
- m_read8_rom 1\r
-\r
-m_read8_rom2: @ 0x100000 - 0x17ffff\r
- m_read8_rom 2\r
+.global PicoRead8_sram\r
+.global PicoRead8_io\r
+.global PicoRead16_sram\r
+.global PicoRead16_io\r
+.global PicoWrite8_io\r
+.global PicoWrite16_io\r
\r
-m_read8_rom3: @ 0x180000 - 0x1fffff\r
- m_read8_rom 3\r
-\r
-m_read8_rom4: @ 0x200000 - 0x27ffff, SRAM area\r
+PicoRead8_sram: @ u32 a, u32 d\r
ldr r2, =(SRam)\r
ldr r3, =(Pico+0x22200)\r
ldr r1, [r2, #8] @ SRam.end\r
- bic r0, r0, #0xf80000\r
- orr r0, r0, #0x200000\r
cmp r0, r1\r
- bgt m_read8_nosram\r
+ bge m_read8_nosram\r
ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read8_nosram\r
ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
- tst r1, #5\r
- bne SRAMRead\r
+ tst r1, #SRR_MAPPED\r
+ beq m_read8_nosram\r
+ ldr r1, [r2, #0x0c]\r
+ tst r1, #SRF_EEPROM\r
+ bne m_read8_eeprom\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ ldr r2, [r2] @ SRam.data\r
+ sub r0, r0, r1\r
+ add r0, r0, r2\r
+ ldrb r0, [r0]\r
+ bx lr\r
+\r
m_read8_nosram:\r
ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
+ @ XXX: banking unfriendly\r
ldr r1, [r3]\r
eor r0, r0, #1\r
ldrb r0, [r1, r0]\r
bx lr\r
\r
-m_read8_rom5: @ 0x280000 - 0x2fffff\r
- m_read8_rom 5\r
-\r
-m_read8_rom6: @ 0x300000 - 0x37ffff\r
- m_read8_rom 6\r
-\r
-m_read8_rom7: @ 0x380000 - 0x3fffff\r
- m_read8_rom 7\r
-\r
-m_read8_rom8: @ 0x400000 - 0x47ffff\r
- m_read8_rom 8\r
-\r
-m_read8_rom9: @ 0x480000 - 0x4fffff\r
- m_read8_rom 9\r
-\r
-m_read8_romA: @ 0x500000 - 0x57ffff\r
- m_read8_rom 0xA\r
-\r
-m_read8_romB: @ 0x580000 - 0x5fffff\r
- m_read8_rom 0xB\r
-\r
-m_read8_romC: @ 0x600000 - 0x67ffff\r
- m_read8_rom 0xC\r
-\r
-m_read8_romD: @ 0x680000 - 0x6fffff\r
- m_read8_rom 0xD\r
-\r
-m_read8_romE: @ 0x700000 - 0x77ffff\r
- m_read8_rom 0xE\r
-\r
-m_read8_romF: @ 0x780000 - 0x7fffff\r
- m_read8_rom 0xF\r
-\r
-m_read8_rom10: @ 0x800000 - 0x87ffff\r
- m_read8_rom 0x10\r
-\r
-m_read8_rom11: @ 0x880000 - 0x8fffff\r
- m_read8_rom 0x11\r
-\r
-m_read8_rom12: @ 0x900000 - 0x97ffff\r
- m_read8_rom 0x12\r
+m_read8_eeprom:\r
+ stmfd sp!,{r0,lr}\r
+ bl EEPROM_read\r
+ ldmfd sp!,{r0,lr}\r
+ tst r0, #1\r
+ moveq r0, r0, lsr #8\r
+ bx lr\r
\r
-m_read8_rom13: @ 0x980000 - 0x9fffff\r
- m_read8_rom 0x13\r
\r
+PicoRead8_io: @ u32 a, u32 d\r
+ bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
+ cmp r2, #0xa10000 @ so check for it first\r
+ bne m_read8_not_io\r
\r
-m_m68k_read8_misc:\r
-m_read8_misc:\r
- bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
- cmp r2, #0xa10000 @ so check for it first\r
- bne m_read8_misc2\r
m_read8_misc_io:\r
ands r0, r0, #0x1e\r
beq m_read8_misc_hwreg\r
ldrb r0, [r3, #0x0f] @ Pico.m.hardware\r
bx lr\r
\r
-m_read8_misc2:\r
- mov r2, #0xa10000 @ games also like to poll busreq,\r
- orr r2, r2, #0x001100 @ so we'll try it now\r
- cmp r0, r2\r
- beq z80ReadBusReq\r
-\r
- and r2, r0, #0xff0000 @ finally it might be\r
- cmp r2, #0xa00000 @ z80 area\r
- bne m_read8_misc3\r
- tst r0, #0x4000\r
- beq z80Read8 @ z80 RAM\r
- and r2, r0, #0x6000\r
- cmp r2, #0x4000\r
- mvnne r0, #0\r
- bxne lr @ invalid\r
- b ym2612_read_local_68k\r
-\r
-m_read8_fake_ym2612:\r
+m_read8_not_io:\r
+ and r2, r0, #0xfc00\r
+ cmp r2, #0x1000\r
+ bne m_read8_not_brq\r
+\r
ldr r3, =(Pico+0x22200)\r
- ldrb r0, [r3, #8] @ Pico.m.rotate\r
- add r1, r0, #1\r
- strb r1, [r3, #8]\r
- and r0, r0, #3\r
- bx lr\r
+ mov r1, r0\r
+ ldr r0, [r3, #8] @ Pico.m.rotate\r
+ add r0, r0, #1\r
+ strb r0, [r3, #8]\r
+ eor r0, r0, r0, lsl #6\r
\r
-m_read8_misc3:\r
- @ if everything else fails, use generic handler\r
- stmfd sp!,{r0,lr}\r
- bic r0, r0, #1\r
- mov r1, #8\r
- bl OtherRead16\r
- ldmfd sp!,{r1,lr}\r
tst r1, #1\r
- moveq r0, r0, lsr #8\r
- bx lr\r
-\r
-\r
-m_read8_vdp:\r
- tst r0, #0x70000\r
- tsteq r0, #0x000e0\r
- bxne lr @ invalid read\r
- b PicoVideoRead8\r
-\r
-m_read8_ram:\r
- ldr r1, =Pico\r
- bic r0, r0, #0xff0000\r
- eor r0, r0, #1\r
- ldrb r0, [r1, r0]\r
+ bxne lr @ odd addr -> open bus\r
+ bic r0, r0, #1 @ bit0 defined in this area\r
+ and r2, r1, #0xff00\r
+ cmp r2, #0x1100\r
+ bxne lr @ not busreq\r
+\r
+ ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
+ ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ orr r0, r0, r1\r
+ orr r0, r0, r2\r
bx lr\r
\r
-m_read8_above_rom:\r
- @ might still be SRam (Micro Machines, HardBall '95)\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
- cmp r0, r1\r
- bgt m_read8_ar_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
- blt m_read8_ar_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
- tst r1, #5\r
- bne SRAMRead\r
-m_read8_ar_nosram:\r
- ldr r2, =PicoRead16Hook\r
- stmfd sp!,{r0,lr}\r
+m_read8_not_brq:\r
+ ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- bic r0, r0, #1\r
- mov r1, #8\r
- mov lr, pc\r
- bx r2\r
- ldmfd sp!,{r1,lr}\r
- tst r1, #1\r
- moveq r0, r0, lsr #8\r
+ tst r2, #POPT_DIS_32X\r
+ beq PicoRead8_32x\r
+ mov r0, #0\r
bx lr\r
\r
-.pool\r
-\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
-.macro m_read16_rom sect\r
- ldr r1, =(Pico+0x22200)\r
- bic r0, r0, #0xf80000\r
- ldr r1, [r1]\r
- bic r0, r0, #1\r
-.if \sect\r
- orr r0, r0, #0x080000*\sect\r
-.endif\r
- ldrh r0, [r1, r0]\r
- bx lr\r
-.endm\r
-\r
-\r
-m_read16_rom0: @ 0x000000 - 0x07ffff\r
- m_read16_rom 0\r
-\r
-m_read16_rom1: @ 0x080000 - 0x0fffff\r
- m_read16_rom 1\r
-\r
-m_read16_rom2: @ 0x100000 - 0x17ffff\r
- m_read16_rom 2\r
-\r
-m_read16_rom3: @ 0x180000 - 0x1fffff\r
- m_read16_rom 3\r
-\r
-m_read16_rom4: @ 0x200000 - 0x27ffff, SRAM area (NBA Live 95)\r
+PicoRead16_sram: @ u32 a, u32 d\r
ldr r2, =(SRam)\r
ldr r3, =(Pico+0x22200)\r
ldr r1, [r2, #8] @ SRam.end\r
- bic r0, r0, #0xf80000\r
- bic r0, r0, #1\r
- orr r0, r0, #0x200000\r
cmp r0, r1\r
- bgt m_read16_nosram\r
+ bge m_read16_nosram\r
ldr r1, [r2, #4] @ SRam.start\r
cmp r0, r1\r
blt m_read16_nosram\r
ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
- tst r1, #5\r
+ tst r1, #SRR_MAPPED\r
beq m_read16_nosram\r
- stmfd sp!,{lr}\r
- bl SRAMRead16\r
- ldmfd sp!,{pc}\r
+ ldr r1, [r2, #0x0c]\r
+ tst r1, #SRF_EEPROM\r
+ bne EEPROM_read\r
+ ldr r1, [r2, #4] @ SRam.start\r
+ ldr r2, [r2] @ SRam.data\r
+ sub r0, r0, r1\r
+ add r0, r0, r2\r
+ ldrb r1, [r0], #1\r
+ ldrb r0, [r0]\r
+ orr r0, r0, r1, lsl #8\r
+ bx lr\r
+\r
m_read16_nosram:\r
ldr r1, [r3, #4] @ romsize\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
- ldr r1, [r3] @ 1ci\r
+ @ XXX: banking unfriendly\r
+ ldr r1, [r3]\r
ldrh r0, [r1, r0]\r
bx lr\r
\r
-m_read16_rom5: @ 0x280000 - 0x2fffff\r
- m_read16_rom 5\r
-\r
-m_read16_rom6: @ 0x300000 - 0x37ffff\r
- m_read16_rom 6\r
-\r
-m_read16_rom7: @ 0x380000 - 0x3fffff\r
- m_read16_rom 7\r
-\r
-m_read16_rom8: @ 0x400000 - 0x47ffff\r
- m_read16_rom 8\r
-\r
-m_read16_rom9: @ 0x480000 - 0x4fffff\r
- m_read16_rom 9\r
\r
-m_read16_romA: @ 0x500000 - 0x57ffff\r
- m_read16_rom 0xA\r
-\r
-m_read16_romB: @ 0x580000 - 0x5fffff\r
- m_read16_rom 0xB\r
-\r
-m_read16_romC: @ 0x600000 - 0x67ffff\r
- m_read16_rom 0xC\r
-\r
-m_read16_romD: @ 0x680000 - 0x6fffff\r
- m_read16_rom 0xD\r
-\r
-m_read16_romE: @ 0x700000 - 0x77ffff\r
- m_read16_rom 0xE\r
-\r
-m_read16_romF: @ 0x780000 - 0x7fffff\r
- m_read16_rom 0xF\r
-\r
-m_read16_rom10: @ 0x800000 - 0x87ffff\r
- m_read16_rom 0x10\r
-\r
-m_read16_rom11: @ 0x880000 - 0x8fffff\r
- m_read16_rom 0x11\r
-\r
-m_read16_rom12: @ 0x900000 - 0x97ffff\r
- m_read16_rom 0x12\r
-\r
-m_read16_rom13: @ 0x980000 - 0x9fffff\r
- m_read16_rom 0x13\r
-\r
-m_read16_misc:\r
- bic r0, r0, #1\r
- mov r1, #16\r
- b OtherRead16\r
-\r
-m_read16_vdp:\r
- tst r0, #0x70000 @ if ((a&0xe700e0)==0xc00000)\r
- tsteq r0, #0x000e0\r
- bxne lr @ invalid read\r
- bic r0, r0, #1\r
- b PicoVideoRead\r
-\r
-m_read16_ram:\r
- ldr r1, =Pico\r
- bic r0, r0, #0xff0000\r
- bic r0, r0, #1\r
- ldrh r0, [r1, r0]\r
- bx lr\r
-\r
-m_read16_above_rom:\r
- @ might still be SRam\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
- bic r0, r0, #1\r
- cmp r0, r1\r
- bgt m_read16_ar_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
- blt m_read16_ar_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
- tst r1, #5\r
- beq m_read16_ar_nosram\r
+PicoRead16_io: @ u32 a, u32 d\r
+ bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
+ cmp r2, #0xa10000 @ so check for it first\r
+ bne m_read16_not_io\r
stmfd sp!,{lr}\r
- bl SRAMRead16\r
+ bl m_read8_misc_io @ same as read8\r
+ orr r0, r0, r0, lsl #8 @ only has bytes mirrored\r
ldmfd sp!,{pc}\r
-m_read16_ar_nosram:\r
- ldr r2, =PicoRead16Hook\r
- ldr r2, [r2]\r
- mov r1, #16\r
- bx r2\r
-\r
-.pool\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-.macro m_read32_rom sect\r
- ldr r1, =(Pico+0x22200)\r
- bic r0, r0, #0xf80000\r
- ldr r1, [r1]\r
- bic r0, r0, #1\r
-.if \sect\r
- orr r0, r0, #0x080000*\sect\r
-.endif\r
- ldrh r0, [r1, r0]!\r
- ldrh r1, [r1, #2] @ 1ci\r
- orr r0, r1, r0, lsl #16\r
- bx lr\r
-.endm\r
-\r
-\r
-m_read32_rom0: @ 0x000000 - 0x07ffff\r
- m_read32_rom 0\r
-\r
-m_read32_rom1: @ 0x080000 - 0x0fffff\r
- m_read32_rom 1\r
-\r
-m_read32_rom2: @ 0x100000 - 0x17ffff\r
- m_read32_rom 2\r
\r
-m_read32_rom3: @ 0x180000 - 0x1fffff\r
- m_read32_rom 3\r
+m_read16_not_io:\r
+ and r2, r0, #0xfc00\r
+ cmp r2, #0x1000\r
+ bne m_read16_not_brq\r
\r
-m_read32_rom4: @ 0x200000 - 0x27ffff, SRAM area (does any game do long reads?)\r
- ldr r2, =(SRam)\r
ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
- bic r0, r0, #0xf80000\r
- bic r0, r0, #1\r
- orr r0, r0, #0x200000\r
- cmp r0, r1\r
- bgt m_read32_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
- blt m_read32_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
- tst r1, #5\r
- beq m_read32_nosram\r
- stmfd sp!,{r0,lr}\r
- bl SRAMRead16\r
- ldmfd sp!,{r1,lr}\r
- stmfd sp!,{r0,lr}\r
- add r0, r1, #2\r
- bl SRAMRead16\r
- ldmfd sp!,{r1,lr}\r
- orr r0, r0, r1, lsl #16\r
- bx lr\r
-m_read32_nosram:\r
- ldr r1, [r3, #4] @ romsize\r
- cmp r0, r1\r
- movgt r0, #0\r
- bxgt lr @ bad location\r
- ldr r1, [r3] @ (1ci)\r
- ldrh r0, [r1, r0]!\r
- ldrh r1, [r1, #2] @ (2ci)\r
- orr r0, r1, r0, lsl #16\r
+ and r2, r0, #0xff00\r
+ ldr r0, [r3, #8] @ Pico.m.rotate\r
+ add r0, r0, #1\r
+ strb r0, [r3, #8]\r
+ eor r0, r0, r0, lsl #5\r
+ eor r0, r0, r0, lsl #8\r
+ bic r0, r0, #0x100 @ bit8 defined in this area\r
+ cmp r2, #0x1100\r
+ bxne lr @ not busreq\r
+\r
+ ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
+ ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ orr r0, r0, r1, lsl #8\r
+ orr r0, r0, r2, lsl #8\r
bx lr\r
\r
-m_read32_rom5: @ 0x280000 - 0x2fffff\r
- m_read32_rom 5\r
-\r
-m_read32_rom6: @ 0x300000 - 0x37ffff\r
- m_read32_rom 6\r
-\r
-m_read32_rom7: @ 0x380000 - 0x3fffff\r
- m_read32_rom 7\r
-\r
-m_read32_rom8: @ 0x400000 - 0x47ffff\r
- m_read32_rom 8\r
-\r
-m_read32_rom9: @ 0x480000 - 0x4fffff\r
- m_read32_rom 9\r
-\r
-m_read32_romA: @ 0x500000 - 0x57ffff\r
- m_read32_rom 0xA\r
-\r
-m_read32_romB: @ 0x580000 - 0x5fffff\r
- m_read32_rom 0xB\r
-\r
-m_read32_romC: @ 0x600000 - 0x67ffff\r
- m_read32_rom 0xC\r
-\r
-m_read32_romD: @ 0x680000 - 0x6fffff\r
- m_read32_rom 0xD\r
-\r
-m_read32_romE: @ 0x700000 - 0x77ffff\r
- m_read32_rom 0xE\r
-\r
-m_read32_romF: @ 0x780000 - 0x7fffff\r
- m_read32_rom 0xF\r
-\r
-m_read32_rom10: @ 0x800000 - 0x87ffff\r
- m_read32_rom 0x10\r
-\r
-m_read32_rom11: @ 0x880000 - 0x8fffff\r
- m_read32_rom 0x11\r
-\r
-m_read32_rom12: @ 0x900000 - 0x97ffff\r
- m_read32_rom 0x12\r
-\r
-m_read32_rom13: @ 0x980000 - 0x9fffff\r
- m_read32_rom 0x13\r
-\r
-m_read32_misc:\r
- bic r0, r0, #1\r
- stmfd sp!,{r0,lr}\r
- mov r1, #32\r
- bl OtherRead16\r
- mov r1, r0\r
- ldmfd sp!,{r0}\r
- stmfd sp!,{r1}\r
- add r0, r0, #2\r
- mov r1, #32\r
- bl OtherRead16\r
- ldmfd sp!,{r1,lr}\r
- orr r0, r0, r1, lsl #16\r
- bx lr\r
-\r
-m_read32_vdp:\r
- tst r0, #0x70000\r
- tsteq r0, #0x000e0\r
- bxne lr @ invalid read\r
- bic r0, r0, #1\r
- add r1, r0, #2\r
- stmfd sp!,{r1,lr}\r
- bl PicoVideoRead\r
- swp r0, r0, [sp]\r
- bl PicoVideoRead\r
- ldmfd sp!,{r1,lr}\r
- orr r0, r0, r1, lsl #16\r
- bx lr\r
-\r
-m_read32_ram:\r
- ldr r1, =Pico\r
- bic r0, r0, #0xff0000\r
- bic r0, r0, #1\r
- ldrh r0, [r1, r0]!\r
- ldrh r1, [r1, #2] @ 2ci\r
- orr r0, r1, r0, lsl #16\r
- bx lr\r
-\r
-m_read32_above_rom:\r
- ldr r2, =PicoRead16Hook\r
- bic r0, r0, #1\r
+m_read16_not_brq:\r
+ ldr r2, =PicoOpt\r
ldr r2, [r2]\r
- mov r1, #32\r
- stmfd sp!,{r0,r2,lr}\r
- mov lr, pc\r
- bx r2\r
- mov r1, r0\r
- ldmfd sp!,{r0,r2}\r
- stmfd sp!,{r1}\r
- add r0, r0, #2\r
- mov r1, #32\r
- mov lr, pc\r
- bx r2\r
- ldmfd sp!,{r1,lr}\r
- orr r0, r0, r1, lsl #16\r
- bx lr\r
-\r
-.pool\r
-\r
-@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
-\r
-PicoWriteRomHW_SSF2: @ u32 a, u32 d\r
- and r0, r0, #0xe\r
- movs r0, r0, lsr #1\r
- bne pwr_banking\r
-\r
- @ sram register\r
- ldr r2, =(Pico+0x22211) @ Pico.m.sram_reg\r
- ldrb r0, [r2]\r
- and r1, r1, #3\r
- bic r0, r0, #3\r
- orr r0, r0, r1\r
- strb r0, [r2]\r
- bx lr\r
-\r
-pwr_banking:\r
- and r1, r1, #0x1f\r
-\r
- ldr r3, =m_read8_def_table\r
- ldr r2, =m_read8_table\r
- ldr r12, [r3, r1, lsl #2]\r
- str r12, [r2, r0, lsl #2]\r
-\r
- ldr r3, =m_read16_def_table\r
- ldr r2, =m_read16_table\r
- ldr r12, [r3, r1, lsl #2]\r
- str r12, [r2, r0, lsl #2]\r
-\r
- ldr r3, =m_read32_def_table\r
- ldr r2, =m_read32_table\r
- ldr r12, [r3, r1, lsl #2]\r
- str r12, [r2, r0, lsl #2]\r
- \r
+ tst r2, #POPT_DIS_32X\r
+ beq PicoRead16_32x\r
+ mov r0, #0\r
bx lr\r
\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
-@ Here we only handle most often used locations,\r
-@ everything else is passed to generic handlers\r
+PicoWrite8_io: @ u32 a, u32 d\r
+ bic r2, r0, #0x1e @ most commonly we get i/o port write,\r
+ eor r2, r2, #0xa10000 @ so check for it first\r
+ eors r2, r2, #1\r
+ bne m_write8_not_io\r
\r
-PicoWrite8: @ u32 a, u8 d\r
- bic r0, r0, #0xff000000\r
- and r2, r0, #0x00e00000\r
- cmp r2, #0x00e00000 @ RAM?\r
- ldr r3, =Pico\r
- biceq r0, r0, #0x00ff0000\r
- eoreq r0, r0, #1\r
- streqb r1, [r3, r0]\r
- bxeq lr\r
-\r
-m_m68k_write8_misc:\r
- bic r2, r0, #0x1f @ most commonly we get i/o port write,\r
- cmp r2, #0xa10000 @ so check for it first\r
- bne m_write8_misc2\r
m_write8_io:\r
ldr r2, =PicoOpt\r
and r0, r0, #0x1e\r
ldr r2, [r2]\r
ldr r3, =(Pico+0x22000) @ Pico.ioports\r
- tst r2, #0x20 @ 6 button pad?\r
- streqb r1, [r3, r0, lsr #1]\r
- bxeq lr\r
+ tst r2, #POPT_6BTN_PAD\r
+ beq m_write8_io_done\r
cmp r0, #2\r
cmpne r0, #4\r
bne m_write8_io_done @ not likely to happen\r
strb r1, [r3, r0, lsr #1]\r
bx lr\r
\r
-\r
-m_write8_misc2:\r
- and r2, r0, #0xff0000\r
- cmp r2, #0xa00000 @ z80 area?\r
- bne m_write8_not_z80\r
- tst r0, #0x4000\r
- bne m_write8_z80_not_ram\r
- ldr r3, =(Pico+0x20000) @ Pico.zram\r
- add r2, r3, #0x02200 @ Pico+0x22200\r
- ldrb r2, [r2, #9] @ Pico.m.z80Run\r
- bic r0, r0, #0xff0000\r
- bic r0, r0, #0x00e000\r
- tst r2, #1\r
- ldr r2, =SekCycleCnt\r
- streqb r1, [r3, r0] @ zram\r
- ldr r0, [r2]\r
- add r0, r0, #2 @ hack?\r
- str r0, [r2]\r
+m_write8_not_io:\r
+ tst r0, #1\r
+ bne m_write8_not_z80ctl @ even addrs only\r
+ and r2, r0, #0xff00\r
+ cmp r2, #0x1100\r
+ moveq r0, r1\r
+ beq ctl_write_z80busreq\r
+ cmp r2, #0x1200\r
+ moveq r0, r1\r
+ beq ctl_write_z80reset\r
+\r
+m_write8_not_z80ctl:\r
+ @ unlikely\r
+ eor r2, r0, #0xa10000\r
+ eor r2, r2, #0x003000\r
+ eors r2, r2, #0x0000f1\r
+ bne m_write8_not_sreg\r
+ ldr r3, =(Pico+0x22200)\r
+ ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
+ bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
+ orr r2, r2, r1\r
+ strb r2, [r3, #(8+9)]\r
bx lr\r
\r
-m_write8_z80_not_ram:\r
- and r2, r0, #0x6000\r
- cmp r2, #0x4000\r
- bne m_write8_z80_not_ym2612\r
- ldr r3, =PicoOpt\r
- and r0, r0, #3\r
- ldr r3, [r3]\r
- mov r2, #0 @ is_from_z80 = 0\r
- tst r3, #1\r
- bxeq lr\r
- stmfd sp!,{lr}\r
- and r1, r1, #0xff\r
- bl ym2612_write_local\r
- ldr r2, =emustatus\r
- ldmfd sp!,{lr}\r
- ldr r1, [r2]\r
- and r0, r0, #1\r
- orr r1, r0, r1\r
- str r1, [r2] @ emustatus|=ym2612_write_local(a&3, d);\r
+m_write8_not_sreg:\r
+ ldr r2, =PicoOpt\r
+ ldr r2, [r2]\r
+ tst r2, #POPT_DIS_32X\r
+ beq PicoWrite8_32x\r
bx lr\r
\r
-m_write8_z80_not_ym2612: @ not too likely\r
- mov r2, r0, lsl #17\r
- bic r2, r2, #6<<17\r
- mov r3, #0x7f00\r
- orr r3, r3, #0x0011\r
- cmp r3, r2, lsr #17 @ psg @ z80 area?\r
- beq m_write8_psg\r
- and r2, r0, #0x7f00\r
- cmp r2, #0x6000 @ bank register?\r
- bxne lr @ invalid write\r
-\r
-m_write8_z80_bank_reg:\r
- ldr r3, =(Pico+0x22208) @ Pico.m\r
- ldrh r2, [r3, #0x0a]\r
- mov r1, r1, lsl #8\r
- orr r2, r1, r2, lsr #1\r
- bic r2, r2, #0xfe00\r
- strh r2, [r3, #0x0a]\r
- bx lr\r
+@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
+PicoWrite16_io: @ u32 a, u32 d\r
+ bic r2, r0, #0x1f @ most commonly we get i/o port write,\r
+ cmp r2, #0xa10000 @ so check for it first\r
+ beq m_write8_io\r
+\r
+m_write16_not_io:\r
+ and r2, r0, #0xff00\r
+ cmp r2, #0x1100\r
+ moveq r0, r1, lsr #8\r
+ beq ctl_write_z80busreq\r
+ cmp r2, #0x1200\r
+ moveq r0, r1, lsr #8\r
+ beq ctl_write_z80reset\r
+\r
+m_write16_not_z80ctl:\r
+ @ unlikely\r
+ eor r2, r0, #0xa10000\r
+ eor r2, r2, #0x003000\r
+ eors r2, r2, #0x0000f0\r
+ bne m_write16_not_sreg\r
+ ldr r3, =(Pico+0x22200)\r
+ ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
+ bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
+ orr r2, r2, r1\r
+ strb r2, [r3, #(8+9)]\r
+ bx lr\r
\r
-m_write8_not_z80:\r
- and r2, r0, #0xe70000\r
- cmp r2, #0xc00000 @ VDP area?\r
- bne OtherWrite8 @ passthrough\r
- and r2, r0, #0xf9\r
- cmp r2, #0x11\r
- bne OtherWrite8\r
-m_write8_psg:\r
+m_write16_not_sreg:\r
ldr r2, =PicoOpt\r
- and r0, r1, #0xff\r
ldr r2, [r2]\r
- tst r2, #2\r
- bxeq lr\r
- b SN76496Write\r
+ tst r2, #POPT_DIS_32X\r
+ beq PicoWrite16_32x\r
+ bx lr\r
+\r
+.pool\r
\r
unsigned short z80_bank68k; // 0a\r
unsigned short pad0;\r
unsigned char pad1;\r
- unsigned char z80_reset; // z80 reset held\r
+ unsigned char z80_reset; // 0f z80 reset held\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
unsigned short eeprom_addr; // EEPROM address register\r
unsigned char eeprom_cycle; // EEPROM cycle number\r
\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
-PICO_INTERNAL_ASM void PicoMemRemapCD(int r3);\r
-PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
+void PicoMemStateLoaded(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
# settings\r
#mz80 = 1\r
#debug_cyclone = 1\r
-#asm_memory = 1 # TODO\r
+asm_memory = 1\r
asm_render = 1\r
asm_ym2612 = 1\r
asm_misc = 1\r
asm_cdpico = 1\r
-#asm_cdmemory = 1 # TODO\r
+asm_cdmemory = 1\r
amalgamate = 0\r
#profile = 1\r
#use_musashi = 1\r
notaz.gp2x.de / picodrive.git / commitdiff