.text
.globl main
+.globl VBL
##################################################
# #
.endm
+# convert tile coords in d0, d1 to nametable addr to a0
+.macro XY2NT
+ lsl.w #6,d1
+ add.w d1,d0
+ lsl.w #1,d0
+ movea.l #0xe000,a0
+ add.w d0,a0
+.endm
+
#################################################
# #
# DATA #
.align 2
main:
+ /* mask irqs durinf init */
+ move.w #0x2700,sr
+
+ movea.l #0,a6
+
+ /* Init pads */
+ move.b #0x40,(0xa10009).l
+ move.b #0x40,(0xa10003).l
+
/* Initialize VDP */
jsr init_gfx
jsr load_tiles
/* generate A layer map */
- movea.l #0xe000,a6
+ movea.l #0xe000,a1
move.l #28-1,d4
lmaploop0:
- movea.l a6,a0
+ movea.l a1,a0
jsr load_prepare
move.l #64/2-1,d3
0: move.l #0x00000000,(a0)
dbra d3,0b
- add.l #64*2,a6
+ add.l #64*2,a1
dbra d4,lmaploop0
/* generate B layer map */
0: move.l (a1)+,(a0)
dbra d3,0b
- jsr wait_vsync
-
- movea.l #hello,a0
- moveq.l #1,d0
- moveq.l #1,d1
- jsr print
+ move.w #0x2000,sr
##################################################
# #
# #
##################################################
+# global regs:
+# a6 - page[31:8],cursor_offs[7:0]
+
forever:
+VBL:
+ addq.l #1,(vtimer).l
+ movem.l d0-d7/a0-a5,-(a7)
+
+ /* draw main stuff */
+ clr.l d7
+ move.l a6,d0
+ lsr.l #8,d0
+ move.l d0,a1 /* current addr */
+
+ movea.l #0xe004,a2
+ move.l #27-1,d5
+
+draw_column:
+ move.l a2,a0
+ jsr load_prepare
+
+ /* addr */
+ move.l a1,d2
+ moveq.l #6,d3
+ jsr print_hex_preped
+
+ /* 4 shorts */
+ moveq.l #4-1,d4
+draw_shorts:
+ move.w #' ',(a0)
+ move.w (a1)+,d2
+ moveq.l #4,d3
+ jsr print_hex_preped
+ dbra d4,draw_shorts
+
+ move.w #' ',(a0)
+ move.w #' ',(a0)
+
+ /* 8 chars */
+ subq.l #8,a1
+ moveq.l #8-1,d4
+draw_chars:
+ move.b (a1)+,d0
+ move.b d0,d1
+ sub.b #0x20,d1
+ cmp.b #0x60,d1
+ blo 0f
+ move.w #'.',d0
+0:
+ move.w d0,(a0)
+ dbra d4,draw_chars
+
+ add.w #0x80,a2
+ dbra d5,draw_column
+
+ /* handle input */
+ jsr get_input /* x0cbrldu x1sa00du */
+ btst.b #0,d0
+ beq _in_nup
+ sub.l #0x0800,a6
+
+_in_nup:
+ btst.b #1,d0
+ beq _in_ndn
+ add.l #0x0800,a6
+
+_in_ndn:
+ btst.l #10,d0
+ beq _in_nleft
+ sub.l #0xd800,a6
+
+_in_nleft:
+ btst.b #11,d0
+ beq _in_nright
+ add.l #0xd800,a6
+
+_in_nright:
+
+end:
+ movem.l (a7)+,d0-d7/a0-a5
+ rte
+
+
#################################################
# #
# Initialize VDP registers #
rts
+# read single phase from controller
+# a0 - addr
+# d0 - result
+get_input:
+ move.b #0x40,(0xa10003)
+ nop
+ nop
+ nop
+ move.b (0xa10003),d0
+ move.b #0x00,(0xa10003)
+ lsl.w #8,d0
+ nop
+ move.b (0xa10003),d0
+ eor.w #0xffff,d0
+# move.b #0x40,(0xa10003)
+ rts
+
# Load tile data from ROM
# a0: VRAM base
# a1: pattern address
print:
move.l a0,a1
- lsl.w #6,d1
- add.w d1,d0
- lsl.w #1,d0
- movea.l #0xe000,a0
- add.w d0,a0
+ XY2NT
jsr load_prepare
moveq.l #0,d0
rts
+# print_hex
+# d0 - x
+# d1 - y
+# d2 - value
+# d3 - digit cnt
+# destroys a0
+
+print_hex:
+ XY2NT
+ jsr load_prepare
+
+print_hex_preped:
+ move.l d3,d0
+ lsl.b #2,d0
+ ror.l d0,d2 /* prep value */
+ moveq.l #0,d0
+ subq.l #1,d3 /* count */
+
+_print_hex_loop:
+ rol.l #4,d2
+ move.b d2,d0
+ and.b #0xf,d0
+ cmp.b #0xa,d0
+ bge 1f
+
+ add.b #'0',d0
+ jmp 2f
+1:
+ add.b #0x37,d0
+2:
+ move.w d0,(a0)
+ dbra d3,_print_hex_loop
+
+ rts
+
+
#################################################
# #
# Wait for next VBlank interrupt #