extern const unsigned char hcounts_32[];\r
extern const unsigned char hcounts_40[];\r
\r
+static unsigned hvlatch; // latched hvcounter value\r
+static int blankline; // display disabled for this line\r
\r
int (*PicoDmaHook)(unsigned int source, int len, unsigned short **base, unsigned int *mask) = NULL;\r
\r
+\r
+/* VDP FIFO implementation\r
+ * \r
+ * fifo_slot: last slot executed in this scanline\r
+ * fifo_cnt: #slots remaining for active FIFO write (#writes<<#bytep)\r
+ * fifo_total: #total FIFO entries pending\r
+ * fifo_data: last values transferred through fifo\r
+ * fifo_queue: fifo transfer queue (#writes, VRAM_byte_p)\r
+ *\r
+ * FIFO states: empty total=0\r
+ * inuse total>0 && total<4\r
+ * full total==4\r
+ * wait total>4\r
+ * Conditions:\r
+ * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles\r
+ * implies blocking the 68k up to that slot.\r
+ *\r
+ * A FIFO write goes to the end of the fifo queue. There can be more pending\r
+ * writes than FIFO slots, but the 68k will be blocked in most of those cases.\r
+ * This is only about correct timing, data xfer must be handled by the caller.\r
+ * Blocking the CPU means burning cycles via SekCyclesBurn*(), which is to be\r
+ * executed by the caller.\r
+ *\r
+ * FIFOSync "executes" FIFO write slots up to the given cycle in the current\r
+ * scanline. A queue entry completely executed is removed from the queue.\r
+ * FIFOWrite pushes writes to the transfer queue. If it's a blocking write, 68k\r
+ * is blocked if more than 4 FIFO writes are pending.\r
+ * FIFORead executes a 68k read. 68k is blocked until the next transfer slot.\r
+ */\r
+\r
+// FIFO transfer slots per line: H32 blank, H40 blank, H32 active, H40 active\r
+static const short vdpslots[] = { 166, 204, 16, 18 };\r
+// mapping between slot# and 68k cycles in a blanked scanline\r
+static const int vdpcyc2sl_bl[] = { (166<<16)/488, (204<<16)/488, (16<<16)/488, (18<<16)/488 };\r
+static const int vdpsl2cyc_bl[] = { (488<<16)/166, (488<<16)/204, (488<<16)/16, (488<<16)/18 };\r
+\r
+// VDP transfer slots in active display 32col mode. 1 slot is 488/171 = 2.8538\r
+// 68k cycles. Only 16 of the 171 slots in a scanline can be used by CPU/DMA:\r
+// (HINT=slot 0): 13,27,42,50,58,74,82,90,106,114,122,138,146,154,169,170\r
+const unsigned char vdpcyc2sl_32[] = { // 68k cycles/4 since HINT to slot #\r
+// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,\r
+ 3, 3, 3, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5,\r
+ 5, 5, 5, 5, 6, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7,\r
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 9, 9, 9, 9, 9,\r
+ 9,10,10,10,10,10,10,11,11,11,11,11,11,11,11,11,\r
+11,11,12,12,12,12,12,12,13,13,13,13,13,13,14,14,\r
+14,14,14,14,14,14,14,14,15,16,16,16,16,16,16,16,\r
+};\r
+const unsigned char vdpsl2cyc_32[] = { // slot # to 68k cycles/4 since HINT\r
+ 0, 9, 19, 30, 35, 41, 52, 58, 64, 75, 81, 87, 98,104,110,120,121,123,123\r
+};\r
+\r
+// VDP transfer slots in active display 40col mode. 1 slot is 488/210 = 2.3238\r
+// 68k cycles. Only 18 of the 210 slots in a scanline can be used by CPU/DMA:\r
+// (HINT=0): 23,49,57,65,81,89,97,113,121,129,145,153,161,177,185,193,208,209\r
+const unsigned char vdpcyc2sl_40[] = { // 68k cycles/4 since HINT to slot #\r
+// 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,\r
+ 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5,\r
+ 5, 5, 5, 6, 6, 6, 6, 6, 7, 7, 7, 7, 7, 7, 7, 7,\r
+ 7, 8, 8, 8, 8, 8, 9, 9, 9, 9,10,10,10,10,10,10,\r
+10,10,10,10,11,11,11,11,12,12,12,12,12,13,13,13,\r
+13,13,13,13,13,13,14,14,14,14,14,15,15,15,15,15,\r
+16,16,16,16,16,16,16,16,17,18,18,18,18,18,18,18,\r
+};\r
+const unsigned char vdpsl2cyc_40[] = { // slot # to 68k cycles/4 since HINT\r
+ 0, 13, 28, 33, 37, 47, 51, 56, 65, 70, 74, 84, 88, 93,102,107,112,120,121,123,123\r
+};\r
+\r
+// NB code assumes fifo_* arrays have size 2^n\r
+// last transferred FIFO data, ...x = index XXX currently only CPU\r
+static short fifo_data[4], fifo_dx;\r
+// queued FIFO transfers, ...x = index, ...l = queue length\r
+// each entry has 2 values: [n]>>1=#writes, [n]&1=is VRAM byte access\r
+static int fifo_queue[8], fifo_qx, fifo_ql;\r
+\r
+signed int fifo_cnt; // pending slots for current queue entry\r
+unsigned short fifo_slot; // last executed slot in current scanline\r
+unsigned int fifo_total; // total# of pending FIFO entries\r
+\r
+// sync FIFO to cycles\r
+void PicoVideoFIFOSync(int cycles)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+ int h40 = pv->reg[12] & 1;\r
+ const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
+ int slots, done;\r
+\r
+ // calculate #slots since last executed slot\r
+ if (active) slots = cs[cycles/4];\r
+ else slots = (cycles * vdpcyc2sl_bl[h40] + cycles) >> 16;\r
+ slots -= fifo_slot;\r
+\r
+ // advance FIFO queue by #done slots\r
+ done = slots;\r
+ while (done > 0 && fifo_ql) {\r
+ int l = done, b = fifo_queue[fifo_qx&7] & 1;\r
+ if (l > fifo_cnt)\r
+ l = fifo_cnt;\r
+ fifo_total -= ((fifo_cnt & b) + l) >> b;\r
+ fifo_slot += l;\r
+ fifo_cnt -= l;\r
+ done -= l;\r
+\r
+ if (fifo_cnt == 0) {\r
+ fifo_qx ++, fifo_ql --;\r
+ fifo_cnt= (fifo_queue[fifo_qx&7] >> 1) << (fifo_queue[fifo_qx&7] & 1);\r
+ }\r
+ }\r
+\r
+ // release CPU and terminate DMA if FIFO isn't blocking the 68k anymore\r
+ if (fifo_total <= 4) {\r
+ pv->status &= ~PVS_CPUWR;\r
+ pv->command &= ~0x80;\r
+ if (!(pv->status & PVS_DMAPEND))\r
+ pv->status &= ~(SR_DMA|PVS_DMAFILL);\r
+ }\r
+ if (fifo_total == 0)\r
+ pv->status &= ~PVS_CPURD;\r
+}\r
+\r
+// drain FIFO, blocking 68k on the way. FIFO must be synced prior to drain.\r
+int PicoVideoFIFODrain(int level, int cycles)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+ int h40 = pv->reg[12] & 1;\r
+ const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;\r
+ int maxsl = vdpslots[h40 + 2*active]; // max xfer slots in this scanline\r
+ int burn = 0;\r
+\r
+ while (fifo_total > level && fifo_slot < maxsl) {\r
+ int b = fifo_queue[fifo_qx&7] & 1;\r
+ int cnt = (fifo_total-level) << b;\r
+ int last = fifo_slot;\r
+ int slot = (fifo_cnt<cnt?fifo_cnt:cnt) + last; // target slot\r
+ unsigned ocyc = cycles;\r
+\r
+ if (slot > maxsl) {\r
+ // target in later scanline, advance to eol\r
+ slot = maxsl;\r
+ fifo_slot = maxsl;\r
+ cycles = 488;\r
+ } else {\r
+ // advance FIFO to target slot and CPU to cycles at that slot\r
+ fifo_slot = slot;\r
+ if (active) cycles = sc[slot]*4;\r
+ else cycles = ((slot * vdpsl2cyc_bl[h40] + slot) >> 16);\r
+ }\r
+ burn += cycles - ocyc;\r
+\r
+ slot -= last;\r
+ fifo_total -= ((fifo_cnt & b) + slot) >> b;\r
+ fifo_cnt -= slot;\r
+\r
+ if (fifo_cnt == 0) {\r
+ fifo_qx ++, fifo_ql --;\r
+ fifo_cnt= (fifo_queue[fifo_qx&7] >> 1) << (fifo_queue[fifo_qx&7] & 1);\r
+ }\r
+ }\r
+\r
+ // release CPU and terminate DMA if FIFO isn't blocking the bus anymore\r
+ if (fifo_total <= 4) {\r
+ pv->status &= ~PVS_CPUWR;\r
+ pv->command &= ~0x80;\r
+ if (!(pv->status & PVS_DMAPEND))\r
+ pv->status &= ~(SR_DMA|PVS_DMAFILL);\r
+ }\r
+ if (fifo_total == 0)\r
+ pv->status &= ~PVS_CPURD;\r
+\r
+ return burn;\r
+}\r
+\r
+// read VDP data port\r
+int PicoVideoFIFORead(void)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+ int h40 = pv->reg[12] & 1;\r
+ const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
+ const unsigned char *sc = h40 ? vdpsl2cyc_40 : vdpsl2cyc_32;\r
+ int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;\r
+ int burn = 0;\r
+\r
+ PicoVideoFIFOSync(lc);\r
+\r
+ // advance FIFO and CPU until FIFO is empty\r
+ burn = PicoVideoFIFODrain(0, lc);\r
+ lc += burn;\r
+ if (fifo_total > 0)\r
+ pv->status |= PVS_CPURD; // target slot is in later scanline\r
+ else {\r
+ // use next VDP access slot for reading, block 68k until then\r
+ if (active) {\r
+ fifo_slot = cs[lc/4] + 1;\r
+ burn += sc[fifo_slot]*4;\r
+ } else {\r
+ fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16) + 1;\r
+ burn += ((fifo_slot * vdpsl2cyc_bl[h40] + fifo_slot) >> 16);\r
+ }\r
+ burn -= lc;\r
+ }\r
+\r
+ return burn;\r
+}\r
+ \r
+// write VDP data port\r
+int PicoVideoFIFOWrite(int count, int byte_p, unsigned sr_mask,unsigned sr_flags)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ int active = !(pv->status & SR_VB) && (pv->reg[1] & 0x40);\r
+ int h40 = pv->reg[12] & 1;\r
+ const unsigned char *cs = h40 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
+ int lc = SekCyclesDone()-Pico.t.m68c_line_start+4;\r
+ int burn = 0;\r
+\r
+ PicoVideoFIFOSync(lc);\r
+ pv->status = (pv->status & ~sr_mask) | sr_flags;\r
+\r
+ if (count) {\r
+ // update FIFO state if it was empty\r
+ if (fifo_total == 0 && count) {\r
+ if (active) fifo_slot = cs[lc/4];\r
+ else fifo_slot = (lc * vdpcyc2sl_bl[h40] + lc) >> 16;\r
+ fifo_cnt = count << byte_p;\r
+ }\r
+\r
+ // create xfer queue entry\r
+ int x = (fifo_qx + fifo_ql) & 7;\r
+ fifo_queue[x] = (count << 1) | byte_p;\r
+ fifo_ql ++;\r
+ fifo_total += count;\r
+ }\r
+\r
+ // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
+ if ((pv->status & (PVS_CPUWR|PVS_DMAFILL)) == PVS_CPUWR)\r
+ burn = PicoVideoFIFODrain(4, lc);\r
+\r
+ return burn;\r
+}\r
+\r
+// at HINT, advance FIFO to new scanline\r
+int PicoVideoFIFOHint(void)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ int burn = 0;\r
+\r
+ // reset slot to start of scanline\r
+ fifo_slot = 0;\r
+ \r
+ // if CPU is waiting for the bus, advance CPU and FIFO until bus is free\r
+ if (pv->status & PVS_CPURD)\r
+ burn = PicoVideoFIFORead();\r
+ if (pv->status & PVS_CPUWR)\r
+ burn = PicoVideoFIFOWrite(0, 0, 0, 0);\r
+\r
+ return burn;\r
+}\r
+\r
+// switch FIFO mode between active/inactive display\r
+void PicoVideoFIFOMode(int active)\r
+{\r
+ struct PicoVideo *pv = &Pico.video;\r
+ const unsigned char *cs = pv->reg[12]&1 ? vdpcyc2sl_40 : vdpcyc2sl_32;\r
+ int h40 = pv->reg[12] & 1;\r
+ int lc = SekCyclesDone() - Pico.t.m68c_line_start;\r
+\r
+ PicoVideoFIFOSync(lc);\r
+\r
+ if (fifo_total) {\r
+ // recalculate FIFO slot for new mode\r
+ if (!(pv->status & SR_VB) && active)\r
+ fifo_slot = cs[lc/4];\r
+ else fifo_slot = ((lc * vdpcyc2sl_bl[h40] + lc) >> 16);\r
+ }\r
+}\r
+\r
+\r
+// VDP memory rd/wr\r
+\r
static __inline void AutoIncrement(void)\r
{\r
Pico.video.addr=(unsigned short)(Pico.video.addr+Pico.video.reg[0xf]);\r
\r
static unsigned int VideoRead(void)\r
{\r
- unsigned int a=0,d=0;\r
+ unsigned int a, d = fifo_data[(fifo_dx+1)&3];\r
\r
a=Pico.video.addr; a>>=1;\r
\r
+ SekCyclesBurnRun(PicoVideoFIFORead());\r
switch (Pico.video.type)\r
{\r
case 0: d=PicoMem.vram [a & 0x7fff]; break;\r
- case 8: d=PicoMem.cram [a & 0x003f]; break;\r
- case 4: d=PicoMem.vsram[a & 0x003f]; break;\r
+ case 8: d=(PicoMem.cram [a & 0x003f] & 0x0eee) | (d & ~0x0eee); break;\r
+ case 4: if ((a & 0x3f) >= 0x28) a = 0;\r
+ d=(PicoMem.vsram [a & 0x003f] & 0x07ff) | (d & ~0x07ff); break;\r
+ case 12:a=PicoMem.vram [a & 0x7fff]; if (Pico.video.addr&1) a >>= 8;\r
+ d=(a & 0x00ff) | (d & ~0x00ff); break;\r
default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;\r
}\r
\r
return d;\r
}\r
\r
+// VDP DMA\r
+\r
static int GetDmaLength(void)\r
{\r
struct PicoVideo *pvid=&Pico.video;\r
u32 mask = 0x1ffff;\r
\r
elprintf(EL_VDPDMA, "DmaSlow[%i] %06x->%04x len %i inc=%i blank %i [%u] @ %06x",\r
- Pico.video.type, source, a, len, inc, (Pico.video.status&8)||!(Pico.video.reg[1]&0x40),\r
+ Pico.video.type, source, a, len, inc, (Pico.video.status&SR_VB)||!(Pico.video.reg[1]&0x40),\r
SekCyclesDone(), SekPc);\r
\r
- Pico.m.dma_xfers = len;\r
- if (Pico.m.dma_xfers < len) // lame 16bit var\r
- Pico.m.dma_xfers = ~0;\r
- SekCyclesBurnRun(CheckDMA(488 - (SekCyclesDone()-Pico.t.m68c_line_start)));\r
+ SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_DMAPEND,\r
+ SR_DMA | PVS_CPUWR) + 8);\r
\r
if ((source & 0xe00000) == 0xe00000) { // Ram\r
base = (u16 *)PicoMem.ram;\r
int source;\r
elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());\r
\r
- Pico.m.dma_xfers = len;\r
- if (Pico.m.dma_xfers < len)\r
- Pico.m.dma_xfers = ~0;\r
- Pico.video.status |= SR_DMA;\r
+ SekCyclesBurnRun(PicoVideoFIFOWrite(len, 1, PVS_CPUWR|PVS_DMAPEND, SR_DMA));\r
\r
source =Pico.video.reg[0x15];\r
source|=Pico.video.reg[0x16]<<8;\r
\r
+ // XXX implement VRAM 128k? Is this even working?\r
for (; len; len--)\r
{\r
vr[a] = vr[source++ & 0xffff];\r
len = GetDmaLength();\r
elprintf(EL_VDPDMA, "DmaFill len %i inc %i [%u]", len, inc, SekCyclesDone());\r
\r
- Pico.m.dma_xfers = len;\r
- if (Pico.m.dma_xfers < len) // lame 16bit var\r
- Pico.m.dma_xfers = ~0;\r
- Pico.video.status |= SR_DMA;\r
+ SekCyclesBurnRun(PicoVideoFIFOWrite(len, Pico.video.type == 1, PVS_CPUWR|PVS_DMAPEND, SR_DMA));\r
\r
switch (Pico.video.type)\r
{\r
Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
break;\r
case 3: // cram\r
+ Pico.m.dirtyPal = 1;\r
+ for (l = len; l; l--) {\r
+ PicoMem.cram[(a/2) & 0x3f] = data;\r
+\r
+ // Increment address register\r
+ a += inc;\r
+ }\r
+ break;\r
case 5: { // vsram\r
- // TODO: needs fifo; anyone using these?\r
- static int once;\r
- if (!once++)\r
- elprintf(EL_STATUS|EL_ANOMALY|EL_VDPDMA, "TODO: cram/vsram fill");\r
+ for (l = len; l; l--) {\r
+ PicoMem.vsram[(a/2) & 0x3f] = data;\r
+\r
+ // Increment address register\r
+ a += inc;\r
+ }\r
+ break;\r
}\r
- case 0x81:\r
+ case 0x81: // vram 128k\r
for (l = len; l; l--) {\r
VideoWrite128(a, data);\r
\r
\r
}\r
\r
+// VDP command handling\r
+\r
static NOINLINE void CommandDma(void)\r
{\r
struct PicoVideo *pvid=&Pico.video;\r
u32 len, method;\r
u32 source;\r
\r
- if ((pvid->reg[1]&0x10)==0) return; // DMA not enabled\r
-\r
- if (Pico.m.dma_xfers)\r
+ pvid->status |= PVS_DMAPEND;\r
+ PicoVideoFIFOSync(SekCyclesDone()-Pico.t.m68c_line_start);\r
+ if (pvid->status & SR_DMA) {\r
elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",\r
- Pico.m.dma_xfers, SekPc);\r
+ fifo_total, SekPc);\r
+ fifo_total = fifo_ql = 0;\r
+ }\r
+ pvid->status |= SR_DMA;\r
\r
len = GetDmaLength();\r
source =Pico.video.reg[0x15];\r
DmaSlow(len, source << 1); // 68000 to VDP\r
else if (method == 3)\r
DmaCopy(len); // VRAM Copy\r
- else\r
+ else {\r
+ pvid->status |= PVS_DMAFILL;\r
return;\r
-\r
+ }\r
source += len;\r
Pico.video.reg[0x13] = Pico.video.reg[0x14] = 0;\r
Pico.video.reg[0x15] = source;\r
pvid->addr_u = (u8)((cmd >> 2) & 1);\r
}\r
\r
-static void DrawSync(int blank_on)\r
+// VDP interface\r
+ \r
+static void DrawSync(int skip)\r
{\r
int lines = Pico.video.reg[1]&0x08 ? 240 : 224;\r
- if (Pico.m.scanline < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&\r
- !PicoIn.skipFrame && Pico.est.DrawScanline <= Pico.m.scanline) {\r
+ int last = Pico.m.scanline - (skip || blankline == Pico.m.scanline);\r
+\r
+ if (last < lines && !(PicoIn.opt & POPT_ALT_RENDERER) &&\r
+ !PicoIn.skipFrame && Pico.est.DrawScanline <= last) {\r
//elprintf(EL_ANOMALY, "sync");\r
- PicoDrawSync(Pico.m.scanline, blank_on);\r
+ if (blankline >= 0 && blankline < last) {\r
+ PicoDrawSync(blankline, 1);\r
+ blankline = -1;\r
+ }\r
+ PicoDrawSync(last, 0);\r
}\r
}\r
\r
pvid->pending=0;\r
}\r
\r
- if (!(pvid->status & SR_VB) && (pvid->reg[1]&0x40) && !(PicoIn.opt&POPT_DIS_VDP_FIFO))\r
+ if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))\r
{\r
- int use = pvid->type == 1 ? 2 : 1;\r
- pvid->lwrite_cnt -= use;\r
- if (pvid->lwrite_cnt < 0)\r
- SekCyclesBurnRun(488 - (SekCyclesDone()-Pico.t.m68c_line_start));\r
- elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} #%i @ %06x",\r
- Pico.video.addr, d, SekCyclesDone(), Pico.video.type, pvid->lwrite_cnt, SekPc);\r
+ fifo_data[++fifo_dx&3] = d;\r
+ SekCyclesBurnRun(PicoVideoFIFOWrite(1, pvid->type == 1, 0, PVS_CPUWR));\r
+\r
+ elprintf(EL_ASVDP, "VDP data write: [%04x] %04x [%u] {%i} @ %06x",\r
+ Pico.video.addr, d, SekCyclesDone(), Pico.video.type, SekPc);\r
}\r
VideoWrite(d);\r
\r
- if ((pvid->command&0x80) && (pvid->reg[1]&0x10) && (pvid->reg[0x17]>>6)==2)\r
- DmaFill(d);\r
+ // start DMA fill on write. NB VSRAM and CRAM fills use wrong FIFO data.\r
+ if ((pvid->status & (PVS_DMAPEND|PVS_DMAFILL)) == (PVS_DMAPEND|PVS_DMAFILL))\r
+ DmaFill(fifo_data[(fifo_dx + !!(pvid->type&~0x81))&3]);\r
\r
break;\r
\r
if (pvid->pending)\r
{\r
// Low word of command:\r
+ if (!(pvid->reg[1]&0x10))\r
+ d = (d&~0x80)|(pvid->command&0x80);\r
pvid->command &= 0xffff0000;\r
pvid->command |= d;\r
pvid->pending = 0;\r
// Register write:\r
int num=(d>>8)&0x1f;\r
int dold=pvid->reg[num];\r
- int blank_on = 0;\r
+ int skip=0;\r
pvid->type=0; // register writes clear command (else no Sega logo in Golden Axe II)\r
if (num > 0x0a && !(pvid->reg[1]&4)) {\r
elprintf(EL_ANOMALY, "%02x written to reg %02x in SMS mode @ %06x", d, num, SekPc);\r
return;\r
}\r
\r
- if (num == 1 && !(d&0x40) && SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)\r
- blank_on = 1;\r
- DrawSync(blank_on);\r
+ if (num == 0 && !(pvid->reg[0]&2) && (d&2))\r
+ hvlatch = PicoVideoRead(0x08);\r
+ if (num == 1 && ((pvid->reg[1]^d)&0x40)) {\r
+ PicoVideoFIFOMode(d & 0x40);\r
+ // handle line blanking before line rendering\r
+ if (SekCyclesDone() - Pico.t.m68c_line_start <= 488-390) {\r
+ skip = 1;\r
+ blankline = d&0x40 ? -1 : Pico.m.scanline;\r
+ }\r
+ }\r
+ DrawSync(skip);\r
pvid->reg[num]=(unsigned char)d;\r
switch (num)\r
{\r
}\r
}\r
\r
-static u32 SrLow(const struct PicoVideo *pv)\r
+static u32 VideoSr(const struct PicoVideo *pv)\r
{\r
unsigned int c, d = pv->status;\r
+ unsigned int hp = pv->reg[12]&1 ? 32:40; // HBLANK start\r
+ unsigned int hl = pv->reg[12]&1 ? 94:84; // HBLANK length\r
\r
c = SekCyclesDone();\r
- if (c - Pico.t.m68c_line_start - 39 < 92)\r
+ if (c - Pico.t.m68c_line_start - hp < hl)\r
d |= SR_HB;\r
- if (CYCLES_GT(c, Pico.t.dma_end))\r
- d &= ~SR_DMA;\r
+\r
+ PicoVideoFIFOSync(c-Pico.t.m68c_line_start);\r
+ if (pv->status & SR_DMA)\r
+ d |= SR_EMPT; // unused by DMA, or rather flags not updated?\r
+ else if (fifo_total >= 4)\r
+ d |= SR_FULL;\r
+ else if (!fifo_total)\r
+ d |= SR_EMPT;\r
return d;\r
}\r
\r
if (a == 0x04) // control port\r
{\r
struct PicoVideo *pv = &Pico.video;\r
- unsigned int d = SrLow(pv);\r
- pv->pending = 0;\r
+ unsigned int d = VideoSr(pv);\r
+ if (pv->pending) {\r
+ CommandChange();\r
+ pv->pending = 0;\r
+ }\r
elprintf(EL_SR, "SR read: %04x [%u] @ %06x", d, SekCyclesDone(), SekPc);\r
return d;\r
}\r
unsigned int d;\r
\r
d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME\r
- if (Pico.video.reg[12]&1)\r
- d = hcounts_40[d];\r
- else d = hcounts_32[d];\r
+ if (Pico.video.reg[0]&2)\r
+ d = hvlatch;\r
+ else if (Pico.video.reg[12]&1)\r
+ d = hcounts_40[d] | (Pico.video.v_counter << 8);\r
+ else d = hcounts_32[d] | (Pico.video.v_counter << 8);\r
\r
elprintf(EL_HVCNT, "hv: %02x %02x [%u] @ %06x", d, Pico.video.v_counter, SekCyclesDone(), SekPc);\r
- return d | (Pico.video.v_counter << 8);\r
+ return d;\r
}\r
\r
if (a==0x00) // data port\r
\r
unsigned char PicoVideoRead8CtlH(void)\r
{\r
- u8 d = (u8)(Pico.video.status >> 8);\r
- Pico.video.pending = 0;\r
+ u8 d = VideoSr(&Pico.video) >> 8;\r
+ if (Pico.video.pending) {\r
+ CommandChange();\r
+ Pico.video.pending = 0;\r
+ }\r
elprintf(EL_SR, "SR read (h): %02x @ %06x", d, SekPc);\r
return d;\r
}\r
\r
unsigned char PicoVideoRead8CtlL(void)\r
{\r
- u8 d = SrLow(&Pico.video);\r
- Pico.video.pending = 0;\r
+ u8 d = VideoSr(&Pico.video);\r
+ if (Pico.video.pending) {\r
+ CommandChange();\r
+ Pico.video.pending = 0;\r
+ }\r
elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);\r
return d;\r
}\r
notaz.gp2x.de / picodrive.git / commitdiff