\r
pcd_sync_s68k(SekCyclesDone(), 0);\r
Pico_mcd->s68k_regs[a] = d;\r
+ if (a == 0x03) {\r
+ // There are cases when master checks for successful switching of RAM to\r
+ // slave. This can produce race conditions where slave switches RAM back to\r
+ // master while master is delayed by interrupt before the check executes.\r
+ // Delay slave a bit to make sure master can check before slave changes.\r
+ SekCycleCntS68k += 24;\r
+ }\r
if (Pico_mcd->m.s68k_poll_a == (a & ~1))\r
{\r
if (Pico_mcd->m.s68k_poll_cnt > POLL_LIMIT) {\r