more accuracy fixes

git-svn-id: file:///home/notaz/opt/svn/PicoDrive@186 be3aeb3a-fb24-0410-a615-afba39da0efa

diff --git a/cpu/Cyclone/Cyclone.txt b/cpu/Cyclone/Cyclone.txt
index 4858b18..b2c675d 100644 (file)
--- a/cpu/Cyclone/Cyclone.txt
+++ b/cpu/Cyclone/Cyclone.txt
@@ -42,8 +42,9 @@ v0.0087 notaz
     - Merged some duplicate handler endings\r
   + Cyclone now does better job avoiding pipeline interlocks.\r
   + Replaced incorrect handler of DBT with proper one.\r
-  + Fixed "MOVEA (An)+ An" behaviour.\r
-  + Fixed flags for ROXR and LSR. Hopefully got them right now.\r
+  + Changed "MOVEA (An)+ An" behaviour.\r
+  + Fixed flag behaviour of ROXR, ASL, LSR and NBCD in certain situations.\r
+    Hopefully got them right now.\r
   + Additional functionality added for MAME and other ports (see config.h).\r
 \r
 v0.0086 notaz\r

diff --git a/cpu/Cyclone/OpArith.cpp b/cpu/Cyclone/OpArith.cpp
index fe3d40a..47ff8b1 100644 (file)
--- a/cpu/Cyclone/OpArith.cpp
+++ b/cpu/Cyclone/OpArith.cpp
@@ -237,7 +237,7 @@ int OpMul(int op)
   EaCalc(10,0x0e00,rea, 2);\r
   EaRead(10,     2,rea, 2,0x0e00);\r
 \r
-  ot("  movs r0,r0,asl #16\n");\r
+  ot("  movs r1,r0,asl #16\n");\r
 \r
   if (type==0) // div\r
   {\r
@@ -249,20 +249,25 @@ int OpMul(int op)
     if (sign)\r
     {\r
       ot("  mov r11,#0 ;@ r11 = 1 or 2 if the result is negative\n");\r
-      ot("  orrmi r11,r11,#1\n");\r
-      ot("  mov r0,r0,asr #16\n");\r
-      ot("  rsbmi r0,r0,#0 ;@ Make r0 positive\n");\r
-      ot("\n");\r
       ot("  tst r2,r2\n");\r
       ot("  orrmi r11,r11,#2\n");\r
       ot("  rsbmi r2,r2,#0 ;@ Make r2 positive\n");\r
       ot("\n");\r
+      ot("  movs r0,r1,asr #16\n");\r
+      ot("  orrmi r11,r11,#1\n");\r
+      ot("  rsbmi r0,r0,#0 ;@ Make r0 positive\n");\r
+      ot("\n");\r
+      ot(";@ detect the nasty 0x80000000 / -1 situation\n");\r
+      ot("  mov r3,r2,asr #31\n");\r
+      ot("  eors r3,r3,r1,asr #16\n");\r
+      ot("  beq wrendofop%.4x\n",op);\r
     }\r
     else\r
     {\r
-      ot("  mov r0,r0,lsr #16 ;@ use only 16 bits of divisor\n");\r
+      ot("  mov r0,r1,lsr #16 ;@ use only 16 bits of divisor\n");\r
     }\r
 \r
+    ot("\n");\r
     ot(";@ Divide r2 by r0\n");\r
     ot("  mov r3,#0\n");\r
     ot("  mov r1,r0\n");\r
@@ -299,6 +304,8 @@ int OpMul(int op)
       ot("  cmp r3,r1,asr #16 ;@ signed overflow?\n");\r
       ot("  orrne r9,r9,#0x10000000 ;@ set overflow flag\n");\r
       ot("  bne endofop%.4x ;@ overflow!\n",op);\r
+      ot("\n");\r
+      ot("wrendofop%.4x%s\n",op,ms?"":":");\r
     }\r
     else\r
     {\r
@@ -306,6 +313,7 @@ int OpMul(int op)
       ot("  movs r1,r3,lsr #16 ;@ check for overflow condition\n");\r
       ot("  orrne r9,r9,#0x10000000 ;@ set overflow flag\n");\r
       ot("  bne endofop%.4x ;@ overflow!\n",op);\r
+      ot("\n");\r
     }\r
 \r
     ot("  mov r1,r3,lsl #16 ;@ Clip to 16-bits\n");\r
@@ -319,7 +327,7 @@ int OpMul(int op)
   if (type==1)\r
   {\r
     ot(";@ Get 16-bit signs right:\n");\r
-    ot("  mov r0,r0,%s #16\n",sign?"asr":"lsr");\r
+    ot("  mov r0,r1,%s #16\n",sign?"asr":"lsr");\r
     ot("  mov r2,r2,lsl #16\n");\r
     ot("  mov r2,r2,%s #16\n",sign?"asr":"lsr");\r
     ot("\n");\r
@@ -486,29 +494,31 @@ int OpNbcd(int op)
   ot("  mov r0,r0,asl #24\n");\r
   ot("  and r2,r2,#0x20000000\n");\r
   ot("  add r2,r0,r2,lsr #5 ;@ add X\n");\r
-  ot("  rsbs r1,r2,#0x9a000000 ;@ do arithmetic\n");\r
+  ot("  rsb r11,r2,#0x9a000000 ;@ do arithmetic\n");\r
 \r
-  ot("  orrmi r9,r9,#0x80000000 ;@ N\n");\r
-  ot("  cmp r1,#0x9a000000\n");\r
+  ot("  cmp r11,#0x9a000000\n");\r
   ot("  beq finish%.4x\n",op);\r
   ot("\n");\r
 \r
-  ot("  mvn r3,r9,lsr #3 ;@ Undefined V behavior\n",op);\r
-  ot("  and r2,r1,#0x0f000000\n");\r
+  ot("  mvn r3,r11,lsr #31 ;@ Undefined V behavior\n",op);\r
+  ot("  and r2,r11,#0x0f000000\n");\r
   ot("  cmp r2,#0x0a000000\n");\r
-  ot("  andeq r1,r1,#0xf0000000\n");\r
-  ot("  addeq r1,r1,#0x10000000\n");\r
-  ot("  and r3,r3,r1,lsr #3 ;@ Undefined V behavior part II\n",op);\r
-  ot("  tst r1,r1\n");\r
-  ot("  orr r9,r9,r3 ;@ save V\n",op);\r
+  ot("  andeq r11,r11,#0xf0000000\n");\r
+  ot("  addeq r11,r11,#0x10000000\n");\r
+  ot("  and r3,r3,r11,lsr #31 ;@ Undefined V behavior part II\n",op);\r
+  ot("  movs r1,r11,asr #24\n");\r
   ot("  bicne r9,r9,#0x40000000 ;@ Z\n");\r
+  ot("  orr r9,r9,r3,lsl #28 ;@ save V\n",op);\r
   ot("  orr r9,r9,#0x20000000 ;@ C\n");\r
   ot("\n");\r
 \r
-  EaWrite(10,     1, ea,0,0x3f,1);\r
+  EaWrite(10,     1, ea,0,0x3f,0,0);\r
 \r
   ot("finish%.4x%s\n",op,ms?"":":");\r
+  ot("  tst r11,r11\n");\r
+  ot("  orrmi r9,r9,#0x80000000 ;@ N\n");\r
   ot("  str r9,[r7,#0x4c] ;@ Save X\n");\r
+  ot("\n");\r
 \r
   OpEnd(ea);\r
 \r
@@ -541,9 +551,19 @@ int OpAritha(int op)
   if(size==2&&(sea<0x10||sea==0x3c)) Cycles+=2;\r
   if(type==1) Cycles=6;\r
 \r
-  // to handle suba.w (A0)+, A0 properly, must calc reg EA first\r
-  EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);\r
-  EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
+  // EA calculation order defines how situations like  suba.w (A0)+, A0 get handled.\r
+  // different emus act differently in this situation, I couldn't fugure which is right behaviour.\r
+  // This is Musashi's behaviour.\r
+  if (type == 1)\r
+  {\r
+    EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
+    EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);\r
+  }\r
+  else\r
+  {\r
+    EaCalcReadNoSE(type!=1?10:-1,11,dea,2,0x0e00);\r
+    EaCalcReadNoSE(-1,0,sea,size,0x003f);\r
+  }\r
 \r
   if (size<2) ot("  mov r0,r0,asl #%d\n\n",size?16:24);\r
   if (size<2) asr=(char *)(size?",asr #16":",asr #24");\r

diff --git a/cpu/Cyclone/OpBranch.cpp b/cpu/Cyclone/OpBranch.cpp
index 5d132cf..da76306 100644 (file)
--- a/cpu/Cyclone/OpBranch.cpp
+++ b/cpu/Cyclone/OpBranch.cpp
@@ -11,8 +11,7 @@ static void CheckPc(int reg)
   ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
   ot("  mov r4,r0\n");\r
 #else\r
-  if (reg != 4)\r
-    ot("  mov r4,r%i\n", reg);\r
+  ot("  bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
 #endif\r
   ot("\n");\r
 }\r
@@ -194,7 +193,7 @@ int Op4E70(int op)
     case 6: // trapv\r
     OpStart(op,0x10); Cycles=4;\r
     ot("  tst r9,#0x10000000\n");\r
-    ot("  subne r5,r5,#%i\n",30);\r
+    ot("  subne r5,r5,#%i\n",34);\r
     ot("  movne r0,#0x1c ;@ TRAPV exception\n");\r
     ot("  blne Exception\n");\r
     OpEnd(0x10);\r
@@ -336,6 +335,7 @@ int OpDbra(int op)
     ot("  addeq r4,r4,#2 ;@ Skip branch offset\n");\r
     ot("  subeq r5,r5,#4 ;@ additional cycles\n");\r
     ot("  addne r4,r4,r0 ;@ r4 = New PC\n");\r
+    ot("  bic r4,r4,#1\n"); // we do not emulate address errors\r
     ot("\n");\r
 #endif\r
     Cycles=12-2;\r
@@ -384,6 +384,7 @@ int OpBranch(int op)
   if (offset==0)  size=1;\r
   if (offset==-1) size=2;\r
 \r
+  if (size==2) size=0; // 000 model does not support long displacement\r
   if (size) use=op; // 16-bit or 32-bit\r
   else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
 \r
@@ -451,6 +452,8 @@ int OpBranch(int op)
     Cycles=18; // always 18\r
   }\r
 \r
+  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+\r
 #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
   if (offset!=0 && offset!=-1) checkpc=1;\r
 #endif\r
@@ -462,12 +465,11 @@ int OpBranch(int op)
 #endif\r
   if (checkpc)\r
   {\r
-    ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
     CheckPc(0);\r
   }\r
   else\r
   {\r
-    ot("  add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
+    ot("  bic r4,r0,#1\n"); // we do not emulate address errors\r
     ot("\n");\r
   }\r
 \r

diff --git a/cpu/Cyclone/OpLogic.cpp b/cpu/Cyclone/OpLogic.cpp
index 7623704..65d2293 100644 (file)
--- a/cpu/Cyclone/OpLogic.cpp
+++ b/cpu/Cyclone/OpLogic.cpp
@@ -403,7 +403,7 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       ot("\n");\r
     }\r
 \r
-    if (type==0 && dir) ot("  mov r3,r0 ;@ save old value for V flag calculation\n");\r
+    if (type==0 && dir) ot("  adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
 \r
     ot(";@ Shift register:\n");\r
     if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
@@ -434,7 +434,8 @@ static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
       ot("  mov r1,#0x80000000\n");\r
       ot("  ands r3,r3,r1,asr %s\n", pct);\r
       ot("  cmpne r3,r1,asr %s\n", pct);\r
-      ot("  biceq r9,r9,#0x10000000\n");\r
+      ot("  eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
+      ot("  tsteq r1,#0x80000000\n");\r
       ot("  orrne r9,r9,#0x10000000\n");\r
       ot("\n");\r
     }\r

diff --git a/cpu/Cyclone/tests/test_misc2_gen.c b/cpu/Cyclone/tests/test_misc2_gen.c
index 8341ea4..108156b 100644 (file)
--- a/cpu/Cyclone/tests/test_misc2_gen.c
+++ b/cpu/Cyclone/tests/test_misc2_gen.c
@@ -87,8 +87,6 @@ int main()
                {
                        if ((op&0x00ff) == 0)
                                write_op(op, 6, 0, 0);
-                       else if ((op&0x00ff) == 0xff)
-                               write_op(op, 0, 6, 0);
                }
                else if ((op&0xf0f8)==0x50c8) // DBxx
                {
@@ -96,7 +94,7 @@ int main()
                }
                else if ((op&0xff80)==0x4e80) // Jsr
                {
-                       int addr = 0x300 + i*8 + 8;
+                       int addr = 0x300 + op*8 + 8;
                        if ((op&0x3f) == 0x39)
                                write_op(op, addr >> 16, addr & 0xffff, 0);
                }
@@ -112,7 +110,8 @@ int main()
        }
 
        // jump to the beginning
-       write_op(0x4ef8, 0x300, 0, 0);
+       write_op(0x4ef8, 0x300, 0x4ef8, 0x300);
+       write_op(0x4ef8, 0x300, 0x4ef8, 0x300);
 
        fclose(f);
        return 0;