core vdp, more fixes for cpu write access and save/load

diff --git a/pico/videoport.c b/pico/videoport.c
index a029a15..1c69e88 100644 (file)
--- a/pico/videoport.c
+++ b/pico/videoport.c
@@ -158,7 +158,7 @@ int (*PicoDmaHook)(u32 source, int len, unsigned short **base, u32 *mask) = NULL
  *                     full    total==4\r
  *                     wait    total>4\r
  * Conditions:\r
- * fifo_slot is always behind slot2cyc[cycles]. Advancing it beyond cycles\r
+ * fifo_slot is normally behind slot2cyc[cycles]. Advancing it beyond cycles\r
  * implies blocking the 68k up to that slot.\r
  *\r
  * A FIFO write goes to the end of the FIFO queue, but DMA running in background\r
@@ -213,25 +213,23 @@ static __inline int AdvanceFIFOEntry(struct VdpFIFO *vf, struct PicoVideo *pv, i
   if (!(vf->fifo_queue[vf->fifo_qx] & FQ_BGDMA))\r
     vf->fifo_total -= ((cnt & b) + l) >> b;\r
   cnt -= l;\r
+  pv->fifo_cnt = cnt;\r
 \r
   // if entry has been processed...\r
   if (cnt == 0) {\r
     // remove entry from FIFO\r
-    if (vf->fifo_ql) {\r
-      vf->fifo_queue[vf->fifo_qx] = 0;\r
-      vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;\r
-    }\r
+    vf->fifo_queue[vf->fifo_qx] = 0;\r
+    vf->fifo_qx = (vf->fifo_qx+1) & 7, vf->fifo_ql --;\r
     // start processing for next entry if there is one\r
     if (vf->fifo_ql) {\r
       b = vf->fifo_queue[vf->fifo_qx] & FQ_BYTE;\r
-      cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;\r
+      pv->fifo_cnt = (vf->fifo_queue[vf->fifo_qx] >> 3) << b;\r
     } else { // FIFO empty\r
       pv->status &= ~PVS_FIFORUN;\r
       vf->fifo_total = 0;\r
     }\r
   }\r
 \r
-  pv->fifo_cnt = cnt;\r
   return l;\r
 }\r
 \r
@@ -363,11 +361,11 @@ int PicoVideoFIFOWrite(int count, int flags, unsigned sr_mask,unsigned sr_flags)
       // XXX if interrupting a DMA fill, fill data changes\r
       if (x == vf->fifo_qx) { // overtaking to queue head?\r
         int f = vf->fifo_queue[x] & 7;\r
-        vf->fifo_queue[(x+1) & 7] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
+        vf->fifo_queue[x] = (pv->fifo_cnt >> (f & FQ_BYTE) << 3) | f;\r
         pv->status &= ~PVS_FIFORUN;\r
-      } else\r
-        // push background DMA back\r
-        vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];\r
+      }\r
+      // push background DMA back\r
+      vf->fifo_queue[(x+1) & 7] = vf->fifo_queue[x];\r
       x = (x-1) & 7;\r
     }\r
 \r
@@ -1152,16 +1150,17 @@ void PicoVideoLoad(void)
   // convert former dma_xfers (why was this in PicoMisc anyway?)\r
   if (Pico.m.dma_xfers) {\r
     pv->status |= SR_DMA;\r
-    pv->fifo_cnt = Pico.m.dma_xfers * (b ? 2 : 1);\r
+    pv->fifo_cnt = Pico.m.dma_xfers << b;\r
     Pico.m.dma_xfers = 0;\r
   }\r
   // make an entry in the FIFO if there are outstanding transfers\r
   vf->fifo_ql = vf->fifo_total = 0;\r
   if (pv->fifo_cnt) {\r
     pv->status |= PVS_FIFORUN|PVS_CPUWR;\r
-    vf->fifo_total = (pv->fifo_cnt + (b)) >> b;\r
-    if (pv->status & SR_DMA)\r
-      b |= (pv->status & (PVS_DMAFILL|PVS_DMABG)) ? FQ_BGDMA : FQ_FGDMA;\r
+    if (!(pv->status & PVS_DMABG))\r
+      vf->fifo_total = (pv->fifo_cnt + b) >> b;\r
+    if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL))\r
+      b |= (pv->status & PVS_DMABG) ? FQ_BGDMA : FQ_FGDMA;\r
     vf->fifo_queue[vf->fifo_qx] = (vf->fifo_total << 3) | b;\r
     vf->fifo_ql = 1;\r
   }\r