#include "../../PicoInt.h"
-#define TCACHE_SIZE (256*1024)
+#define TCACHE_SIZE (1024*1024)
static unsigned int *block_table[0x5090/2];
static unsigned int *block_table_iram[15][0x800/2];
static unsigned int *tcache = NULL;
static void op00(unsigned int op, unsigned int imm)
{
unsigned int tmpv;
- PC = ((unsigned short *)&op) + 1; /* FIXME: needed for interpreter */
+ PC = ((unsigned short *)(void *)&op) + 1; /* FIXME: needed for interpreter */
if (op == 0) return; // nop
if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
// not sure. MAME claims that only hi word is transfered.
int cond = 0;
do {
COND_CHECK
- if (cond) { int new_PC = imm; write_STACK(GET_PC()); write_PC(new_PC); }
+ if (cond) { int new_PC = imm; write_STACK(GET_PC()); SET_PC(new_PC); }
}
while (0);
}
{
int cond = 0;
COND_CHECK
- if (cond) write_PC(imm);
+ if (cond) SET_PC(imm);
}
- while(0);
+ while (0);
}
// mod cond, op
*tcache_ptr++ = (u32) &ssp->gr[SSP_PC].v; // -2 ptr to rPC
*tcache_ptr++ = (u32) in_funcs; // -1 func pool
+ printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
block_start = tcache_ptr;
emit_block_prologue();
- //printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<1);
- for (;;)
+ for (; icount < 100;)
{
icount++;
+ //printf(" insn #%i\n", icount);
op = PROGRAM(pc++);
op1 = op >> 9;
- emit_mov_const16(0, op);
+ emit_mov_const(0, op);
// need immediate?
if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6) {
- emit_mov_const16(1, PROGRAM(pc++)); // immediate
+ emit_mov_const(1, PROGRAM(pc++)); // immediate
}
// dump PC
nblocks++;
//if (pc >= 0x400)
printf("%i blocks, %i bytes\n", nblocks, (tcache_ptr - tcache)*4);
+ //printf("%p %p\n", tcache_ptr, emit_block_epilogue);
#if 0
{
}
exit(0);
#endif
+
+ handle_caches();
+
return block_start;
}
ssp1601_reset_local(ssp);
}
-static void handle_caches()
-{
-#ifdef ARM
- extern void flush_inval_dcache(const void *start_addr, const void *end_addr);
- extern void flush_inval_icache(const void *start_addr, const void *end_addr);
- flush_inval_dcache(tcache, tcache_ptr);
- flush_inval_icache(tcache, tcache_ptr);
-#else
-#error wth
-#endif
-}
-
void ssp1601_dyn_run(int cycles)
{
while (cycles > 0)
//printf("enter @ %04x, PC=%04x\n", (PC - tcache)<<1, rPC<<1);
g_cycles = 0;
- handle_caches();
+ //printf("enter %04x\n", rPC);
trans_entry();
+ //printf("leave %04x\n", rPC);
cycles -= g_cycles;
/*
if (!had_jump) {
#define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
-static void emit_mov_const16(int d, unsigned int val)
+static void emit_mov_const(int d, unsigned int val)
{
int need_or = 0;
- if (val & 0xff00) {
- EOP_MOV_IMM(0, d, 24/2, (val>>8)&0xff);
+ if (val & 0xff000000) {
+ EOP_MOV_IMM(0, d, 8/2, (val>>24)&0xff);
need_or = 1;
}
- if ((val & 0xff) || !need_or)
- EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, d, d, 0, val&0xff);
+ if (val & 0x00ff0000) {
+ EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 16/2, (val>>16)&0xff);
+ need_or = 1;
+ }
+ if (val & 0x0000ff00) {
+ EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 24/2, (val>>8)&0xff);
+ need_or = 1;
+ }
+ if ((val &0x000000ff) || !need_or)
+ EOP_C_DOP_IMM(A_COND_AL,need_or ? A_OP_ORR : A_OP_MOV, 0, need_or ? d : 0, d, 0, val&0xff);
+}
+
+static void check_offset_12(unsigned int val)
+{
+ if (!(val & ~0xfff)) return;
+ printf("offset_12 overflow %04x\n", val);
+ exit(1);
}
static void emit_block_prologue(void)
{
int back = (tcache_ptr - block_start) + 2;
back += 3; // g_cycles
+ check_offset_12(back<<2);
+
EOP_LDR_NEGIMM(2,15,back<<2); // ldr r2,[pc,#back]
- emit_mov_const16(3, icount);
+ emit_mov_const(3, icount);
EOP_STR_SIMPLE(3,2); // str r3,[r2]
EOP_LDMFD_ST(A_R14M); // ldmfd r13!, {r14}
{
int back = (tcache_ptr - block_start) + 2;
back += 2; // rPC ptr
+ check_offset_12(back<<2);
+
EOP_LDR_NEGIMM(2,15,back<<2); // ldr r2,[pc,#back]
- emit_mov_const16(3, pc);
+ emit_mov_const(3, pc<<16);
EOP_STR_SIMPLE(3,2); // str r3,[r2]
}
{
int back = (tcache_ptr - block_start) + 2;
back += 1; // func table
+ check_offset_12(back<<2);
+
EOP_LDR_NEGIMM(2,15,back<<2); // ldr r2,[pc,#back]
EOP_MOV_REG_SIMPLE(14,15); // mov lr,pc
EOP_LDR_IMM(15,2,op1<<2); // ldr pc,[r2,#op1]
}
+static void handle_caches()
+{
+#ifdef ARM
+ extern void flush_inval_caches(const void *start_addr, const void *end_addr);
+ flush_inval_caches(tcache, tcache_ptr);
+#else
+#error wth
+#endif
+}
+