#define POPT_EN_32X (1<<20) // x0 0000\r
#define POPT_EN_PWM (1<<21)\r
#define POPT_PWM_IRQ_OPT (1<<22)\r
+#define POPT_DIS_FM_SSGEG (1<<23)\r
\r
#define PAHW_MCD (1<<0)\r
#define PAHW_32X (1<<1)\r
ym2612_pack_state();\r
memcpy(state, YM2612GetRegs(), 0x204);\r
}\r
- YM2612Init(Pico.m.pal ? OSC_PAL/7 : OSC_NTSC/7, PicoIn.sndRate);\r
+ YM2612Init(Pico.m.pal ? OSC_PAL/7 : OSC_NTSC/7, PicoIn.sndRate, !(PicoIn.opt&POPT_DIS_FM_SSGEG));\r
if (preserve_state) {\r
// feed it back it's own registers, just like after loading state\r
memcpy(YM2612GetRegs(), state, 0x204);\r
// flags: stereo, ssg_enabled, disabled, _, pan_r, pan_l\r
chan_render_prep();\r
#define BIT_IF(v,b,c) { v &= ~(1<<(b)); if (c) v |= 1<<(b); }\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00000f));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00000f) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0x00000f) active_chs |= chan_render(buffer, length, 0, flags|((pan&0x003)<<4)) << 0;\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0000f0));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0000f0) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0x0000f0) active_chs |= chan_render(buffer, length, 1, flags|((pan&0x00c)<<2)) << 1;\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0x000f00));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0x000f00) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0x000f00) active_chs |= chan_render(buffer, length, 2, flags|((pan&0x030) )) << 2;\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00f000));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0x00f000) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0x00f000) active_chs |= chan_render(buffer, length, 3, flags|((pan&0x0c0)>>2)) << 3;\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0f0000));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0x0f0000) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0x0f0000) active_chs |= chan_render(buffer, length, 4, flags|((pan&0x300)>>4)) << 4;\r
- BIT_IF(flags, 1, (ym2612.ssg_mask & 0xf00000));\r
+ BIT_IF(flags, 1, (ym2612.ssg_mask & 0xf00000) && (ym2612.OPN.ST.flags & 1));\r
if (ym2612.slot_mask & 0xf00000) active_chs |= chan_render(buffer, length, 5, flags|((pan&0xc00)>>6)|(!!ym2612.dacen<<2)) << 5;\r
#undef BIT_IF\r
chan_render_finish();\r
\r
\r
/* initialize YM2612 emulator */\r
-void YM2612Init_(int clock, int rate)\r
+void YM2612Init_(int clock, int rate, int ssg)\r
{\r
memset(&ym2612, 0, sizeof(ym2612));\r
init_tables();\r
\r
ym2612.OPN.ST.clock = clock;\r
ym2612.OPN.ST.rate = rate;\r
+ ym2612.OPN.ST.flags = (ssg ? 1:0);\r
\r
OPNSetPres( 6*24 );\r
\r
UINT8 address; /* 10 address register | need_save */\r
UINT8 status; /* 11 status flag | need_save */\r
UINT8 mode; /* mode CSM / 3SLOT */\r
- UINT8 pad;\r
+ UINT8 flags; /* operational flags */\r
int TA; /* timer a */\r
int TAC; /* timer a maxval */\r
int TAT; /* timer a ticker | need_save */\r
extern YM2612 ym2612;\r
#endif\r
\r
-void YM2612Init_(int baseclock, int rate);\r
+void YM2612Init_(int baseclock, int rate, int ssg);\r
void YM2612ResetChip_(void);\r
int YM2612UpdateOne_(int *buffer, int length, int stereo, int is_buf_empty);\r
\r
#else\r
/* GP2X specific */\r
#include "../../platform/gp2x/940ctl.h"\r
-#define YM2612Init(baseclock,rate) do { \\r
- if (PicoIn.opt&POPT_EXT_FM) YM2612Init_940(baseclock, rate); \\r
- else YM2612Init_(baseclock, rate); \\r
+#define YM2612Init(baseclock,rate,ssg) do { \\r
+ if (PicoIn.opt&POPT_EXT_FM) YM2612Init_940(baseclock, rate, ssg); \\r
+ else YM2612Init_(baseclock, rate, ssg); \\r
} while (0)\r
#define YM2612ResetChip() do { \\r
if (PicoIn.opt&POPT_EXT_FM) YM2612ResetChip_940(); \\r
mee_range_h ("Overclock M68k (%)", MA_OPT2_OVERCLOCK_M68K,currentConfig.overclock_68k, 0, 1000, h_ovrclk),
mee_onoff ("Emulate Z80", MA_OPT2_ENABLE_Z80, PicoIn.opt, POPT_EN_Z80),
mee_onoff ("Emulate YM2612 (FM)", MA_OPT2_ENABLE_YM2612, PicoIn.opt, POPT_EN_FM),
+ mee_onoff ("Disable YM2612 SSG-EG", MA_OPT2_DISABLE_YM_SSG,PicoIn.opt, POPT_DIS_FM_SSGEG),
mee_onoff ("Emulate SN76496 (PSG)", MA_OPT2_ENABLE_SN76496,PicoIn.opt, POPT_EN_PSG),
mee_onoff ("gzip savestates", MA_OPT2_GZIP_STATES, currentConfig.EmuOpt, EOPT_GZIP_SAVES),
mee_onoff ("Don't save last used ROM", MA_OPT2_NO_LAST_ROM, currentConfig.EmuOpt, EOPT_NO_AUTOSVCFG),
MA_OPT2_VSYNC,
MA_OPT2_ENABLE_Z80,
MA_OPT2_ENABLE_YM2612,
+ MA_OPT2_DISABLE_YM_SSG,
MA_OPT2_ENABLE_SN76496,
MA_OPT2_GZIP_STATES,
MA_OPT2_NO_LAST_ROM,
}\r
\r
\r
-void YM2612Init_940(int baseclock, int rate)\r
+void YM2612Init_940(int baseclock, int rate, int ssg)\r
{\r
static int oldrate;\r
\r
memset(shared_ctl, 0, sizeof(*shared_ctl));\r
\r
/* cause local ym2612 to init REGS */\r
- YM2612Init_(baseclock, rate);\r
+ YM2612Init_(baseclock, rate, ssg);\r
\r
internal_reset();\r
\r
void sharedmem940_init(void);\r
void sharedmem940_finish(void);\r
\r
-void YM2612Init_940(int baseclock, int rate);\r
+void YM2612Init_940(int baseclock, int rate, int ssg);\r
void YM2612ResetChip_940(void);\r
int YM2612UpdateOne_940(int *buffer, int length, int stereo, int is_buf_empty);\r
\r
case JOB940_INITALL:\r
/* ym2612 */\r
shared_ctl->writebuff0[0] = shared_ctl->writebuff1[0] = 0xffff;\r
- YM2612Init_(shared_ctl->baseclock, shared_ctl->rate);\r
+ YM2612Init_(shared_ctl->baseclock, shared_ctl->rate, 0);\r
/* Helix mp3 decoder */\r
__malloc_init();\r
shared_data->mp3dec = MP3InitDecoder();\r