DMNA handling fix

git-svn-id: file:///home/notaz/opt/svn/PicoDrive@555 be3aeb3a-fb24-0410-a615-afba39da0efa

diff --git a/Pico/cd/Memory.c b/Pico/cd/Memory.c
index c140976..9f61975 100644 (file)
--- a/Pico/cd/Memory.c
+++ b/Pico/cd/Memory.c
@@ -21,11 +21,13 @@ typedef unsigned int   u32;
 #ifdef _MSC_VER\r
 #define rdprintf\r
 #define wrdprintf\r
+#define r3printf\r
 #else\r
 //#define rdprintf dprintf\r
 #define rdprintf(...)\r
 //#define wrdprintf dprintf\r
 #define wrdprintf(...)\r
+#define r3printf(...)\r
 #endif\r
 \r
 #ifdef EMU_CORE_DEBUG\r
@@ -57,7 +59,7 @@ static u32 m68k_reg_read16(u32 a)
       d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r
       // the DMNA delay must only be visible on s68k side (Lunar2, Silpheed)\r
       if (Pico_mcd->m.state_flags&2) { d &= ~1; d |= 2; }\r
-      //printf("m68k_regs r3: %02x @%06x\n", (u8)d, SekPc);\r
+      r3printf(EL_STATUS, "m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r
       goto end;\r
     case 4:\r
       d = Pico_mcd->s68k_regs[4]<<8;\r
@@ -122,7 +124,7 @@ void m68k_reg_write8(u32 a, u32 d)
       return;\r
     case 3: {\r
       u32 dold = Pico_mcd->s68k_regs[3]&0x1f;\r
-      //printf("m68k_regs w3: %02x @%06x\n", (u8)d, SekPc);\r
+      r3printf(EL_STATUS, "m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r
       d &= 0xc2;\r
       if ((dold>>6) != ((d>>6)&3))\r
         dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r
@@ -134,10 +136,12 @@ void m68k_reg_write8(u32 a, u32 d)
       } else {\r
         //dold &= ~2; // ??\r
 #if 1\r
-       if ((d & 2) && !(dold & 2)) {\r
+       if (d & (d ^ dold) & 2) { // DMNA is being set\r
           Pico_mcd->m.state_flags |= 2; // we must delay setting DMNA bit (needed for Silpheed)\r
           d &= ~2;\r
        }\r
+        else\r
+          Pico_mcd->m.state_flags &= ~2;\r
 #else\r
         if (d & 2) dold &= ~1; // return word RAM to s68k in 2M mode\r
 #endif\r
@@ -239,7 +243,7 @@ u32 s68k_reg_read16(u32 a)
       return ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r
     case 2:\r
       d = (Pico_mcd->s68k_regs[2]<<8) | (Pico_mcd->s68k_regs[3]&0x1f);\r
-      //printf("s68k_regs r3: %02x @%06x\n", (u8)d, SekPcS68k);\r
+      r3printf(EL_STATUS, "s68k_regs r3: %02x @%06x", (u8)d, SekPcS68k);\r
       return s68k_poll_detect(a, d);\r
     case 6:\r
       return CDC_Read_Reg();\r
@@ -289,10 +293,11 @@ void s68k_reg_write8(u32 a, u32 d)
       return; // only m68k can change WP\r
     case 3: {\r
       int dold = Pico_mcd->s68k_regs[3];\r
-      //elprintf(EL_STATUS, "s68k_regs w3: %02x s@%06x", (u8)d, SekPcS68k);\r
+      r3printf(EL_STATUS, "s68k_regs w3: %02x @%06x", (u8)d, SekPcS68k);\r
       d &= 0x1d;\r
       d |= dold&0xc2;\r
-      if (d&4) {\r
+      if (d&4)\r
+      {\r
         if ((d ^ dold) & 5) {\r
           d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r
           PicoMemResetCD(d);\r
@@ -302,12 +307,14 @@ void s68k_reg_write8(u32 a, u32 d)
           PicoMemResetCDdecode(d);\r
 #endif\r
         if (!(dold & 4)) {\r
-          dprintf("wram mode 2M->1M");\r
+          r3printf(EL_STATUS, "wram mode 2M->1M");\r
           wram_2M_to_1M(Pico_mcd->word_ram2M);\r
         }\r
-      } else {\r
+      }\r
+      else\r
+      {\r
         if (dold & 4) {\r
-          dprintf("wram mode 1M->2M");\r
+          r3printf(EL_STATUS, "wram mode 1M->2M");\r
           if (!(d&1)) { // it didn't set the ret bit, which means it doesn't want to give WRAM to m68k\r
             d &= ~3;\r
             d |= (dold&1) ? 2 : 1; // then give it to the one which had bank0 in 1M mode\r
@@ -319,6 +326,7 @@ void s68k_reg_write8(u32 a, u32 d)
           d |= dold&1;\r
         if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r
       }\r
+      Pico_mcd->m.state_flags &= ~2;\r
       break;\r
     }\r
     case 4:\r