core, fix 68k cycles in cyclone,fame (exceptions,bit ops,ADDI.L,TAS,CHK,MUL*,DIV*)

also syncs these changes between fame and cyclone

in accordance with the test_inst_speed, available here:
https://gendev.spritesmind.net/forum/viewtopic.php?t=3321
DIV* is only closely approximated, it can be slightly on the high side.

diff --git a/.gitmodules b/.gitmodules
index 4f610df..5d28012 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -3,7 +3,7 @@
        url = https://github.com/irixxxx/libpicofe.git
 [submodule "cpu/cyclone"]
        path = cpu/cyclone
-       url = https://github.com/notaz/cyclone68000.git
+       url = https://github.com/irixxxx/cyclone68000.git
 [submodule "pico/sound/emu2413"]
        path = pico/sound/emu2413
        url = https://github.com/digital-sound-antiques/emu2413.git

diff --git a/cpu/cyclone b/cpu/cyclone
index 425e3a4..ee45bb2 160000 (submodule)
--- a/cpu/cyclone
+++ b/cpu/cyclone
@@ -1 +1 @@
-Subproject commit 425e3a4066ee1cc8a3bae28956fbbdc9a516001d
+Subproject commit ee45bb2b10b3abf10a4335ea24fc029e3f61c10a

diff --git a/cpu/fame/famec.c b/cpu/fame/famec.c
index 9e832bc..a2edb3d 100644 (file)
--- a/cpu/fame/famec.c
+++ b/cpu/fame/famec.c
@@ -183,6 +183,11 @@
 // internals core macros\r
 /////////////////////////\r
 \r
+// helper macros\r
+#define BITCOUNT(r,v)  \\r
+    (r = (v) - (((v)>>1)&0x55555555), r = (r&0x33333333) + ((r>>2)&0x33333333), \\r
+     r = (((r + (r>>4))&0x0f0f0f0f) * 0x01010101)>>24)\r
+\r
 #define XB             MEM_LE4(0)\r
 #define XW             MEM_LE2(0)\r
 \r
@@ -525,13 +530,13 @@ static const s32 exception_cycle_table[256] =
         50, //  2: Bus Error\r
         50, //  3: Address Error\r
         34, //  4: Illegal Instruction\r
-        38, //  5: Divide by Zero\r
-        40, //  6: CHK\r
+        34, //  5: Divide by Zero\r
+        34, //  6: CHK\r
         34, //  7: TRAPV\r
         34, //  8: Privilege Violation\r
         34, //  9: Trace\r
-         4, // 10:\r
-         4, // 11:\r
+        34, // 10: Line A\r
+        34, // 11: Line F\r
          4, // 12: RESERVED\r
          4, // 13: Coprocessor Protocol Violation\r
          4, // 14: Format Error\r

diff --git a/cpu/fame/famec_opcodes.h b/cpu/fame/famec_opcodes.h
index ffb7c4e..d5b9a04 100644 (file)
--- a/cpu/fame/famec_opcodes.h
+++ b/cpu/fame/famec_opcodes.h
@@ -1074,11 +1074,7 @@ OPCODE(0x0280)
        flag_NotZ = res;
        flag_N = res >> 24;
        DREGu32((Opcode >> 0) & 7) = res;
-#ifdef USE_CYCLONE_TIMING
-RET(14)
-#else
 RET(16)
-#endif
 }
 
 // ANDI
@@ -1303,7 +1299,11 @@ OPCODE(0x027C)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(20)
 }
@@ -1953,7 +1953,11 @@ OPCODE(0x0A7C)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
                RET(0)
+#else
+               RET(4)
+#endif
        }
 RET(20)
 }
@@ -3904,7 +3908,12 @@ OPCODE(0x0840)
        flag_NotZ = res & src;
        res ^= src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(10)
+#else
 RET(12)
+#endif
 }
 
 // BCHGn
@@ -4087,7 +4096,12 @@ OPCODE(0x0880)
        flag_NotZ = res & src;
        res &= ~src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(12)
+#else
 RET(14)
+#endif
 }
 
 // BCLRn
@@ -4270,7 +4284,12 @@ OPCODE(0x08C0)
        flag_NotZ = res & src;
        res |= src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(10)
+#else
 RET(12)
+#endif
 }
 
 // BSETn
@@ -4663,7 +4682,12 @@ OPCODE(0x0140)
        flag_NotZ = res & src;
        res ^= src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(6)
+#else
 RET(8)
+#endif
 }
 
 // BCHG
@@ -4846,7 +4870,12 @@ OPCODE(0x0180)
        flag_NotZ = res & src;
        res &= ~src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(8)
+#else
 RET(10)
+#endif
 }
 
 // BCLR
@@ -5029,7 +5058,12 @@ OPCODE(0x01C0)
        flag_NotZ = res & src;
        res |= src;
        DREGu32((Opcode >> 0) & 7) = res;
+#ifdef USE_CYCLONE_TIMING
+       if (src >> 16) ctx->io_cycle_counter -= 2;
+RET(6)
+#else
 RET(8)
+#endif
 }
 
 // BSET
@@ -16571,7 +16605,11 @@ OPCODE(0x46C0)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(12)
 }
@@ -16600,7 +16638,11 @@ OPCODE(0x46D0)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(16)
 }
@@ -16630,7 +16672,11 @@ OPCODE(0x46D8)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(16)
 }
@@ -16660,7 +16706,11 @@ OPCODE(0x46E0)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(18)
 }
@@ -16690,7 +16740,11 @@ OPCODE(0x46E8)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(20)
 }
@@ -16720,7 +16774,11 @@ OPCODE(0x46F0)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(22)
 }
@@ -16750,7 +16808,11 @@ OPCODE(0x46F8)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(20)
 }
@@ -16779,7 +16841,11 @@ OPCODE(0x46F9)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(24)
 }
@@ -16809,7 +16875,11 @@ OPCODE(0x46FA)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(20)
 }
@@ -16839,7 +16909,11 @@ OPCODE(0x46FB)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(22)
 }
@@ -16865,7 +16939,11 @@ OPCODE(0x46FC)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(16)
 }
@@ -16895,7 +16973,11 @@ OPCODE(0x46DF)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(16)
 }
@@ -16925,7 +17007,11 @@ OPCODE(0x46E7)
        else
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+               RET(0)
+#else
                RET(4)
+#endif
        }
 RET(18)
 }
@@ -18327,7 +18413,7 @@ OPCODE(0x4AD0)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(18)
+RET(14)
 #else
 RET(8)
 #endif
@@ -18357,7 +18443,7 @@ OPCODE(0x4AD8)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(18)
+RET(14)
 #else
 RET(8)
 #endif
@@ -18387,7 +18473,7 @@ OPCODE(0x4AE0)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(20)
+RET(16)
 #else
 RET(10)
 #endif
@@ -18417,7 +18503,7 @@ OPCODE(0x4AE8)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(22)
+RET(18)
 #else
 RET(12)
 #endif
@@ -18447,7 +18533,7 @@ OPCODE(0x4AF0)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(24)
+RET(20)
 #else
 RET(14)
 #endif
@@ -18476,7 +18562,7 @@ OPCODE(0x4AF8)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(22)
+RET(18)
 #else
 RET(12)
 #endif
@@ -18505,7 +18591,7 @@ OPCODE(0x4AF9)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(26)
+RET(22)
 #else
 RET(16)
 #endif
@@ -18535,7 +18621,7 @@ OPCODE(0x4ADF)
 
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(18)
+RET(14)
 #else
 RET(8)
 #endif
@@ -18593,7 +18679,7 @@ RET(0)
 OPCODE(0xF000)
 {
        SET_PC(execute_exception(ctx, M68K_1111_EX, GET_PC-2, GET_SR));
-RET(0) // 4 already taken by exc. handler
+RET(0) 
 }
 
 // MOVEMaR
@@ -19154,7 +19240,11 @@ RET(12)
 OPCODE(0x4E40)
 {
        SET_PC(execute_exception(ctx, M68K_TRAP_BASE_EX + (Opcode & 0xF), GET_PC, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
 RET(4)
+#endif
 }
 
 // LINK
@@ -19225,7 +19315,11 @@ OPCODE(0x4E60)
        if (!flag_S)
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
                RET(4)
+#endif
        }
        res = AREGu32((Opcode >> 0) & 7);
        ASP = res;
@@ -19241,7 +19335,11 @@ OPCODE(0x4E68)
        if (!flag_S)
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
                RET(4)
+#endif
        }
        res = ASP;
        AREG((Opcode >> 0) & 7) = res;
@@ -19257,7 +19355,11 @@ OPCODE(0x4E70)
        if (!flag_S)
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
                RET(4)
+#endif
        }
        PRE_IO
        if (ctx->reset_handler) ctx->reset_handler();
@@ -19281,7 +19383,11 @@ OPCODE(0x4E72)
        if (!flag_S)
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
                RET(4)
+#endif
        }
        FETCH_WORD(res);
        res &= M68K_SR_MASK;
@@ -19305,7 +19411,11 @@ OPCODE(0x4E73)
        if (!flag_S)
        {
                SET_PC(execute_exception(ctx, M68K_PRIVILEGE_VIOLATION_EX, GET_PC-2, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#else
                RET(4)
+#endif
        }
        PRE_IO
        POP_16_F(res)
@@ -19342,8 +19452,12 @@ RET(16)
 // TRAPV
 OPCODE(0x4E76)
 {
-       if (flag_V & 0x80)
+       if (flag_V & 0x80) {
                SET_PC(execute_exception(ctx, M68K_TRAPV_EX, GET_PC, GET_SR));
+#ifdef USE_CYCLONE_TIMING
+RET(0)
+#endif
+       }
 RET(4)
 }
 
@@ -19606,6 +19720,7 @@ OPCODE(0x4180)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(4)
        }
 RET(10)
 }
@@ -19624,6 +19739,7 @@ OPCODE(0x4190)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(8)
        }
        POST_IO
 RET(14)
@@ -19644,6 +19760,7 @@ OPCODE(0x4198)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(8)
        }
        POST_IO
 RET(14)
@@ -19664,6 +19781,7 @@ OPCODE(0x41A0)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(10)
        }
        POST_IO
 RET(16)
@@ -19684,6 +19802,7 @@ OPCODE(0x41A8)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(12)
        }
        POST_IO
 RET(18)
@@ -19704,6 +19823,7 @@ OPCODE(0x41B0)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(14)
        }
        POST_IO
 RET(20)
@@ -19723,6 +19843,7 @@ OPCODE(0x41B8)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(12)
        }
        POST_IO
 RET(18)
@@ -19742,6 +19863,7 @@ OPCODE(0x41B9)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(16)
        }
        POST_IO
 RET(22)
@@ -19762,6 +19884,7 @@ OPCODE(0x41BA)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(12)
        }
        POST_IO
 RET(18)
@@ -19782,6 +19905,7 @@ OPCODE(0x41BB)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(14)
        }
        POST_IO
 RET(20)
@@ -19799,6 +19923,7 @@ OPCODE(0x41BC)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(8)
        }
        POST_IO
 RET(14)
@@ -19819,6 +19944,7 @@ OPCODE(0x419F)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(8)
        }
        POST_IO
 RET(14)
@@ -19839,6 +19965,7 @@ OPCODE(0x41A7)
        {
                flag_N = res >> 8;
                SET_PC(execute_exception(ctx, M68K_CHK_EX, GET_PC, GET_SR));
+RET(10)
        }
        POST_IO
 RET(16)
@@ -27099,9 +27226,9 @@ OPCODE(0x80C0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(140)
+RET(4)
 #else
-RET(10)
+RET(14)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27115,7 +27242,7 @@ RET(10)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(140)
+RET(10)
 #else
 RET(70)
 #endif
@@ -27126,12 +27253,12 @@ RET(70)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(140)
+RET(138-BITCOUNT(res,q)*2)
 #else
 RET(90)
 #endif
+       }
 }
 
 // DIVU
@@ -27147,9 +27274,9 @@ OPCODE(0x80D0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(8)
 #else
-RET(14)
+RET(18)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27163,7 +27290,7 @@ RET(14)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(14)
 #else
        RET(74)
 #endif
@@ -27174,12 +27301,12 @@ RET(144)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(142-BITCOUNT(res,q)*2)
 #else
 RET(94)
 #endif
+       }
 }
 
 // DIVU
@@ -27196,9 +27323,9 @@ OPCODE(0x80D8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(8)
 #else
-RET(14)
+RET(18)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27212,7 +27339,7 @@ RET(14)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(14)
 #else
        RET(74)
 #endif
@@ -27223,12 +27350,12 @@ RET(144)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(142-BITCOUNT(res,q)*2)
 #else
 RET(94)
 #endif
+       }
 }
 
 // DIVU
@@ -27245,9 +27372,9 @@ OPCODE(0x80E0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(10)
 #else
-RET(16)
+RET(20)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27261,7 +27388,7 @@ RET(16)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(16)
 #else
        RET(76)
 #endif
@@ -27272,12 +27399,12 @@ RET(146)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(144-BITCOUNT(res,q)*2)
 #else
 RET(96)
 #endif
+       }
 }
 
 // DIVU
@@ -27294,9 +27421,9 @@ OPCODE(0x80E8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(12)
 #else
-RET(18)
+RET(22)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27310,7 +27437,7 @@ RET(18)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(18)
 #else
        RET(78)
 #endif
@@ -27321,12 +27448,12 @@ RET(148)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(146-BITCOUNT(res,q)*2)
 #else
 RET(98)
 #endif
+       }
 }
 
 // DIVU
@@ -27343,9 +27470,9 @@ OPCODE(0x80F0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(14)
 #else
-RET(20)
+RET(24)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27359,7 +27486,7 @@ RET(20)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(20)
 #else
        RET(80)
 #endif
@@ -27370,12 +27497,12 @@ RET(150)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(148-BITCOUNT(res,q)*2)
 #else
 RET(100)
 #endif
+       }
 }
 
 // DIVU
@@ -27391,9 +27518,9 @@ OPCODE(0x80F8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(12)
 #else
-RET(18)
+RET(22)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27407,7 +27534,7 @@ RET(18)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(18)
 #else
        RET(78)
 #endif
@@ -27418,12 +27545,12 @@ RET(148)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(146-BITCOUNT(res,q)*2)
 #else
 RET(98)
 #endif
+       }
 }
 
 // DIVU
@@ -27439,9 +27566,9 @@ OPCODE(0x80F9)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(152)
+RET(16)
 #else
-RET(22)
+RET(26)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27455,7 +27582,7 @@ RET(22)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(152)
+RET(22)
 #else
        RET(82)
 #endif
@@ -27466,12 +27593,12 @@ RET(152)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(152)
+RET(150-BITCOUNT(res,q)*2)
 #else
 RET(102)
 #endif
+       }
 }
 
 // DIVU
@@ -27488,9 +27615,9 @@ OPCODE(0x80FA)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(12)
 #else
-RET(18)
+RET(22)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27504,7 +27631,7 @@ RET(18)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(18)
 #else
        RET(78)
 #endif
@@ -27515,12 +27642,12 @@ RET(148)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(148)
+RET(146-BITCOUNT(res,q)*2)
 #else
 RET(98)
 #endif
+       }
 }
 
 // DIVU
@@ -27537,9 +27664,9 @@ OPCODE(0x80FB)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(14)
 #else
-RET(20)
+RET(24)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27553,7 +27680,7 @@ RET(20)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(20)
 #else
        RET(80)
 #endif
@@ -27564,12 +27691,12 @@ RET(150)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(150)
+RET(148-BITCOUNT(res,q)*2)
 #else
 RET(100)
 #endif
+       }
 }
 
 // DIVU
@@ -27583,9 +27710,9 @@ OPCODE(0x80FC)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(8)
 #else
-RET(14)
+RET(18)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27599,7 +27726,7 @@ RET(14)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(14)
 #else
        RET(74)
 #endif
@@ -27610,12 +27737,12 @@ RET(144)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(142-BITCOUNT(res,q)*2)
 #else
 RET(94)
 #endif
+       }
 }
 
 // DIVU
@@ -27632,9 +27759,9 @@ OPCODE(0x80DF)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(8)
 #else
-RET(14)
+RET(18)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27648,7 +27775,7 @@ RET(14)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(14)
 #else
        RET(74)
 #endif
@@ -27659,12 +27786,12 @@ RET(144)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(144)
+RET(142-BITCOUNT(res,q)*2)
 #else
 RET(94)
 #endif
+       }
 }
 
 // DIVU
@@ -27681,9 +27808,9 @@ OPCODE(0x80E7)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(10)
 #else
-RET(16)
+RET(20)
 #endif
        }
        dst = DREGu32((Opcode >> 9) & 7);
@@ -27697,7 +27824,7 @@ RET(16)
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(16)
 #else
        RET(76)
 #endif
@@ -27708,12 +27835,12 @@ RET(146)
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-RET(146)
+RET(144-BITCOUNT(res,q)*2)
 #else
 RET(96)
 #endif
+       }
 }
 
 // DIVS
@@ -27727,9 +27854,10 @@ OPCODE(0x81C0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81C0;
+RET(4)
+#else
+               RET(14)
 #endif
-               RET(10)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -27739,9 +27867,10 @@ goto end81C0;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81C0;
-#endif
+RET(16+(dst>>31)*2)
+#else
        RET(50)
+#endif
        }
        {
                s32 q, r;
@@ -27753,9 +27882,12 @@ goto end81C0;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81C0;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(16+(dst>>31)*2)
+} else RET(152+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(80)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -27763,11 +27895,12 @@ goto end81C0;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81C0: ctx->io_cycle_counter -= 50;
-#endif
+RET(152+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(108)
+#endif
+       }
 }
 
 // DIVS
@@ -27783,9 +27916,10 @@ OPCODE(0x81D0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D0;
+RET(8)
+#else
+               RET(18)
 #endif
-               RET(14)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -27795,9 +27929,10 @@ goto end81D0;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D0;
-#endif
+RET(20+(dst>>31)*2)
+#else
        RET(54)
+#endif
        }
        {
                s32 q, r;
@@ -27809,9 +27944,12 @@ goto end81D0;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D0;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(20+(dst>>31)*2)
+} else RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(84)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -27819,11 +27957,12 @@ goto end81D0;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81D0: ctx->io_cycle_counter -= 50;
-#endif
+RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(112)
+#endif
+       }
 }
 
 // DIVS
@@ -27840,9 +27979,10 @@ OPCODE(0x81D8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D8;
+RET(8)
+#else
+               RET(18)
 #endif
-               RET(14)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -27852,9 +27992,10 @@ goto end81D8;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D8;
-#endif
+RET(20+(dst>>31)*2)
+#else
        RET(54)
+#endif
        }
        {
                s32 q, r;
@@ -27866,9 +28007,12 @@ goto end81D8;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81D8;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(20+(dst>>31)*2)
+} else RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(84)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -27876,11 +28020,12 @@ goto end81D8;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81D8: ctx->io_cycle_counter -= 50;
-#endif
+RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(112)
+#endif
+       }
 }
 
 // DIVS
@@ -27897,9 +28042,10 @@ OPCODE(0x81E0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E0;
+RET(10)
+#else
+               RET(20)
 #endif
-               RET(16)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -27909,9 +28055,10 @@ goto end81E0;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E0;
-#endif
+RET(22+(dst>>31)*2)
+#else
        RET(56)
+#endif
        }
        {
                s32 q, r;
@@ -27923,9 +28070,12 @@ goto end81E0;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E0;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(22+(dst>>31)*2)
+} else RET(158+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(86)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -27933,11 +28083,12 @@ goto end81E0;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81E0: ctx->io_cycle_counter -= 50;
-#endif
+RET(158+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(114)
+#endif
+       }
 }
 
 // DIVS
@@ -27954,9 +28105,10 @@ OPCODE(0x81E8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E8;
+RET(12)
+#else
+               RET(22)
 #endif
-               RET(18)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -27966,9 +28118,10 @@ goto end81E8;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E8;
-#endif
+RET(24+(dst>>31)*2)
+#else
        RET(58)
+#endif
        }
        {
                s32 q, r;
@@ -27980,9 +28133,12 @@ goto end81E8;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E8;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(24+(dst>>31)*2)
+} else RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(88)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -27990,11 +28146,12 @@ goto end81E8;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81E8: ctx->io_cycle_counter -= 50;
-#endif
+RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(116)
+#endif
+       }
 }
 
 // DIVS
@@ -28011,9 +28168,10 @@ OPCODE(0x81F0)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F0;
+RET(14)
+#else
+               RET(24)
 #endif
-               RET(20)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28023,9 +28181,10 @@ goto end81F0;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F0;
-#endif
+RET(26+(dst>>31)*2)
+#else
        RET(60)
+#endif
        }
        {
                s32 q, r;
@@ -28037,9 +28196,12 @@ goto end81F0;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F0;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(26+(dst>>31)*2)
+} else RET(162+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(90)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28047,11 +28209,12 @@ goto end81F0;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81F0: ctx->io_cycle_counter -= 50;
-#endif
+RET(162+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(118)
+#endif
+       }
 }
 
 // DIVS
@@ -28067,9 +28230,10 @@ OPCODE(0x81F8)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F8;
+RET(12)
+#else
+               RET(22)
 #endif
-               RET(18)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28079,9 +28243,10 @@ goto end81F8;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F8;
-#endif
+RET(24+(dst>>31)*2)
+#else
        RET(58)
+#endif
        }
        {
                s32 q, r;
@@ -28093,9 +28258,12 @@ goto end81F8;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F8;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(24+(dst>>31)*2)
+} else RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(88)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28103,11 +28271,12 @@ goto end81F8;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81F8: ctx->io_cycle_counter -= 50;
-#endif
+RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(116)
+#endif
+       }
 }
 
 // DIVS
@@ -28123,9 +28292,10 @@ OPCODE(0x81F9)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F9;
+RET(16)
+#else
+               RET(26)
 #endif
-               RET(22)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28135,9 +28305,10 @@ goto end81F9;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F9;
-#endif
+RET(28+(dst>>31)*2)
+#else
        RET(62)
+#endif
        }
        {
                s32 q, r;
@@ -28149,9 +28320,12 @@ goto end81F9;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81F9;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(28+(dst>>31)*2)
+} else RET(164+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(92)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28159,11 +28333,12 @@ goto end81F9;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81F9: ctx->io_cycle_counter -= 50;
-#endif
+RET(164+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(120)
+#endif
+       }
 }
 
 // DIVS
@@ -28180,9 +28355,10 @@ OPCODE(0x81FA)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FA;
+RET(12)
+#else
+               RET(22)
 #endif
-               RET(18)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28192,9 +28368,10 @@ goto end81FA;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FA;
-#endif
+RET(24+(dst>>31)*2)
+#else
        RET(58)
+#endif
        }
        {
                s32 q, r;
@@ -28206,9 +28383,12 @@ goto end81FA;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FA;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(24+(dst>>31)*2)
+} else RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(88)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28216,11 +28396,12 @@ goto end81FA;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81FA: ctx->io_cycle_counter -= 50;
-#endif
+RET(160+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(116)
+#endif
+       }
 }
 
 // DIVS
@@ -28237,9 +28418,10 @@ OPCODE(0x81FB)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FB;
+RET(14)
+#else
+               RET(24)
 #endif
-               RET(20)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28249,9 +28431,10 @@ goto end81FB;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FB;
-#endif
+RET(26+(dst>>31)*2)
+#else
        RET(60)
+#endif
        }
        {
                s32 q, r;
@@ -28263,9 +28446,12 @@ goto end81FB;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FB;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(26+(dst>>31)*2)
+} else RET(162+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(90)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28273,11 +28459,12 @@ goto end81FB;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81FB: ctx->io_cycle_counter -= 50;
-#endif
+RET(162+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(118)
+#endif
+       }
 }
 
 // DIVS
@@ -28291,9 +28478,10 @@ OPCODE(0x81FC)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FC;
+RET(8)
+#else
+               RET(18)
 #endif
-               RET(14)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28303,9 +28491,10 @@ goto end81FC;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FC;
-#endif
+RET(20+(dst>>31)*2)
+#else
        RET(54)
+#endif
        }
        {
                s32 q, r;
@@ -28317,9 +28506,12 @@ goto end81FC;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81FC;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(20+(dst>>31)*2)
+} else RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(84)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28327,11 +28519,12 @@ goto end81FC;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81FC: ctx->io_cycle_counter -= 50;
-#endif
+RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(112)
+#endif
+       }
 }
 
 // DIVS
@@ -28348,9 +28541,10 @@ OPCODE(0x81DF)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81DF;
+RET(8)
+#else
+               RET(18)
 #endif
-               RET(14)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28360,9 +28554,10 @@ goto end81DF;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81DF;
-#endif
+RET(20+(dst>>31)*2)
+#else
        RET(54)
+#endif
        }
        {
                s32 q, r;
@@ -28374,9 +28569,12 @@ goto end81DF;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81DF;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(20+(dst>>31)*2)
+} else RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(84)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28384,11 +28582,12 @@ goto end81DF;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81DF: ctx->io_cycle_counter -= 50;
-#endif
+RET(156+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(112)
+#endif
+       }
 }
 
 // DIVS
@@ -28405,9 +28604,10 @@ OPCODE(0x81E7)
        {
                SET_PC(execute_exception(ctx, M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E7;
+RET(10)
+#else
+               RET(20)
 #endif
-               RET(16)
        }
        dst = DREGu32((Opcode >> 9) & 7);
        if ((dst == 0x80000000) && (src == (u32)-1))
@@ -28417,9 +28617,10 @@ goto end81E7;
                res = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E7;
-#endif
+RET(22+(dst>>31)*2)
+#else
        RET(56)
+#endif
        }
        {
                s32 q, r;
@@ -28431,9 +28632,12 @@ goto end81E7;
                {
                        flag_V = M68K_SR_V;
 #ifdef USE_CYCLONE_TIMING_DIV
-goto end81E7;
-#endif
+if (q > 0xFFFF || q < -0x10000) {
+       RET(22+(dst>>31)*2)
+} else RET(158+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
        RET(86)
+#endif
                }
                q &= 0x0000FFFF;
                flag_NotZ = q;
@@ -28441,11 +28645,12 @@ goto end81E7;
                flag_V = flag_C = 0;
                res = q | (r << 16);
        DREGu32((Opcode >> 9) & 7) = res;
-       }
 #ifdef USE_CYCLONE_TIMING_DIV
-end81E7: ctx->io_cycle_counter -= 50;
-#endif
+RET(158+(dst>>31)*4+((src^dst)>>31)*2-BITCOUNT(res,abs(q))*2)
+#else
 RET(114)
+#endif
+       }
 }
 
 // SUBaD
@@ -34309,7 +34514,7 @@ OPCODE(0xC0C0)
        flag_V = flag_C = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING
-RET(54)
+RET(38+BITCOUNT(res,src)*2)
 #else
 RET(50)
 #endif
@@ -34332,7 +34537,7 @@ OPCODE(0xC0D0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src)*2)
 #else
 RET(54)
 #endif
@@ -34356,7 +34561,7 @@ OPCODE(0xC0D8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src)*2)
 #else
 RET(54)
 #endif
@@ -34380,7 +34585,7 @@ OPCODE(0xC0E0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(60)
+RET(44+BITCOUNT(res,src)*2)
 #else
 RET(56)
 #endif
@@ -34404,7 +34609,7 @@ OPCODE(0xC0E8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src)*2)
 #else
 RET(58)
 #endif
@@ -34428,7 +34633,7 @@ OPCODE(0xC0F0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(64)
+RET(48+BITCOUNT(res,src)*2)
 #else
 RET(60)
 #endif
@@ -34451,7 +34656,7 @@ OPCODE(0xC0F8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src)*2)
 #else
 RET(58)
 #endif
@@ -34474,7 +34679,7 @@ OPCODE(0xC0F9)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(66)
+RET(50+BITCOUNT(res,src)*2)
 #else
 RET(62)
 #endif
@@ -34498,7 +34703,7 @@ OPCODE(0xC0FA)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src)*2)
 #else
 RET(58)
 #endif
@@ -34522,7 +34727,7 @@ OPCODE(0xC0FB)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(64)
+RET(48+BITCOUNT(res,src)*2)
 #else
 RET(60)
 #endif
@@ -34542,7 +34747,7 @@ OPCODE(0xC0FC)
        flag_V = flag_C = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src)*2)
 #else
 RET(54)
 #endif
@@ -34566,7 +34771,7 @@ OPCODE(0xC0DF)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src)*2)
 #else
 RET(54)
 #endif
@@ -34590,7 +34795,7 @@ OPCODE(0xC0E7)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(60)
+RET(44+BITCOUNT(res,src)*2)
 #else
 RET(56)
 #endif
@@ -34610,7 +34815,7 @@ OPCODE(0xC1C0)
        flag_V = flag_C = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING
-RET(54)
+RET(38+BITCOUNT(res,src^(src<<1)))
 #else
 RET(50)
 #endif
@@ -34633,7 +34838,7 @@ OPCODE(0xC1D0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(54)
 #endif
@@ -34657,7 +34862,7 @@ OPCODE(0xC1D8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(54)
 #endif
@@ -34681,7 +34886,7 @@ OPCODE(0xC1E0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(60)
+RET(44+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(56)
 #endif
@@ -34705,7 +34910,7 @@ OPCODE(0xC1E8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(58)
 #endif
@@ -34729,7 +34934,7 @@ OPCODE(0xC1F0)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(64)
+RET(48+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(60)
 #endif
@@ -34752,7 +34957,7 @@ OPCODE(0xC1F8)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(58)
 #endif
@@ -34775,7 +34980,7 @@ OPCODE(0xC1F9)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(66)
+RET(50+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(62)
 #endif
@@ -34799,7 +35004,7 @@ OPCODE(0xC1FA)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(62)
+RET(46+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(58)
 #endif
@@ -34823,7 +35028,7 @@ OPCODE(0xC1FB)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(64)
+RET(48+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(60)
 #endif
@@ -34843,7 +35048,7 @@ OPCODE(0xC1FC)
        flag_V = flag_C = 0;
        DREGu32((Opcode >> 9) & 7) = res;
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(54)
 #endif
@@ -34867,7 +35072,7 @@ OPCODE(0xC1DF)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(58)
+RET(42+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(54)
 #endif
@@ -34891,7 +35096,7 @@ OPCODE(0xC1E7)
        DREGu32((Opcode >> 9) & 7) = res;
        POST_IO
 #ifdef USE_CYCLONE_TIMING
-RET(60)
+RET(44+BITCOUNT(res,src^(src<<1))*2)
 #else
 RET(56)
 #endif