#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
SekRunM68k(m68k_cycles); \
+ if (Pico32x.emu_flags & P32XF_Z80_32X_IO) \
+ PicoSyncZ80(SekCycleCnt); \
if (Pico32x.emu_flags & (P32XF_68KCPOLL|P32XF_68KVPOLL)) \
p32x_sync_sh2s(SekCyclesDoneT2()); \
} while (0)
m68k_poll.cnt = 0;
dr2 = SekDar(2);
- if (cycles - msh2.m68krcycles_done > 500)
+ if (cycles - msh2.m68krcycles_done > 244
+ || (Pico32x.comm_dirty_68k & comreg))
p32x_sync_sh2s(cycles);
+
if (Pico32x.comm_dirty_sh2 & comreg)
Pico32x.comm_dirty_sh2 &= ~comreg;
else if (m68k_poll_detect(a, cycles, P32XF_68KCPOLL)) {
// -----------------------------------------------------------------
+static void z80_md_bank_write_32x(unsigned int a, unsigned char d)
+{
+ unsigned int addr68k;
+
+ addr68k = Pico.m.z80_bank68k << 15;
+ addr68k += a & 0x7fff;
+ if ((addr68k & 0xfff000) == 0xa15000)
+ Pico32x.emu_flags |= P32XF_Z80_32X_IO;
+
+ elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, d);
+ m68k_write8(addr68k, d);
+}
+
+// -----------------------------------------------------------------
+
static const u16 msh2_code[] = {
// trap instructions
0xaffe, // bra <self>
sh2_drc_mem_setup(&msh2);
sh2_drc_mem_setup(&ssh2);
+
+ // z80 hack
+ z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write_32x, 1);
}
void Pico32xMemStateLoaded(void)
#define P32XP_FULL (1<<15) // PWM pulse\r
#define P32XP_EMPTY (1<<14)\r
\r
-#define P32XF_68KCPOLL (1 << 0)\r
-#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_68KCPOLL (1 << 0)\r
+#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r