idl_src = CPU_BE2(*(u32 *)(Pico.rom + 0x3d4)) & ~0xf0000000;
idl_dst = CPU_BE2(*(u32 *)(Pico.rom + 0x3d8)) & ~0xf0000000;
idl_size= CPU_BE2(*(u32 *)(Pico.rom + 0x3dc));
- if (idl_size > Pico.romsize || idl_src + idl_size > Pico.romsize ||
- idl_size > 0x40000 || idl_dst + idl_size > 0x40000 || (idl_src & 3) || (idl_dst & 3)) {
- elprintf(EL_STATUS|EL_ANOMALY, "32x: invalid initial data ptrs: %06x -> %06x, %06x",
- idl_src, idl_dst, idl_size);
+ // copy in guest memory space
+ idl_src += 0x2000000;
+ idl_dst += 0x6000000;
+ while (idl_size >= 4) {
+ p32x_sh2_write32(idl_dst, p32x_sh2_read32(idl_src, &msh2), &msh2);
+ idl_src += 4, idl_dst += 4, idl_size -= 4;
}
- else
- memcpy(Pico32xMem->sdram + idl_dst, Pico.rom + idl_src, idl_size);
// VBR
vbr = CPU_BE2(*(u32 *)(Pico.rom + 0x3e8));
msh2_write32_map[0x00/2] = msh2_write32_map[0x20/2] = sh2_write32_cs0;
// CS1 - ROM
bank_switch_rom_sh2();
- msh2_read8_map[0x02/2].mask = msh2_read8_map[0x22/2].mask = 0x3fffff; // FIXME
- msh2_read16_map[0x02/2].mask = msh2_read16_map[0x22/2].mask = 0x3ffffe; // FIXME
- msh2_read32_map[0x02/2].mask = msh2_read32_map[0x22/2].mask = 0x3ffffc; // FIXME
+ for (rs = 0x8000; rs < Pico.romsize && rs < 0x400000; rs *= 2) ;
+ msh2_read8_map[0x02/2].mask = msh2_read8_map[0x22/2].mask = rs-1;
+ msh2_read16_map[0x02/2].mask = msh2_read16_map[0x22/2].mask = rs-1;
+ msh2_read32_map[0x02/2].mask = msh2_read32_map[0x22/2].mask = rs-1;
msh2_write16_map[0x02/2] = msh2_write16_map[0x22/2] = sh2_write16_rom;
msh2_write32_map[0x02/2] = msh2_write32_map[0x22/2] = sh2_write32_rom;
// CS2 - DRAM