core vdp, fix status for very short DMA transfers

diff --git a/pico/videoport.c b/pico/videoport.c
index 710c0ba..defbf3e 100644 (file)
--- a/pico/videoport.c
+++ b/pico/videoport.c
@@ -536,6 +536,9 @@ static void DmaSlow(int len, u32 source)
 \r
   SekCyclesBurnRun(PicoVideoFIFOWrite(len, FQ_FGDMA | (pvid->type == 1),\r
                               PVS_DMABG, SR_DMA | PVS_CPUWR));\r
+  // short transfers might have been completely conveyed to FIFO, adjust state\r
+  if ((pvid->status & SR_DMA) && VdpFIFO.fifo_total <= 4)\r
+    SetFIFOState(&VdpFIFO, pvid);\r
 \r
   if ((source & 0xe00000) == 0xe00000) { // Ram\r
     base = (u16 *)PicoMem.ram;\r
@@ -895,7 +898,7 @@ PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d)
       // the vertical scroll value for this line must be read from VSRAM early,\r
       // since the A/B tile row to be read depends on it. E.g. Skitchin, OD2\r
       // in contrast, CRAM writes would have an immediate effect on the current\r
-      // pixel. XXX think about different offset values for different RAM types\r
+      // pixel, so sync can be closer to start of actual image data\r
       PicoVideoSync(InHblank(pvid->type == 3 ? 103 : 30)); // cram in Toy Story\r
 \r
     if (!(PicoIn.opt&POPT_DIS_VDP_FIFO))\r