// each entry has 2 values: [n]>>3 = #writes, [n]&7 = flags\r
static int fifo_queue[8], fifo_qx, fifo_ql; // XXX must go into save?\r
enum { FQ_BYTE = 1, FQ_BGDMA = 2, FQ_FGDMA = 4 }; // queue flags, NB: BYTE = 1!\r
-unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)\r
+static unsigned int fifo_total; // total# of pending FIFO entries (w/o BGDMA)\r
\r
-unsigned short fifo_slot; // last executed slot in current scanline\r
+static unsigned short fifo_slot; // last executed slot in current scanline\r
\r
// map cycles to FIFO slot\r
static __inline int GetFIFOSlot(struct PicoVideo *pv, int cycles)\r
}\r
\r
// switch FIFO mode between active/inactive display\r
-void PicoVideoFIFOMode(int active)\r
+static void PicoVideoFIFOMode(int active)\r
{\r
struct PicoVideo *pv = &Pico.video;\r
int h40 = pv->reg[12] & 1;\r
if (pvid->status & SR_DMA) {\r
elprintf(EL_VDPDMA, "Dma overlap, left=%d @ %06x",\r
fifo_total, SekPc);\r
- fifo_total = fifo_ql = 0;\r
+ pvid->fifo_cnt = fifo_total = fifo_ql = 0;\r
}\r
\r
len = GetDmaLength();\r
\r
// account for all outstanding xfers XXX kludge, entry attr's not saved\r
for (l = fifo_ql, x = fifo_qx + l-1; l > 1; l--, x--)\r
- pv->fifo_cnt += (fifo_queue[x&7] >> 2) << (fifo_queue[x&7] & FQ_BYTE);\r
+ pv->fifo_cnt += (fifo_queue[x&7] >> 3) << (fifo_queue[x&7] & FQ_BYTE);\r
}\r
\r
void PicoVideoLoad(void)\r