}
}
-// if !nested_call, must sync CPUs before calling this
-void p32x_update_irls(SH2 *active_sh2)
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles)
{
int irqs, mlvl = 0, slvl = 0;
- int m68k_cycles = 0;
int mrun, srun;
if (active_sh2 != NULL)
{
if (PicoAHW & PAHW_32X) {
Pico32x.sh2irqs |= P32XI_VRES;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCyclesDoneT2());
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, 0);
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, 0);
p32x_pwm_ctl_changed();
}
Pico32x.sh2irqs |= P32XI_VINT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCyclesDoneT2());
p32x_sh2_poll_event(&msh2, SH2_STATE_VPOLL, 0);
p32x_sh2_poll_event(&ssh2, SH2_STATE_VPOLL, 0);
}
SekCycleCnt = 0;
sh2s[0].m68krcycles_done = sh2s[1].m68krcycles_done = SekCycleCntT;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, SekCycleCntT);
p32x_pwm_state_loaded();
run_events(SekCycleCntT);
}
r[0] = (r[0] & ~P32XS_nRES) | (d & P32XS_nRES);
return;
case 3: // irq ctl
- if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ if ((d & 1) != !!(Pico32x.sh2irqi[0] & P32XI_CMD)) {
p32x_sync_sh2s(SekCyclesDoneT());
- Pico32x.sh2irqi[0] |= P32XI_CMD;
- p32x_update_irls(NULL);
+ if (d & 1)
+ Pico32x.sh2irqi[0] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[0] &= ~P32XI_CMD;
+ p32x_update_irls(NULL, SekCyclesDoneT2());
}
- if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ if (!!(d & 2) != !!(Pico32x.sh2irqi[1] & P32XI_CMD)) {
p32x_sync_sh2s(SekCyclesDoneT());
- Pico32x.sh2irqi[1] |= P32XI_CMD;
- p32x_update_irls(NULL);
+ if (d & 2)
+ Pico32x.sh2irqi[1] |= P32XI_CMD;
+ else
+ Pico32x.sh2irqi[1] &= ~P32XI_CMD;
+ p32x_update_irls(NULL, SekCyclesDoneT2());
}
return;
case 5: // bank
Pico32x.sh2_regs[0] |= d & 0x80;
if (d & 1)
p32x_pwm_schedule_sh2(&sh2s[cpuid]);
- p32x_update_irls(&sh2s[cpuid]);
+ p32x_update_irls(&sh2s[cpuid], 0);
return;
case 5: // H count
d &= 0xff;
return;
irls:
- p32x_update_irls(&sh2s[cpuid]);
+ p32x_update_irls(&sh2s[cpuid], 0);
}
// ------------------------------------------------------------------
static void do_pwm_irq(unsigned int m68k_cycles)
{
Pico32x.sh2irqs |= P32XI_PWM;
- p32x_update_irls(NULL);
+ p32x_update_irls(NULL, m68k_cycles);
if (Pico32x.regs[0x30 / 2] & P32XP_RTP) {
p32x_event_schedule(m68k_cycles, P32X_EVENT_PWM, pwm_cycles / 3 + 1);
void Pico32xStateLoaded(int is_early);\r
void p32x_sync_sh2s(unsigned int m68k_target);\r
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
-void p32x_update_irls(SH2 *active_sh2);\r
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
void p32x_reset_sh2s(void);\r
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r