core, fix for vdp save/load regression

diff --git a/pico/videoport.c b/pico/videoport.c
index a667e9c..72735a6 100644 (file)
--- a/pico/videoport.c
+++ b/pico/videoport.c
@@ -1157,10 +1157,10 @@ void PicoVideoLoad(void)
   }\r
   // make an entry in the FIFO if there are outstanding transfers\r
   vf->fifo_ql = vf->fifo_qx = vf->fifo_total = 0;\r
+  vf->fifo_cnt = pv->fifo_cnt;\r
   if (pv->fifo_cnt) {\r
     int wc = (pv->fifo_cnt + b) >> b;\r
     pv->status |= PVS_FIFORUN|PVS_CPUWR;\r
-    vf->fifo_cnt = pv->fifo_cnt;\r
     if (!(pv->status & PVS_DMABG))\r
       vf->fifo_total = wc;\r
     if ((pv->status & SR_DMA) && !(pv->status & PVS_DMAFILL))\r