if (mrun) {
p32x_sh2_poll_event(&msh2, SH2_IDLE_STATES, m68k_cycles);
if (msh2.state & SH2_STATE_RUN)
- sh2_end_run(&msh2, 1);
+ sh2_end_run(&msh2, 0);
}
srun = sh2_irl_irq(&ssh2, slvl, ssh2.state & SH2_STATE_RUN);
if (srun) {
p32x_sh2_poll_event(&ssh2, SH2_IDLE_STATES, m68k_cycles);
if (ssh2.state & SH2_STATE_RUN)
- sh2_end_run(&ssh2, 1);
+ sh2_end_run(&ssh2, 0);
}
elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
left_to_next = C_M68K_TO_SH2(sh2, (int)(event_time_next - now));
if (sh2_cycles_left(sh2) > left_to_next) {
if (left_to_next < 1)
- left_to_next = 1;
+ left_to_next = 0;
sh2_end_run(sh2, left_to_next);
}
}
left_to_event = C_M68K_TO_SH2(sh2, (int)(event_time_next - m68k_target));
if (sh2_cycles_left(sh2) > left_to_event) {
if (left_to_event < 1)
- left_to_event = 1;
+ left_to_event = 0;
sh2_end_run(sh2, left_to_event);
}
}
sh2->state, sh2->state | flags);
sh2->state |= flags;
- sh2_end_run(sh2, 1);
+ sh2_end_run(sh2, 0);
pevt_log_sh2(sh2, EVT_POLL_START);
#ifdef DRC_SH2
// mark this as an address used for polling if SDRAM
p32x_m68k_poll_event(P32XF_68KCPOLL);
p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
- sh2_end_run(sh2, 1);
+ sh2_end_run(sh2, 0);
sh2_poll_write(a & ~1, r[a / 2], cycles, sh2);
}
return;
p32x_m68k_poll_event(P32XF_68KCPOLL);
p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL, cycles);
if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
- sh2_end_run(sh2, 1);
+ sh2_end_run(sh2, 0);
sh2_poll_write(a, d, cycles, sh2);
}
return;
sh2_poll_write(a, d, cycles, sh2);
p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_RPOLL, cycles);
if (p32x_sh2_ready(sh2->other_sh2, cycles+8))
- sh2_end_run(sh2, 1);
+ sh2_end_run(sh2, 0);
DRC_RESTORE_SR(sh2);
}