core, add TH pad pin latency (load state regression)

diff --git a/pico/memory.c b/pico/memory.c
index 2ca6f2c..e76082a 100644 (file)
--- a/pico/memory.c
+++ b/pico/memory.c
@@ -314,7 +314,7 @@ static port_read_func *port_readers[3] = {
   read_nothing\r
 };\r
 \r
-static int padTHLatency[3];\r
+static int padTHLatency[3]; // TODO this should be in the save file structures\r
 \r
 static NOINLINE u32 port_read(int i)\r
 {\r
@@ -329,6 +329,8 @@ static NOINLINE u32 port_read(int i)
   // Decap Attack reportedly doesn't work on Nomad but works on must\r
   // other MD revisions (different pull-up strength?).\r
   u32 mask = 0x3f;\r
+  if (CYCLES_GE(padTHLatency[i], SekCyclesDone()+100))\r
+    padTHLatency[i] = SekCyclesDone(); // kludge to cope with cycle wrap\r
   if (CYCLES_GE(SekCyclesDone(), padTHLatency[i])) {\r
     mask |= 0x40;\r
     padTHLatency[i] = SekCyclesDone();\r
@@ -413,10 +415,10 @@ NOINLINE void io_ports_write(u32 a, u32 d)
 \r
   // after switching TH to input there's a latency before the pullup value is \r
   // read back as input (see Decap Attack, not in Samurai Showdown, 32x WWF Raw)\r
-  if (a >= 4 && a <= 5) {\r
-    padTHLatency[a - 4] = SekCyclesDone(); // if output, effective immediately\r
+  if (4 <= a && a <= 5) {\r
     if ((PicoMem.ioports[a] & 0x40) && !(d & 0x40))\r
-      padTHLatency[a - 4] += 25; // latency after switching to input\r
+      // latency after switching to input\r
+      padTHLatency[a - 4] = SekCyclesDone() + 25;\r
   }\r
 \r
   // certain IO ports can be used as RAM\r