sh2 drc, MIPS cache maintenance optimisation

diff --git a/Makefile b/Makefile
index 989b9b6..b4f94cb 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -46,7 +46,6 @@ CFLAGS += -finline-limit=42 -fno-unroll-loops -fno-ipa-cp -ffast-math
 # this gets you about 20% better execution speed on 32bit arm/mips
 CFLAGS += -fno-common -fno-stack-protector -fno-guess-branch-probability -fno-caller-saves -fno-tree-loop-if-convert -fno-regmove
 endif
-#OBJS += align.o
 
 # default settings
 ifeq "$(ARCH)" "arm"
@@ -83,8 +82,14 @@ $(TARGET).opk: $(TARGET)
        $(STRIP) .opk_data/PicoDrive
        mksquashfs .opk_data $@ -all-root -noappend -no-exports -no-xattrs
 
+all: opk
+
 OBJS += platform/opendingux/inputmap.o
 
+ifneq (,$(filter %__GCW0__ %__RG350__, $(CFLAGS)))
+CFLAGS += -DMIPS_USE_SYNCI # clear_cache uses SYNCI instead of a syscall
+endif
+
 # OpenDingux is a generic platform, really.
 PLATFORM := generic
 endif

diff --git a/README.md b/README.md
index 86da98e..90d2648 100644 (file)
--- a/README.md
+++ b/README.md
@@ -40,9 +40,7 @@ For gp2x, wiz, and caanoo you may need to compile libpng first.
 
 After configure, compile with
 
-> make opk # for opendingux and gcw0
-> 
-> make # for anything else
+> make
 
 ### helix MP3 decoder
 

diff --git a/cpu/drc/emit_mips.c b/cpu/drc/emit_mips.c
index 38ee569..51509ea 100644 (file)
--- a/cpu/drc/emit_mips.c
+++ b/cpu/drc/emit_mips.c
@@ -1562,12 +1562,36 @@ static int emith_cond_check(int cond, int *r)
 // emitter ABI stuff
 #define emith_pool_check()     /**/
 #define emith_pool_commit(j)   /**/
-// NB: mips32r2 has SYNCI
-#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
 #define        emith_update_cache()    /**/
 #define emith_rw_offs_max()    0x7fff
 #define emith_uext_ptr(r)      /**/
 
+#if __mips_isa_rev >= 2 && defined(MIPS_USE_SYNCI) && defined(__GNUC__)
+// this should normally be in libc clear_cache; however, it sometimes isn't.
+// core function taken from SYNCI description, MIPS32 instruction set manual
+static NOINLINE void host_instructions_updated(void *base, void *end, int force)
+{
+       int step, tmp;
+       asm volatile(
+       "       bal     0f;" // needed to allow for jr.hb
+       "       b       3f;"
+
+       "0:     rdhwr   %2, $1;"
+       "       beqz    %2, 2f;"
+
+       "1:     synci   0(%0);"
+       "       sltu    %3, %0, %1;"
+       "       addu    %0, %0, %2;"
+       "       bnez    %3, 1b;"
+
+       "       sync;"
+       "2:     jr.hb   $ra;"
+       "3:     " : "+r"(base), "+r"(end), "=r"(step), "=r"(tmp) :: "$31");
+}
+#else
+#define host_instructions_updated(base, end, force) __builtin___clear_cache(base, end)
+#endif
+
 // SH2 drc specific
 #define emith_sh2_drc_entry() do { \
        int _c, _z = PTR_SIZE; u32 _m = 0xd0ff0000; \