core vdp, fix display enable in hblank

diff --git a/pico/videoport.c b/pico/videoport.c
index defbf3e..79ee508 100644 (file)
--- a/pico/videoport.c
+++ b/pico/videoport.c
@@ -23,7 +23,8 @@ enum { clkdiv = 2 };    // CPU clock granularity: one of 1,2,4,8
 // Slot clock is sysclock/20 for h32 and sysclock/16 for h40.\r
 // One scanline is 63.7us/64.3us (ntsc/pal) long which is ~488.57 68k cycles.\r
 // Approximate by 488 for VDP.\r
-// 1 slot is 488/171 = 2.8538 68k cycles in h32, and 488/210 = 2.3238 in h40.\r
+// 1 slot is 20/7 = 2.857 68k cycles in h32, and 16/7 = 2.286 in h40. That's\r
+// 171 slots in h32, and ~213.8 (really 193 plus 17 prolonged in HSYNC) in h40.\r
 enum { slcpu = 488 };\r
 \r
 // VDP has a slot counter running from 0x00 to 0xff every scanline, but it has\r
@@ -952,11 +953,13 @@ PICO_INTERNAL_ASM void PicoVideoWrite(u32 a,unsigned short d)
 \r
         if (num == 1 && ((pvid->reg[1]^d)&0x40)) {\r
           // handle line blanking before line rendering. Only the last switch\r
-          // before the 1st sync for other reasons is honoured.\r
-          PicoVideoSync(1);\r
-          lineenabled = (d&0x40) ? Pico.m.scanline : -1;\r
-          linedisabled = (d&0x40) ? -1 : Pico.m.scanline;\r
-          lineoffset = SekCyclesDone() - Pico.t.m68c_line_start;\r
+          // before the 1st sync for other reasons is honoured. Switching after\r
+          // active area is on next line\r
+          int skip = InHblank(470); // Deadly Moves\r
+          PicoVideoSync(skip);\r
+          lineenabled = (d&0x40) ? Pico.m.scanline + !skip: -1;\r
+          linedisabled = (d&0x40) ? -1 : Pico.m.scanline + !skip;\r
+          lineoffset = (skip ? SekCyclesDone() - Pico.t.m68c_line_start : 0);\r
         } else if (((1<<num) & 0x738ff) && pvid->reg[num] != d)\r
           // VDP regs 0-7,11-13,16-18 influence rendering, ignore all others\r
           PicoVideoSync(InHblank(93)); // Toy Story\r